Make the watchdog notice also fine-grained changes within a single
pushbuffer - by tracking just the gpfifo get, the watchdog could wake
when the channel hasn't really been stuck but processing a relatively
large or slow pushbuf.
Jira NVGPU-72
Change-Id: I15374eea5d9abc9d3725a79d0b960503237e478c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1485919
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clk_gm20b.c has number of calls specific to linux and
tegra-soc environment
In order to unify the driver, move all of those calls
to tegra/linux specific file tegra/linux/clk.c
All the clk_*() and tegra_dvfs_*() calls are now
abstracted behind GPU's clock operations and shoule be
accessed using g->ops.clk.<API> format
Remove <linux/clk.h> and <soc/tegra/tegra-dvfs.h> from
clk_gm20b.c
Remove <linux/version.h> from clk_gm20b.c too since
we only support k4.4 and higher version only
Jira NVGPU-49
Change-Id: Ib26811e0423bbd3868b9a46e662b80a8ca088dc5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483092
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Add the following ioctls
- NVGPU_CHANNEL_IOCTL_GET_TIMESLICE for channel timeslice in us
- NVGPU_TSG_IOCTL_GET_TIMESLICE for TSG timeslice in us
If timeslice has not been set explicitly, ioctl returns the
default timeslice that will be used when programming the runlist
entry.
Bug 1883271
Change-Id: Ib18fdd836323b1a2d4efceb1e27d07713bd6fca5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1469040
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Remove gk20a_platform dependencies from gk20a.h. This makes
gk20a_platform a Linux platform specific data structure. Add #include
for platform_gk20a.h in the source files that still depend on Linux.
JIRA NVGPU-16
Change-Id: Ib098accd34a1f5066eb8680c387f9b178169f3f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463547
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This change adds a new sysfs node to allow configuring CZF_BYPASS, to
enable platforms with low context-switching latency requirements.
/sys/devices/17000000.gp10b/czf_bypass
Values:
0 - always
1 - lateZ (default)
2 - single pass
3 - never
The specified value will apply only to newly allocated contexts.
Bug 1914014
Change-Id: Ibb9a8e86089acaadaa7260b00eedec5c80762d6f
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1478567
(cherry picked from commit 3bc022cb38)
Reviewed-on: http://git-master/r/1473820
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Change the channel worker to use nvgpu_cond instead of Linux wait
queue.
JIRA NVGPU-14
Change-Id: Iac856dca2acfa80065f5d2fd542cd2a6278333a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1469850
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Introduce a priv ring HAL and define ISR as the only function in it.
Introduce a gp10b version of the ISR that writes error message to
UART for every priv ring error, and leave the old chips with silent
error handling.
Bug 1846641
Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473696
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Move the function pointer for VPR page allocation to struct gk20a
and use it from there. At the same time remove secure_page_alloc
pointer and add a direct call to it in probe.
Move platform_tegra.h as tegra/linux/platform_gk20a_tegra.h, as it's
only declaring functions defined in platform_gk20a_tegra.c to other
files in the same directory.
JIRA NVGPU-16
Change-Id: I19ac9ee0b2f6734203ae32a1f51d67fd51aced9f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473706
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Added function pointers to check chip specific valid
gfx class and compute class. Also added function pointer
to update ctx header with preemption buffer pointers.
Bug 200292090
Change-Id: I8119ee082e2abb67186a8ac07088f8db7f410ba1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1293502
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- struct nvgpu_falcon to hold properties of falcon controller
- falcon controller interface layer which establish access
to required falcon controller HAL based on struct nvgpu_falcon member
flcn_id & flcn_base parameter.
- each falcon nvgpu_falcon struct initialized during init
with id, base-address along with other properties at HAL.
- Added defines related to flacon controller.
Change-Id: Ia7777c01ecc542150ddd72f8603b7b4475522b58
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1467523
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Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This
includes some functions in allocators that were used only for
debugging.
Remove include of linux/debugfs.h on files that do not deal with
debugfs.
linux/debugfs.h implicitly included linux/fs.h, which we relied on.
Add explicit include of linux/fs.h for all files where this is the
case.
Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467897
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
perfbuf mapping fixes:
- Allocate VM specifically for perfbuf use: using the PMU's
results in mmu faults for larger buffers where 64k pages are used.
- Make 4GB boundary check work for large address spaces
- remove requirement to have allow_all flag set
- track perfbuf ownership and clean up appropriately
Bug 1880196
JIRA EVLR-1074
Change-Id: Ieee4eb17b64acf9b6ede37bf8e6a91892cda4a7e
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1460809
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Move Linux driver specific code to common/linux/module.c. This includes
module initialization, power management, and interrupt functions.
Move pci.c, pci.h and nvgpu_common.c under common/linux as they're
Linux only files.
JIRA NVGPU-16
Change-Id: If92b4dd78ebc0c2bbfa9fbca258e9552e4979b4b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1456162
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Monitoring INA3221 is currently missing on some customer designs.
Use PCI vendor/device ids and VBIOS version to identify such device,
and set power_sensor_missing flag. This flag is subsequently used
to skip power device and power policy programming in PMU.
Bug 1903258
Change-Id: Ia6b5ce563b5cc3593e138635639025b830e4535e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1460936
(cherry picked from commit 42f236c210931d28d2699858bb0663b91cf11046)
Reviewed-on: http://git-master/r/1463104
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From Volta onwards, new DSS ZBC registers are
added for ZBC feature and save/restore of new
ZBC reglist is taken care by ctxsw firmware.
Therefore, PMU should save ZBC reglist only
for PRE-volta chips.
JIRA GPUT19X-20
Change-Id: I7d92274208ca42cc77bf57ea3cc416b5ecf32842
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1460244
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Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.
The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.
JIRA NVGPU-16
Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
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Use nvgpu list APIs instead of linux list APIs
to store pending semaphore waits
Jira NVGPU-13
Change-Id: I42fc6c6233e39f475a939ddd6a81c0cda851b6bf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1454693
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Renaming was done with the following command:
$ find -type f | \
xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'
Also rename mem_desc.[ch] to nvgpu_mem.[ch].
JIRA NVGPU-12
Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325547
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Update the debugging APIs in nvgpu to be more coherent and less dependent
on Linux kernel APIs and data structures. The old API is maintained for
backwards compatibility but the prints themselves are changed.
The old API now prints stuff like this:
[ 46.376077] nvgpu: gk20a_channel_suspend:3430 [DBG] suspend channel 508
[ 46.376242] nvgpu: gk20a_channel_suspend:3430 [DBG] suspend channel 509
[ 46.376359] nvgpu: gk20a_channel_suspend:3430 [DBG] suspend channel 510
[ 46.376466] nvgpu: gk20a_channel_suspend:3430 [DBG] suspend channel 511
[ 46.376604] nvgpu: gk20a_fifo_update_runlist_locked:3090 [DBG] runlist_id : 0, switch to new buffer 0x 4003a0000
[ 46.378348] nvgpu: gk20a_mm_l2_flush:5259 [DBG] l2_flush_dirty 0x2
[ 46.378562] nvgpu: clk_config_pll:170 [DBG] low_PL 1(div1), high_PL 2(div2)
[ 46.378684] nvgpu: clk_config_pll:170 [DBG] low_PL 8(div8), high_PL 17(div17)
Each line starts with 'nvgpu:' since this is the nvgpu driver. Then there's
the function name which is is right justified and post-fixed with a line
number. This keeps all statements lined up so long as the function name does
not exceed the length of characters alloted for function names (33 currently).
Lines are also left justified with 4 available spaces since there are currently
no source files with over 9999 lines. The type of message (DBG, WRN, ERR) is
then printed in brackets. Finally there's whatever message is to be printed.
The new API will be largely the same except there will be an additional
print of the GPU that the message has originated from in order to help debug
cases where both an iGPU and dGPU are active. Also the implicit newline
added in the legacy API has been removed. This is inline with essentially
every other print function in the C world. There are numerous places where
'\n' is added despite it not being needed which results in log files being
littered with blank lines. This makes the logs much harder to read.
Bug ...
Change-Id: I7bc87f2dbbaebf6eb6c9de1a629a0e2963e1804c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1329487
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Split as_gk20a.c into two parts:
common/linux/ioctl_as.c deals with as related devnodes and ioctls.
This file contains all the Linux specific parts of as_gk20a.c.
common/as.c deals with general as_gk20a maintenance and is Linux
independent.
JIRA NVGPU-16
Change-Id: I2d8541e0bd6ce159dc6e4de8e819dfcff0fa8f80
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1330803
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
- check return value of nvgpu_mutex_init in clk_mclk.c
- declare new callback g->ops.pmu.mclk_deinit() to
deinitialize mclk mutexes
- and define this callback for gp106
- add corresponding nvgpu_mutex_destroy calls in
deinitialization
Jira NVGPU-13
Change-Id: I1491c084d330ac9756c9520477e6fe494560e651
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1321294
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ctrl_gk20a.c had some direct accesses to hardware. These violate the
HAL rules, because we don't have per-GPU ctrl, and thus the code
cannot be made GPU independent.
Move all GR accesses to new GR HALs and use existing bus HAL for
accessing timer. Remove #includes of all hardware headers.
JIRA NVGPU-28
Change-Id: I57e67519f62e9bd6c3e725e1bef6e366190f5834
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1327001
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Move code that touches host registers and instance block to fifo HAL.
This involves adding HAL ops for the fifo HAL functions that get
called from outside fifo. This clears responsibility of channel by
leaving it only managing channels in software and push buffers.
channel had member ramfc defined, but it was not used, to remove it.
pbdma_acquire_val consisted both of channel logic and hardware
programming. The channel logic was moved to the caller and only
hardware programming was moved.
Change-Id: Id005787f6cc91276b767e8e86325caf966913de9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1322423
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Move the name field from struct gpu_ops up to struct gk20a. The field
is not a function op, so it doesn't belong in gpu_ops.
Replace all uses of dev_name() with use of g->name when possible.
JIRA NVGPU-16
Change-Id: Ic6e99e39258cbf3bb7c806962cbbd7de5126688f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1328534
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