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085f94bf89
implemented queue support which is needed for cmd/msg for managing CMDQ/MSGQ. In ga10b GSP, totally 4 CMDQ and 4 MSGQ supported. in current implementation we use only one CMDQ and one MSGQ. NVGPU-6784 Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com> Change-Id: Ib40ff9df6580e15824131dd6f54bfb85dce8e594 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2590678 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
55 lines
2.2 KiB
C
55 lines
2.2 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GSP_QUEUE_H
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#define NVGPU_GSP_QUEUE_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_falcon;
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struct nv_flcn_cmd_gsp;
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struct nvgpu_engine_mem_queue;
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struct gsp_init_msg_gsp_init;
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int nvgpu_gsp_queues_init(struct gk20a *g,
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struct nvgpu_engine_mem_queue **queues,
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struct gsp_init_msg_gsp_init *init);
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void nvgpu_gsp_queues_free(struct gk20a *g,
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struct nvgpu_engine_mem_queue **queues);
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u32 nvgpu_gsp_queue_get_size(struct nvgpu_engine_mem_queue **queues,
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u32 queue_id);
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int nvgpu_gsp_queue_push(struct nvgpu_engine_mem_queue **queues,
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u32 queue_id, struct nvgpu_falcon *flcn,
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struct nv_flcn_cmd_gsp *cmd, u32 size);
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bool nvgpu_gsp_queue_is_empty(struct nvgpu_engine_mem_queue **queues,
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u32 queue_id);
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bool nvgpu_gsp_queue_read(struct gk20a *g,
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struct nvgpu_engine_mem_queue **queues,
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u32 queue_id, struct nvgpu_falcon *flcn, void *data,
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u32 bytes_to_read, int *status);
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int nvgpu_gsp_queue_rewind(struct nvgpu_falcon *flcn,
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struct nvgpu_engine_mem_queue **queues,
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u32 queue_id);
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#endif /* NVGPU_GSP_QUEUE_H */
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