mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
0b02c8589d
This reverts commit2d397e34a5. This reverts commitcd6e821cf6. This reverts commit5cf1eb145f. This reverts commita8d6f31bde. This reverts commit067ddbc4e4. This reverts commit3eede64de0. This reverts commit1407133b7e. This reverts commit797dde3e32. Looks like this makes the ap_compute test on embedded-qnx-hv e3550-t194 quite bad. Might also affect ap_resmgr. Signed-off-by: Alex Waterman <alexw@nvidia.com> Change-Id: Ib9f06514d554d1a67993f0f2bd3d180147385e0a Reviewed-on: https://git-master.nvidia.com/r/1761864 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/*
|
|
* GV100 master
|
|
*
|
|
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/types.h>
|
|
|
|
#include "gk20a/gk20a.h"
|
|
|
|
#include "gp10b/mc_gp10b.h"
|
|
|
|
#include "mc_gv100.h"
|
|
#include "gv11b/fb_gv11b.h"
|
|
|
|
#include <nvgpu/hw/gv100/hw_mc_gv100.h>
|
|
|
|
void mc_gv100_intr_enable(struct gk20a *g)
|
|
{
|
|
u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
|
|
|
|
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
|
|
0xffffffffU);
|
|
gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
|
|
0xffffffffU);
|
|
g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
|
|
|
|
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
|
|
mc_intr_pfifo_pending_f() |
|
|
mc_intr_hub_pending_f() |
|
|
mc_intr_priv_ring_pending_f() |
|
|
mc_intr_pbus_pending_f() |
|
|
mc_intr_ltc_pending_f() |
|
|
mc_intr_nvlink_pending_f() |
|
|
eng_intr_mask;
|
|
|
|
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
|
|
mc_intr_pfifo_pending_f()
|
|
| eng_intr_mask;
|
|
|
|
/* TODO: Enable PRI faults for HUB ECC err intr */
|
|
g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
|
|
|
|
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
|
|
g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
|
|
|
|
gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
|
|
g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
|
|
|
|
}
|
|
|
|
bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
|
|
{
|
|
return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
|
|
}
|
|
|
|
bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
|
|
{
|
|
u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
|
|
u32 stall_intr, eng_intr_mask;
|
|
|
|
eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
|
|
if ((mc_intr_0 & eng_intr_mask) != 0U) {
|
|
return true;
|
|
}
|
|
|
|
stall_intr = mc_intr_pfifo_pending_f() |
|
|
mc_intr_hub_pending_f() |
|
|
mc_intr_priv_ring_pending_f() |
|
|
mc_intr_pbus_pending_f() |
|
|
mc_intr_ltc_pending_f() |
|
|
mc_intr_nvlink_pending_f();
|
|
if ((mc_intr_0 & stall_intr) != 0U) {
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|