Sagar Kamble 2c09ee5cf0 gpu: nvgpu: update hw headers with falcon IRQSSET & IRQSCLR ...

For gk20a & gp106, nvgpu driver currently hardcodes base address for FECS,
GPCCS, NVDEC falcons. Instead, emit those register in the hw headers. Base
address is the address of IRQSSET register.

JIRA NVGPU-1587

Change-Id: I710c4006b5ef6ded7980491ac157f8c03399b831
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966643
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-12-12 15:14:02 -08:00

..

nvgpu

gpu: nvgpu: update hw headers with falcon IRQSSET & IRQSCLR

2018-12-12 15:14:02 -08:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00