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Move all definitions and functions other than type defines from types.h to new header utils.h for posix. Update files that use functions and defintions from utils.h DIV_ROUND_UP macro is updated to use safe_ops.h calls to handle the CERT-C wrap issues. Jira NVGPU-3411 Change-Id: I9da3e9f255f39949287c615519f062fd8816aa04 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130453 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Philip Elcan <pelcan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
241 lines
6.0 KiB
C
241 lines
6.0 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdatomic.h>
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#include <nvgpu/posix/utils.h>
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#include <nvgpu/posix/bitops.h>
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#include <nvgpu/posix/atomic.h>
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#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
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#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
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unsigned long nvgpu_posix_ffs(unsigned long word)
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{
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return (unsigned long)__builtin_ffsl(word);
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}
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unsigned long nvgpu_posix_fls(unsigned long word)
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{
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unsigned long ret;
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if (word == 0UL) {
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/* __builtin_clzl() below is undefined for 0, so we have
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* to handle that as a special case.
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*/
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ret = 0UL;
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} else {
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ret = (sizeof(unsigned long) * 8UL) - __builtin_clzl(word);
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}
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return ret;
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}
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static unsigned long __find_next_bit(const unsigned long *addr,
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unsigned long n,
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unsigned long start,
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bool invert)
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{
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unsigned long idx, idx_max;
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unsigned long w;
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unsigned long start_mask;
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/*
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* We make a mask we can XOR into the word so that we can invert the
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* word without requiring a branch. I.e instead of doing:
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*
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* w = invert ? ~addr[idx] : addr[idx]
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*
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* We can do:
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*
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* w = addr[idx] ^= invert_mask
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*
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* This saves us a branch every iteration through the loop. Now we can
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* always just look for 1s.
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*/
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unsigned long invert_mask = invert ? ~0UL : 0UL;
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if (start >= n) {
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return n;
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}
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start_mask = ~0UL << (start & (BITS_PER_LONG - 1));
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idx = start / BITS_PER_LONG;
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w = (addr[idx] ^ invert_mask) & start_mask;
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start = round_up(start, BITS_PER_LONG);
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idx_max = (n - 1) / BITS_PER_LONG;
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/*
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* Find the first non-zero word taking into account start and
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* invert.
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*/
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while (!w) {
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idx++;
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if (idx > idx_max) {
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return n;
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}
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start += BITS_PER_LONG;
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w = addr[idx] ^ invert_mask;
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}
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return min(n, (ffs(w) - 1UL) + idx * BITS_PER_LONG);
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}
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unsigned long find_first_bit(const unsigned long *addr, unsigned long size)
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{
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return __find_next_bit(addr, size, 0, false);
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}
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unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size)
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{
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return __find_next_bit(addr, size, 0, true);
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}
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unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
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unsigned long offset)
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{
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return __find_next_bit(addr, size, offset, false);
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}
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static unsigned long find_next_zero_bit(const unsigned long *addr,
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unsigned long size,
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unsigned long offset)
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{
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return __find_next_bit(addr, size, offset, true);
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}
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void bitmap_set(unsigned long *map, unsigned int start, int len)
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{
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unsigned int end = start + len;
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/*
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* Super slow naive implementation. But speed isn't what matters here.
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*/
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while (start < end) {
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set_bit(start++, map);
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}
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}
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void bitmap_clear(unsigned long *map, unsigned int start, int len)
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{
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unsigned int end = start + len;
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while (start < end) {
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clear_bit(start++, map);
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}
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}
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/*
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* This is essentially a find-first-fit allocator: this searches a bitmap for
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* the first space that is large enough to satisfy the requested size of bits.
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* That means that this is not a vary smart allocator. But it is fast relative
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* to an allocator that goes looking for an optimal location.
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*/
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unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
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unsigned long size,
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unsigned long start,
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unsigned int nr,
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unsigned long align_mask,
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unsigned long align_offset)
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{
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unsigned long offs;
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while (start + nr <= size) {
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start = find_next_zero_bit(map, size, start);
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start = ALIGN_MASK(start + align_offset, align_mask) -
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align_offset;
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/*
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* Not enough space left to satisfy the requested area.
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*/
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if ((start + nr) > size) {
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return size;
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}
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offs = find_next_bit(map, size, start);
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if ((offs - start) >= nr) {
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return start;
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}
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start = offs + 1;
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}
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return size;
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}
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unsigned long bitmap_find_next_zero_area(unsigned long *map,
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unsigned long size,
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unsigned long start,
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unsigned int nr,
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unsigned long align_mask)
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{
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return bitmap_find_next_zero_area_off(map, size, start, nr,
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align_mask, 0);
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}
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bool test_bit(int nr, const volatile unsigned long *addr)
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{
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return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
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}
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bool test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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volatile unsigned long *p = addr + BIT_WORD(nr);
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return (atomic_fetch_or(p, mask) & mask) != 0ULL;
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}
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bool test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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volatile unsigned long *p =
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((volatile unsigned long *)addr) + BIT_WORD(nr);
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return (atomic_fetch_and(p, ~mask) & mask) != 0ULL;
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}
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void set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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(void)atomic_fetch_or(p, mask);
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}
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void clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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(void)atomic_fetch_and(p, ~mask);
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}
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