mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 09:57:08 +03:00
a307b6eb77
Move the nvlink HAL code to unit specific directory as part of nvgpu restructing. This move is done after removing usage of other unit's hardware headers from nvlink. Also confirmed that no other unit files are including nvlink hardware headers. JIRA NVGPU-966 Change-Id: I301e3f8de37c5792a3e1e799b97e5fdfc131f058 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1975259 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
585 lines
15 KiB
C
585 lines
15 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/enabled.h>
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#ifdef CONFIG_TEGRA_NVLINK
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/*
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* WAR: use this function to find detault link, as only one is supported
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* on the library for now
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* Returns NVLINK_MAX_LINKS_SW on failure
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*/
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static u32 __nvgpu_nvlink_get_link(struct nvlink_device *ndev)
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{
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u32 link_id;
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struct gk20a *g = (struct gk20a *) ndev->priv;
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if (!g)
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return NVLINK_MAX_LINKS_SW;
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/* Lets find the detected link */
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if (g->nvlink.initialized_links)
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link_id = ffs(g->nvlink.initialized_links) - 1;
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else
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return NVLINK_MAX_LINKS_SW;
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if (g->nvlink.links[link_id].remote_info.is_connected)
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return link_id;
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return NVLINK_MAX_LINKS_SW;
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}
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static int nvgpu_nvlink_speed_config(struct nvlink_device *ndev)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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int err;
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/* For now master topology is the only one supported */
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if (!ndev->is_master) {
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nvgpu_err(g, "dGPU is not master for Nvlink speed config");
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return -EINVAL;
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}
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err = g->ops.nvlink.speed_config(g);
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if (err != 0) {
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nvgpu_err(g, "Nvlink speed config failed.\n");
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return err;
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}
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ndev->speed = g->nvlink.speed;
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nvgpu_log(g, gpu_dbg_nvlink, "Nvlink default speed set to %d\n",
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ndev->speed);
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return err;
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}
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static int nvgpu_nvlink_early_init(struct nvlink_device *ndev)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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int err;
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/* For now master topology is the only one supported */
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if (!ndev->is_master) {
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nvgpu_log(g, gpu_dbg_info | gpu_dbg_nvlink,
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"dGPU is not master of Nvlink link");
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return -EINVAL;
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}
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err = g->ops.nvlink.early_init(g);
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return err;
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}
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static int nvgpu_nvlink_link_early_init(struct nvlink_device *ndev)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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int err;
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u32 link_id;
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/*
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* First check the topology and setup connectivity
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* HACK: we are only enabling one link for now!!!
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*/
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link_id = ffs(g->nvlink.discovered_links) - 1;
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g->nvlink.links[link_id].remote_info.is_connected = true;
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g->nvlink.links[link_id].remote_info.device_type =
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nvgpu_nvlink_endp_tegra;
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err = g->ops.nvlink.link_early_init(g, BIT(link_id));
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if (err == 0) {
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g->nvlink.links[link_id].priv = (void *) &(ndev->link);
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ndev->link.priv = (void *) g;
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}
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return err;
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}
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static int nvgpu_nvlink_interface_init(struct nvlink_device *ndev)
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{
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int err;
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struct gk20a *g = (struct gk20a *) ndev->priv;
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err = g->ops.nvlink.interface_init(g);
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return err;
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}
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static int nvgpu_nvlink_interface_disable(struct nvlink_device *ndev)
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{
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int err = 0;
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struct gk20a *g = (struct gk20a *) ndev->priv;
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if (g->ops.nvlink.interface_disable)
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err = g->ops.nvlink.interface_disable(g);
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return err;
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}
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static int nvgpu_nvlink_shutdown(struct nvlink_device *ndev)
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{
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int err;
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struct gk20a *g = (struct gk20a *) ndev->priv;
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err = g->ops.nvlink.shutdown(g);
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return 0;
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}
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static int nvgpu_nvlink_reg_init(struct nvlink_device *ndev)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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int err;
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err = g->ops.nvlink.reg_init(g);
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return err;
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}
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static u32 nvgpu_nvlink_get_link_mode(struct nvlink_device *ndev)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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u32 mode;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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mode = g->ops.nvlink.link_get_mode(g, link_id);
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switch (mode) {
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case nvgpu_nvlink_link_off:
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return NVLINK_LINK_OFF;
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case nvgpu_nvlink_link_hs:
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return NVLINK_LINK_HS;
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case nvgpu_nvlink_link_safe:
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return NVLINK_LINK_SAFE;
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case nvgpu_nvlink_link_fault:
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return NVLINK_LINK_FAULT;
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case nvgpu_nvlink_link_rcvy_ac:
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return NVLINK_LINK_RCVY_AC;
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case nvgpu_nvlink_link_rcvy_sw:
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return NVLINK_LINK_RCVY_SW;
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case nvgpu_nvlink_link_rcvy_rx:
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return NVLINK_LINK_RCVY_RX;
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case nvgpu_nvlink_link_detect:
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return NVLINK_LINK_DETECT;
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case nvgpu_nvlink_link_reset:
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return NVLINK_LINK_RESET;
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case nvgpu_nvlink_link_enable_pm:
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return NVLINK_LINK_ENABLE_PM;
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case nvgpu_nvlink_link_disable_pm:
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return NVLINK_LINK_DISABLE_PM;
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case nvgpu_nvlink_link_disable_err_detect:
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return NVLINK_LINK_DISABLE_ERR_DETECT;
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case nvgpu_nvlink_link_lane_disable:
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return NVLINK_LINK_LANE_DISABLE;
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case nvgpu_nvlink_link_lane_shutdown:
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return NVLINK_LINK_LANE_SHUTDOWN;
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default:
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nvgpu_log(g, gpu_dbg_info | gpu_dbg_nvlink,
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"unsupported mode %u", mode);
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}
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return NVLINK_LINK_OFF;
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}
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static u32 nvgpu_nvlink_get_link_state(struct nvlink_device *ndev)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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return g->ops.nvlink.link_get_state(g, link_id);
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}
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static int nvgpu_nvlink_set_link_mode(struct nvlink_device *ndev, u32 mode)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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u32 mode_sw;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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switch (mode) {
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case NVLINK_LINK_OFF:
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mode_sw = nvgpu_nvlink_link_off;
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break;
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case NVLINK_LINK_HS:
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mode_sw = nvgpu_nvlink_link_hs;
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break;
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case NVLINK_LINK_SAFE:
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mode_sw = nvgpu_nvlink_link_safe;
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break;
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case NVLINK_LINK_FAULT:
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mode_sw = nvgpu_nvlink_link_fault;
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break;
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case NVLINK_LINK_RCVY_AC:
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mode_sw = nvgpu_nvlink_link_rcvy_ac;
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break;
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case NVLINK_LINK_RCVY_SW:
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mode_sw = nvgpu_nvlink_link_rcvy_sw;
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break;
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case NVLINK_LINK_RCVY_RX:
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mode_sw = nvgpu_nvlink_link_rcvy_rx;
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break;
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case NVLINK_LINK_DETECT:
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mode_sw = nvgpu_nvlink_link_detect;
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break;
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case NVLINK_LINK_RESET:
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mode_sw = nvgpu_nvlink_link_reset;
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break;
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case NVLINK_LINK_ENABLE_PM:
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mode_sw = nvgpu_nvlink_link_enable_pm;
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break;
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case NVLINK_LINK_DISABLE_PM:
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mode_sw = nvgpu_nvlink_link_disable_pm;
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break;
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case NVLINK_LINK_DISABLE_ERR_DETECT:
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mode_sw = nvgpu_nvlink_link_disable_err_detect;
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break;
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case NVLINK_LINK_LANE_DISABLE:
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mode_sw = nvgpu_nvlink_link_lane_disable;
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break;
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case NVLINK_LINK_LANE_SHUTDOWN:
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mode_sw = nvgpu_nvlink_link_lane_shutdown;
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break;
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default:
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mode_sw = nvgpu_nvlink_link_off;
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}
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return g->ops.nvlink.link_set_mode(g, link_id, mode_sw);
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}
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static void nvgpu_nvlink_get_tx_sublink_state(struct nvlink_device *ndev, u32 *state)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return;
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if (state)
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*state = g->ops.nvlink.get_tx_sublink_state(g, link_id);
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}
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static void nvgpu_nvlink_get_rx_sublink_state(struct nvlink_device *ndev, u32 *state)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return;
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if (state)
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*state = g->ops.nvlink.get_rx_sublink_state(g, link_id);
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}
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static u32 nvgpu_nvlink_get_sublink_mode(struct nvlink_device *ndev,
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bool is_rx_sublink)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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u32 mode;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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mode = g->ops.nvlink.get_sublink_mode(g, link_id, is_rx_sublink);
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switch (mode) {
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case nvgpu_nvlink_sublink_tx_hs:
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return NVLINK_TX_HS;
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case nvgpu_nvlink_sublink_tx_off:
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return NVLINK_TX_OFF;
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case nvgpu_nvlink_sublink_tx_single_lane:
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return NVLINK_TX_SINGLE_LANE;
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case nvgpu_nvlink_sublink_tx_safe:
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return NVLINK_TX_SAFE;
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case nvgpu_nvlink_sublink_tx_enable_pm:
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return NVLINK_TX_ENABLE_PM;
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case nvgpu_nvlink_sublink_tx_disable_pm:
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return NVLINK_TX_DISABLE_PM;
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case nvgpu_nvlink_sublink_tx_common:
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return NVLINK_TX_COMMON;
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case nvgpu_nvlink_sublink_tx_common_disable:
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return NVLINK_TX_COMMON_DISABLE;
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case nvgpu_nvlink_sublink_tx_data_ready:
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return NVLINK_TX_DATA_READY;
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case nvgpu_nvlink_sublink_tx_prbs_en:
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return NVLINK_TX_PRBS_EN;
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case nvgpu_nvlink_sublink_rx_hs:
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return NVLINK_RX_HS;
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case nvgpu_nvlink_sublink_rx_enable_pm:
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return NVLINK_RX_ENABLE_PM;
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case nvgpu_nvlink_sublink_rx_disable_pm:
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return NVLINK_RX_DISABLE_PM;
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case nvgpu_nvlink_sublink_rx_single_lane:
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return NVLINK_RX_SINGLE_LANE;
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case nvgpu_nvlink_sublink_rx_safe:
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return NVLINK_RX_SAFE;
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case nvgpu_nvlink_sublink_rx_off:
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return NVLINK_RX_OFF;
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case nvgpu_nvlink_sublink_rx_rxcal:
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return NVLINK_RX_RXCAL;
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default:
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nvgpu_log(g, gpu_dbg_nvlink, "Unsupported mode: %u", mode);
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break;
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}
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if (is_rx_sublink)
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return NVLINK_RX_OFF;
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return NVLINK_TX_OFF;
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}
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static int nvgpu_nvlink_set_sublink_mode(struct nvlink_device *ndev,
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bool is_rx_sublink, u32 mode)
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{
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struct gk20a *g = (struct gk20a *) ndev->priv;
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u32 link_id;
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u32 mode_sw;
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link_id = __nvgpu_nvlink_get_link(ndev);
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if (link_id == NVLINK_MAX_LINKS_SW)
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return -EINVAL;
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if (!is_rx_sublink) {
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switch (mode) {
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case NVLINK_TX_HS:
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mode_sw = nvgpu_nvlink_sublink_tx_hs;
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break;
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case NVLINK_TX_ENABLE_PM:
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mode_sw = nvgpu_nvlink_sublink_tx_enable_pm;
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break;
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case NVLINK_TX_DISABLE_PM:
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mode_sw = nvgpu_nvlink_sublink_tx_disable_pm;
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break;
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case NVLINK_TX_SINGLE_LANE:
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mode_sw = nvgpu_nvlink_sublink_tx_single_lane;
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break;
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case NVLINK_TX_SAFE:
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mode_sw = nvgpu_nvlink_sublink_tx_safe;
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break;
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case NVLINK_TX_OFF:
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mode_sw = nvgpu_nvlink_sublink_tx_off;
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break;
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case NVLINK_TX_COMMON:
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mode_sw = nvgpu_nvlink_sublink_tx_common;
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break;
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case NVLINK_TX_COMMON_DISABLE:
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mode_sw = nvgpu_nvlink_sublink_tx_common_disable;
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break;
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case NVLINK_TX_DATA_READY:
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mode_sw = nvgpu_nvlink_sublink_tx_data_ready;
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break;
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case NVLINK_TX_PRBS_EN:
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mode_sw = nvgpu_nvlink_sublink_tx_prbs_en;
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break;
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default:
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return -EINVAL;
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}
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} else {
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switch (mode) {
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case NVLINK_RX_HS:
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mode_sw = nvgpu_nvlink_sublink_rx_hs;
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break;
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case NVLINK_RX_ENABLE_PM:
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mode_sw = nvgpu_nvlink_sublink_rx_enable_pm;
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break;
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case NVLINK_RX_DISABLE_PM:
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mode_sw = nvgpu_nvlink_sublink_rx_disable_pm;
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break;
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case NVLINK_RX_SINGLE_LANE:
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mode_sw = nvgpu_nvlink_sublink_rx_single_lane;
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break;
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case NVLINK_RX_SAFE:
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mode_sw = nvgpu_nvlink_sublink_rx_safe;
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break;
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case NVLINK_RX_OFF:
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mode_sw = nvgpu_nvlink_sublink_rx_off;
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break;
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case NVLINK_RX_RXCAL:
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mode_sw = nvgpu_nvlink_sublink_rx_rxcal;
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break;
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default:
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return -EINVAL;
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}
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}
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return g->ops.nvlink.set_sublink_mode(g, link_id, is_rx_sublink,
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mode_sw);
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}
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static int nvgpu_nvlink_init_ops(struct gk20a *g)
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{
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struct nvlink_device *ndev = g->nvlink.priv;
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if (!ndev)
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return -EINVAL;
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/* Fill in device struct */
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ndev->dev_ops.dev_early_init = nvgpu_nvlink_early_init;
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ndev->dev_ops.dev_interface_init = nvgpu_nvlink_interface_init;
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ndev->dev_ops.dev_reg_init = nvgpu_nvlink_reg_init;
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ndev->dev_ops.dev_interface_disable = nvgpu_nvlink_interface_disable;
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ndev->dev_ops.dev_shutdown = nvgpu_nvlink_shutdown;
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ndev->dev_ops.dev_speed_config = nvgpu_nvlink_speed_config;
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/* Fill in the link struct */
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ndev->link.device_id = ndev->device_id;
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ndev->link.mode = NVLINK_LINK_OFF;
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ndev->link.is_sl_supported = false;
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ndev->link.link_ops.get_link_mode = nvgpu_nvlink_get_link_mode;
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ndev->link.link_ops.set_link_mode = nvgpu_nvlink_set_link_mode;
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ndev->link.link_ops.get_sublink_mode = nvgpu_nvlink_get_sublink_mode;
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ndev->link.link_ops.set_sublink_mode = nvgpu_nvlink_set_sublink_mode;
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ndev->link.link_ops.get_link_state = nvgpu_nvlink_get_link_state;
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ndev->link.link_ops.get_tx_sublink_state =
|
|
nvgpu_nvlink_get_tx_sublink_state;
|
|
ndev->link.link_ops.get_rx_sublink_state =
|
|
nvgpu_nvlink_get_rx_sublink_state;
|
|
ndev->link.link_ops.link_early_init =
|
|
nvgpu_nvlink_link_early_init;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nvgpu_nvlink_enumerate(struct gk20a *g)
|
|
{
|
|
struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
|
|
|
|
if (!ndev)
|
|
return -ENODEV;
|
|
|
|
return nvlink_enumerate(ndev);
|
|
}
|
|
|
|
int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off)
|
|
{
|
|
struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
|
|
|
|
if (!ndev)
|
|
return -ENODEV;
|
|
|
|
/* Check if the link is connected */
|
|
if (!g->nvlink.links[link_id].remote_info.is_connected)
|
|
return -ENODEV;
|
|
|
|
if (from_off)
|
|
return nvlink_transition_intranode_conn_off_to_safe(ndev);
|
|
|
|
return nvlink_train_intranode_conn_safe_to_hs(ndev);
|
|
}
|
|
|
|
#endif
|
|
|
|
int nvgpu_nvlink_probe(struct gk20a *g)
|
|
{
|
|
#ifdef CONFIG_TEGRA_NVLINK
|
|
int err;
|
|
struct nvlink_device *ndev;
|
|
|
|
/* Allocating structures */
|
|
ndev = nvgpu_kzalloc(g, sizeof(struct nvlink_device));
|
|
if (!ndev) {
|
|
nvgpu_err(g, "OOM while allocating nvlink device struct");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ndev->priv = (void *) g;
|
|
g->nvlink.priv = (void *) ndev;
|
|
|
|
err = nvgpu_nvlink_read_dt_props(g);
|
|
if (err != 0)
|
|
goto free_ndev;
|
|
|
|
err = nvgpu_nvlink_init_ops(g);
|
|
if (err != 0)
|
|
goto free_ndev;
|
|
|
|
/* Register device with core driver*/
|
|
err = nvlink_register_device(ndev);
|
|
if (err != 0) {
|
|
nvgpu_err(g, "failed on nvlink device registration");
|
|
goto free_ndev;
|
|
}
|
|
|
|
/* Register link with core driver */
|
|
err = nvlink_register_link(&ndev->link);
|
|
if (err != 0) {
|
|
nvgpu_err(g, "failed on nvlink link registration");
|
|
goto unregister_ndev;
|
|
}
|
|
|
|
/* Enable NVLINK support */
|
|
__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, true);
|
|
return 0;
|
|
|
|
unregister_ndev:
|
|
nvlink_unregister_device(ndev);
|
|
|
|
free_ndev:
|
|
nvgpu_kfree(g, ndev);
|
|
g->nvlink.priv = NULL;
|
|
return err;
|
|
#else
|
|
return -ENODEV;
|
|
#endif
|
|
}
|
|
|
|
int nvgpu_nvlink_remove(struct gk20a *g)
|
|
{
|
|
#ifdef CONFIG_TEGRA_NVLINK
|
|
struct nvlink_device *ndev;
|
|
int err;
|
|
|
|
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK))
|
|
return -ENODEV;
|
|
|
|
ndev = g->nvlink.priv;
|
|
if (!ndev)
|
|
return -ENODEV;
|
|
|
|
__nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false);
|
|
|
|
err = nvlink_unregister_link(&ndev->link);
|
|
if (err != 0) {
|
|
nvgpu_err(g, "failed on nvlink link unregistration");
|
|
return err;
|
|
}
|
|
|
|
err = nvlink_unregister_device(ndev);
|
|
if (err != 0) {
|
|
nvgpu_err(g, "failed on nvlink device unregistration");
|
|
return err;
|
|
}
|
|
|
|
nvgpu_kfree(g, ndev);
|
|
|
|
return 0;
|
|
#else
|
|
return -ENODEV;
|
|
#endif
|
|
}
|