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5991f6b856
Simplify object ownership by passing the gr_ctx around directly instead of reading from tsg via a channel; the caller holds the gr_ctx already. Also pass the channel vm and vpr flag instead of the whole channel as only those are needed. Jira NVGPU-1149 Change-Id: Ic0921ccaf65f208105b25f08f8d7b581a56b40fe Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1925431 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
96 lines
3.8 KiB
C
96 lines
3.8 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_TU104_H
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#define NVGPU_GR_TU104_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_preemption_modes_rec;
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enum {
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TURING_CHANNEL_GPFIFO_A = 0xC46F,
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TURING_A = 0xC597,
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TURING_COMPUTE_A = 0xC5C0,
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TURING_DMA_COPY_A = 0xC5B5,
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};
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#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC5C0_SET_SKEDCHECK 0x23c
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#define NVC5C0_SET_SHADER_CUT_COLLECTOR 0x254
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#define NVC5C0_SET_SM_DISP_CTRL 0x250
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#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK 0x1
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#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE 0
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#define NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE 1
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#define NVC597_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC597_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVC597_SET_GO_IDLE_TIMEOUT 0x022c
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#define NVC597_SET_TEX_IN_DBG 0x10bc
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#define NVC597_SET_SKEDCHECK 0x10c0
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#define NVC597_SET_BES_CROP_DEBUG3 0x10c4
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#define NVC597_SET_BES_CROP_DEBUG4 0x10b0
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#define NVC597_SET_SM_DISP_CTRL 0x10c8
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#define NVC597_SET_SHADER_CUT_COLLECTOR 0x10d0
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/* TODO: merge these into global context buffer list in gr_gk20a.h */
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#define RTV_CIRCULAR_BUFFER 8
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#define RTV_CIRCULAR_BUFFER_VA 5
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bool gr_tu104_is_valid_class(struct gk20a *g, u32 class_num);
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bool gr_tu104_is_valid_gfx_class(struct gk20a *g, u32 class_num);
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bool gr_tu104_is_valid_compute_class(struct gk20a *g, u32 class_num);
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int gr_tu104_init_sw_bundle64(struct gk20a *g);
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void gr_tu10x_create_sysfs(struct gk20a *g);
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void gr_tu10x_remove_sysfs(struct gk20a *g);
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int gr_tu104_alloc_global_ctx_buffers(struct gk20a *g);
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int gr_tu104_map_global_ctx_buffers(struct gk20a *g, struct vm_gk20a *vm,
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struct nvgpu_gr_ctx *gr_ctx, bool vpr);
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int gr_tu104_commit_global_ctx_buffers(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, bool patch);
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void gr_tu104_bundle_cb_defaults(struct gk20a *g);
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void gr_tu104_cb_size_default(struct gk20a *g);
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int gr_tu104_get_preemption_mode_flags(struct gk20a *g,
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struct nvgpu_preemption_modes_rec *preemption_modes_rec);
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void gr_tu104_enable_gpc_exceptions(struct gk20a *g);
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int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
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enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs,
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u32 reg_list_ppc_count, u32 *__offset_in_segment);
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int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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void gr_tu104_init_sm_dsm_reg_info(void);
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void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
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u32 *num_sm_dsm_perf_ctrl_regs, u32 **sm_dsm_perf_ctrl_regs,
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u32 *ctrl_register_stride);
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#endif /* NVGPU_GR_TU104_H */
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