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Add fecs hal to read ctxsw_status0 and ctxsw_status1. This helps to avoid direct fecs register access from gr isr error report function. JIRA NVGPU-3016 Change-Id: I6f9725f825ba3b80b309cc2e95a1069d3c03f34f Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2098248 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>