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8cc67f6064
JIRA DNVGPU-170 1) Add clock frequency controller VBIOS structure definitions 2) Parse VBIOS tables and build boardobj structures for clock frequency controller. 3) send clock frequency controller data structures to PMU 4) implement public function to send load/unload command to pmu to enable/disable clock frequency controller support Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07) Reviewed-on: http://git-master/r/1270897 GVS: Gerrit_Virtual_Submit
121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
/*
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* general clock structures & definitions
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _CLK_H_
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#define _CLK_H_
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#include "clk_vin.h"
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#include "clk_fll.h"
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#include "clk_domain.h"
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#include "clk_prog.h"
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#include "clk_vf_point.h"
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#include "clk_mclk.h"
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#include "clk_freq_controller.h"
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#include "gk20a/gk20a.h"
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1F
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#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0
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/* clock related defines for GPUs supporting clock control from pmu*/
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struct clk_pmupstate {
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struct avfsvinobjs avfs_vinobjs;
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struct avfsfllobjs avfs_fllobjs;
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struct clk_domains clk_domainobjs;
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struct clk_progs clk_progobjs;
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struct clk_vf_points clk_vf_pointobjs;
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struct clk_mclk_state clk_mclk;
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struct clk_freq_controllers clk_freq_controllers;
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};
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struct clockentry {
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u8 vbios_clk_domain;
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u8 clk_which;
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u8 perf_index;
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u32 api_clk_domain;
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};
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struct set_fll_clk {
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u32 voltuv;
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u16 gpc2clkmhz;
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u32 current_regime_id_gpc;
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u32 target_regime_id_gpc;
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u16 sys2clkmhz;
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u32 current_regime_id_sys;
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u32 target_regime_id_sys;
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u16 xbar2clkmhz;
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u32 current_regime_id_xbar;
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u32 target_regime_id_xbar;
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};
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS 9
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struct vbios_clock_domain {
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u8 clock_type;
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u8 num_domains;
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struct clockentry clock_entry[NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS];
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};
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struct vbios_clocks_table_1x_hal_clock_entry {
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enum nv_pmu_clk_clkwhich domain;
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bool b_noise_aware_capable;
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};
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_XBAR2CLK 1
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DRAMCLK 2
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_SYS2CLK 3
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_HUB2CLK 4
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_MSDCLK 5
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_PWRCLK 6
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DISPCLK 7
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#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_NUMCLKS 8
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#define PERF_CLK_MCLK 0
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#define PERF_CLK_DISPCLK 1
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#define PERF_CLK_GPC2CLK 2
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#define PERF_CLK_HOSTCLK 3
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#define PERF_CLK_LTC2CLK 4
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#define PERF_CLK_SYS2CLK 5
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#define PERF_CLK_HUB2CLK 6
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#define PERF_CLK_LEGCLK 7
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#define PERF_CLK_MSDCLK 8
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#define PERF_CLK_XCLK 9
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#define PERF_CLK_PWRCLK 10
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#define PERF_CLK_XBAR2CLK 11
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#define PERF_CLK_PCIEGENCLK 12
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#define PERF_CLK_NUM 13
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#define BOOT_GPC2CLK_MHZ 2581
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u32 clk_pmu_vin_load(struct gk20a *g);
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u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
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u32 clk_domain_get_f_or_v(
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struct gk20a *g,
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u32 clkapidomain,
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u16 *pclkmhz,
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u32 *pvoltuv,
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u8 railidx
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);
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u32 clk_domain_get_f_points(
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struct gk20a *g,
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u32 clkapidomain,
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u32 *fpointscount,
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u16 *freqpointsinmhz
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);
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int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
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int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
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int clk_pmu_freq_controller_load(struct gk20a *g, bool bload);
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#endif
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