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fa3f8cc101
Remove including gk20a.h from pmu_gk20a.h. This causes a fallout as some #includes were missing. gr_gp10b.h uses mem_desc, but did not include mm_gk20a.h. Add the include. Including mm_gk20a.h in gr_gp10b.h causes recursive include, as mm_gk20a.h has some gr defines. Move the defines to gr_gk20a.h to remove the dependency. gr_ctx_gk20a.h used struct gk20a pointers, but did not forward declare it. Add a forward declaration. gr_gk20a.h uses dbg_session_gk20a, but was missing forward declaration. gr_gk20a.h did not include nvgpu.h but it uses preemption types from that header. Add include. Change-Id: I2168e2303b55e0d187b816bcb26f37c8af1649ba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1283717 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
183 lines
5.0 KiB
C
183 lines
5.0 KiB
C
/*
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* GK20A Graphics Context
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __GR_CTX_GK20A_H__
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#define __GR_CTX_GK20A_H__
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struct gr_gk20a;
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/* production netlist, one and only one from below */
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/*#undef GK20A_NETLIST_IMAGE_FW_NAME*/
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#define GK20A_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B
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/* emulation netlists, match majorV with HW */
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#define GK20A_NETLIST_IMAGE_A "NETA_img.bin"
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#define GK20A_NETLIST_IMAGE_B "NETB_img.bin"
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#define GK20A_NETLIST_IMAGE_C "NETC_img.bin"
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#define GK20A_NETLIST_IMAGE_D "NETD_img.bin"
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/*
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* Need to support multiple ARCH in same GPU family
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* then need to provide path like ARCH/NETIMAGE to
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* point to correct netimage within GPU family,
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* Example, gm20x can support gm204 or gm206,so path
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* for netimage is gm204/NETC_img.bin, and '/' char
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* will inserted at null terminator char of "GAxxx"
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* to get complete path like gm204/NETC_img.bin
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*/
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#define GPU_ARCH "GAxxx"
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union __max_name {
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#ifdef GK20A_NETLIST_IMAGE_A
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char __name_a[sizeof(GK20A_NETLIST_IMAGE_A)];
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#endif
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#ifdef GK20A_NETLIST_IMAGE_B
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char __name_b[sizeof(GK20A_NETLIST_IMAGE_B)];
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#endif
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#ifdef GK20A_NETLIST_IMAGE_C
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char __name_c[sizeof(GK20A_NETLIST_IMAGE_C)];
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#endif
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#ifdef GK20A_NETLIST_IMAGE_D
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char __name_d[sizeof(GK20A_NETLIST_IMAGE_D)];
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#endif
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};
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#define MAX_NETLIST_NAME (sizeof(GPU_ARCH) + sizeof(union __max_name))
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/* index for emulation netlists */
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#define NETLIST_FINAL -1
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#define NETLIST_SLOT_A 0
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#define NETLIST_SLOT_B 1
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#define NETLIST_SLOT_C 2
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#define NETLIST_SLOT_D 3
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#define MAX_NETLIST 4
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/* netlist regions */
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#define NETLIST_REGIONID_FECS_UCODE_DATA 0
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#define NETLIST_REGIONID_FECS_UCODE_INST 1
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#define NETLIST_REGIONID_GPCCS_UCODE_DATA 2
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#define NETLIST_REGIONID_GPCCS_UCODE_INST 3
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#define NETLIST_REGIONID_SW_BUNDLE_INIT 4
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#define NETLIST_REGIONID_SW_CTX_LOAD 5
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#define NETLIST_REGIONID_SW_NON_CTX_LOAD 6
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#define NETLIST_REGIONID_SW_METHOD_INIT 7
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#define NETLIST_REGIONID_CTXREG_SYS 8
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#define NETLIST_REGIONID_CTXREG_GPC 9
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#define NETLIST_REGIONID_CTXREG_TPC 10
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#define NETLIST_REGIONID_CTXREG_ZCULL_GPC 11
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#define NETLIST_REGIONID_CTXREG_PM_SYS 12
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#define NETLIST_REGIONID_CTXREG_PM_GPC 13
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#define NETLIST_REGIONID_CTXREG_PM_TPC 14
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#define NETLIST_REGIONID_MAJORV 15
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#define NETLIST_REGIONID_BUFFER_SIZE 16
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#define NETLIST_REGIONID_CTXSW_REG_BASE_INDEX 17
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#define NETLIST_REGIONID_NETLIST_NUM 18
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#define NETLIST_REGIONID_CTXREG_PPC 19
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#define NETLIST_REGIONID_CTXREG_PMPPC 20
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#define NETLIST_REGIONID_NVPERF_CTXREG_SYS 21
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#define NETLIST_REGIONID_NVPERF_FBP_CTXREGS 22
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#define NETLIST_REGIONID_NVPERF_CTXREG_GPC 23
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#define NETLIST_REGIONID_NVPERF_FBP_ROUTER 24
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#define NETLIST_REGIONID_NVPERF_GPC_ROUTER 25
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#define NETLIST_REGIONID_CTXREG_PMLTC 26
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#define NETLIST_REGIONID_CTXREG_PMFBPA 27
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#define NETLIST_REGIONID_SWVEIDBUNDLEINIT 28
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#define NETLIST_REGIONID_NVPERF_SYS_ROUTER 29
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#define NETLIST_REGIONID_NVPERF_PMA 30
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#define NETLIST_REGIONID_CTXREG_PMROP 31
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#define NETLIST_REGIONID_CTXREG_PMUCGPC 32
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struct netlist_region {
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u32 region_id;
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u32 data_size;
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u32 data_offset;
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};
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struct netlist_image_header {
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u32 version;
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u32 regions;
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};
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struct netlist_image {
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struct netlist_image_header header;
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struct netlist_region regions[1];
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};
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struct av_gk20a {
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u32 addr;
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u32 value;
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};
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struct aiv_gk20a {
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u32 addr;
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u32 index;
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u32 value;
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};
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struct aiv_list_gk20a {
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struct aiv_gk20a *l;
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u32 count;
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};
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struct av_list_gk20a {
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struct av_gk20a *l;
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u32 count;
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};
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struct u32_list_gk20a {
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u32 *l;
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u32 count;
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};
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struct ctxsw_buf_offset_map_entry {
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u32 addr; /* Register address */
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u32 offset; /* Offset in ctxt switch buffer */
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};
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static inline
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struct av_gk20a *alloc_av_list_gk20a(struct av_list_gk20a *avl)
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{
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avl->l = kzalloc(avl->count * sizeof(*avl->l), GFP_KERNEL);
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return avl->l;
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}
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static inline
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struct aiv_gk20a *alloc_aiv_list_gk20a(struct aiv_list_gk20a *aivl)
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{
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aivl->l = kzalloc(aivl->count * sizeof(*aivl->l), GFP_KERNEL);
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return aivl->l;
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}
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static inline
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u32 *alloc_u32_list_gk20a(struct u32_list_gk20a *u32l)
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{
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u32l->l = kzalloc(u32l->count * sizeof(*u32l->l), GFP_KERNEL);
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return u32l->l;
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}
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struct gr_ucode_gk20a {
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struct {
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struct u32_list_gk20a inst;
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struct u32_list_gk20a data;
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} gpccs, fecs;
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};
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/* main entry for grctx loading */
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int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr);
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int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr);
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struct gpu_ops;
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void gk20a_init_gr_ctx(struct gpu_ops *gops);
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#endif /*__GR_CTX_GK20A_H__*/
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