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526cb04998
Simulator support is intermixed with the rest of code in gk20a.c. Move that code away from gk20a.c to an own file. Change-Id: Idd3c8795cec5eadc6e49811b5b8ff0592c49a7d2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323230 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
248 lines
9.2 KiB
C
248 lines
9.2 KiB
C
/*
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* drivers/video/tegra/host/gk20a/gr_ctx_sim_gk20a.c
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*
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* GK20A Graphics Context for Simulation
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*
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "gk20a.h"
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#include "sim_gk20a.h"
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#include "gr_ctx_gk20a.h"
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int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
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{
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int err = 0;
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u32 i, temp;
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gk20a_dbg(gpu_dbg_fn | gpu_dbg_info,
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"querying grctx info from chiplib");
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g->gr.ctx_vars.dynamic = true;
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g->gr.netlist = GR_NETLIST_DYNAMIC;
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/* query sizes and counts */
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0,
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&g->gr.ctx_vars.ucode.fecs.inst.count);
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0,
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&g->gr.ctx_vars.ucode.fecs.data.count);
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0,
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&g->gr.ctx_vars.ucode.gpccs.inst.count);
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0,
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&g->gr.ctx_vars.ucode.gpccs.data.count);
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gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp);
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g->gr.ctx_vars.buffer_size = temp << 2;
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gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0,
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&g->gr.ctx_vars.sw_bundle_init.count);
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gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0,
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&g->gr.ctx_vars.sw_method_init.count);
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gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0,
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&g->gr.ctx_vars.sw_ctx_load.count);
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gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
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&g->gr.ctx_vars.sw_veid_bundle_init.count);
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gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
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&g->gr.ctx_vars.sw_non_ctx_load.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.sys.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.gpc.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.tpc.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.pm_sys.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.pm_gpc.count);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0,
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&g->gr.ctx_vars.ctxsw_regs.pm_tpc.count);
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err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.fecs.inst);
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err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.fecs.data);
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err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.gpccs.inst);
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err |= !alloc_u32_list_gk20a(&g->gr.ctx_vars.ucode.gpccs.data);
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err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_bundle_init);
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err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_method_init);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.sw_ctx_load);
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err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_non_ctx_load);
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err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_veid_bundle_init);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.sys);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.gpc);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.tpc);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.zcull_gpc);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.ppc);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.pm_sys);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.pm_gpc);
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err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.pm_tpc);
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if (err)
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goto fail;
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for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++)
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS",
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i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]);
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for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++)
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS",
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i, &g->gr.ctx_vars.ucode.fecs.data.l[i]);
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for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++)
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS",
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i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]);
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for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++)
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gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS",
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i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]);
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for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) {
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struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l;
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gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) {
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struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l;
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gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l;
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gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) {
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struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l;
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gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:REG",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) {
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struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l;
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gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE",
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i, &l[i].value);
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}
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for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) {
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struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l;
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR",
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i, &l[i].addr);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX",
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i, &l[i].index);
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gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE",
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i, &l[i].value);
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}
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g->gr.ctx_vars.valid = true;
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gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0,
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&g->gr.ctx_vars.regs_base_index);
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gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib");
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return 0;
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fail:
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gk20a_err(dev_from_gk20a(g),
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"failed querying grctx info from chiplib");
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return err;
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}
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