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JIRA DNVGPU-184 implement a function which takes noise unaware vmin for logic and sram rails as input and sends them to pmu via RPC Change-Id: Ic0d72daf99870477d4dbd17e1c609dd0c39f8197 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248210 (cherry picked from commit 2ad833c1edf65ada6c72b56ecd3551e7c4d396f6) Reviewed-on: http://git-master/r/1270885 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _VOLT_RAIL_H_
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#define _VOLT_RAIL_H_
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#include "boardobj/boardobj.h"
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#include "boardobj/boardobjgrp.h"
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#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04
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#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFF
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#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
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((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
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#define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \
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(boardobjgrp_idxisvalid( \
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&((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
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#define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \
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(!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super)))
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/*!
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* extends boardobj providing attributes common to all voltage_rails.
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*/
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struct voltage_rail {
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struct boardobj super;
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u32 boot_voltage_uv;
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u8 rel_limit_vfe_equ_idx;
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u8 alt_rel_limit_vfe_equ_idx;
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u8 ov_limit_vfe_equ_idx;
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u8 pwr_equ_idx;
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u8 volt_dev_idx_default;
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u8 boot_volt_vfe_equ_idx;
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u8 vmin_limit_vfe_equ_idx;
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u8 volt_margin_limit_vfe_equ_idx;
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u32 volt_margin_limit_vfe_equ_mon_handle;
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u32 rel_limit_vfe_equ_mon_handle;
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u32 alt_rel_limit_vfe_equ_mon_handle;
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u32 ov_limit_vfe_equ_mon_handle;
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struct boardobjgrpmask_e32 volt_dev_mask;
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s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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};
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/*!
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* metadata of voltage rail functionality.
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*/
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struct voltage_rail_metadata {
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u8 volt_domain_hal;
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u8 pct_delta;
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u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
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u8 logic_rail_idx;
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u8 sram_rail_idx;
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struct boardobjgrp_e32 volt_rails;
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};
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u8 volt_rail_vbios_volt_domain_convert_to_internal
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(struct gk20a *g, u8 vbios_volt_domain);
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u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
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*pvolt_rail, u8 volt_dev_idx, u8 operation_type);
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u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
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u32 volt_rail_sw_setup(struct gk20a *g);
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u32 volt_rail_pmu_setup(struct gk20a *g);
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#endif
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