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abe62f6fe0
-Updated PMU version number to sync with p4 cl #:25133717 -As LS falcon's bootstrap is taken care by SEC2 RTOS so, removed ACRLIB from PMU ucode & disabled WPR init from PMU by setting ops .init_wpr_region to NULL -Adding dummy bytes to PMU supersurface member therm data structure to match with tu10x ucode supersurface change sequence offset. -PMU ucode update to enable ECC interrupt -Enable ECC interrupt in Falcon interrupt source -Enable routing of ECC interrupt to HOST. JIRA NVGPU-1150 Change-Id: Ib49f9bf811dc2a01252461c16a44869e07412005 Reviewed-on: https://git-master.nvidia.com/r/1929895 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1957846 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>