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974ad342fa
Update sec2.c to not dereference struct gk20a and update sec2.h to remove unneeded header files. Move sec2.h to include/nvgpu/sec2. JIRA NVGPU-2074 Change-Id: I1a8f4b1913323693fae422ce27c4ec0ac29de24a Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085752 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
144 lines
3.7 KiB
C
144 lines
3.7 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/log.h>
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#include <nvgpu/sec2/sec2.h>
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#include <nvgpu/sec2/queue.h>
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#include <nvgpu/sec2/cmd.h>
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/* command post operation functions */
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static bool sec2_validate_cmd(struct nvgpu_sec2 *sec2,
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struct nv_flcn_cmd_sec2 *cmd, u32 queue_id)
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{
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struct gk20a *g = sec2->g;
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u32 queue_size;
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if (queue_id != SEC2_NV_CMDQ_LOG_ID) {
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goto invalid_cmd;
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}
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if (cmd->hdr.size < PMU_CMD_HDR_SIZE) {
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goto invalid_cmd;
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}
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queue_size = nvgpu_sec2_queue_get_size(sec2->queues, queue_id);
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if (cmd->hdr.size > (queue_size >> 1)) {
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goto invalid_cmd;
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}
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if (!NV_SEC2_UNITID_IS_VALID(cmd->hdr.unit_id)) {
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goto invalid_cmd;
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}
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return true;
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invalid_cmd:
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nvgpu_err(g, "invalid sec2 cmd :");
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nvgpu_err(g, "queue_id=%d, cmd_size=%d, cmd_unit_id=%d\n",
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queue_id, cmd->hdr.size, cmd->hdr.unit_id);
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return false;
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}
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static int sec2_write_cmd(struct nvgpu_sec2 *sec2,
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struct nv_flcn_cmd_sec2 *cmd, u32 queue_id,
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u32 timeout_ms)
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{
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struct nvgpu_timeout timeout;
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struct gk20a *g = sec2->g;
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int err;
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nvgpu_log_fn(g, " ");
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nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER);
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do {
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err = nvgpu_sec2_queue_push(sec2->queues, queue_id, &sec2->flcn,
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cmd, cmd->hdr.size);
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if ((err == -EAGAIN) &&
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(nvgpu_timeout_expired(&timeout) == 0)) {
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nvgpu_usleep_range(1000U, 2000U);
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} else {
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break;
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}
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} while (true);
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if (err != 0) {
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nvgpu_err(g, "fail to write cmd to queue %d", queue_id);
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}
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return err;
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}
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int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd,
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u32 queue_id, sec2_callback callback,
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void *cb_param, u32 timeout)
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{
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struct nvgpu_sec2 *sec2 = &g->sec2;
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struct sec2_sequence *seq = NULL;
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int err = 0;
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if ((cmd == NULL) || (!sec2->sec2_ready)) {
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if (cmd == NULL) {
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nvgpu_warn(g,
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"%s(): SEC2 cmd buffer is NULL", __func__);
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} else {
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nvgpu_warn(g, "%s(): SEC2 is not ready", __func__);
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}
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err = -EINVAL;
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goto exit;
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}
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/* Sanity check the command input. */
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if (!sec2_validate_cmd(sec2, cmd, queue_id)) {
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err = -EINVAL;
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goto exit;
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}
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/* Attempt to reserve a sequence for this command. */
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err = nvgpu_sec2_seq_acquire(g, &sec2->sequences, &seq,
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callback, cb_param);
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if (err != 0) {
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goto exit;
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}
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/* Set the sequence number in the command header. */
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cmd->hdr.seq_id = nvgpu_sec2_seq_get_id(seq);
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cmd->hdr.ctrl_flags = 0U;
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cmd->hdr.ctrl_flags = PMU_CMD_FLAGS_STATUS;
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nvgpu_sec2_seq_set_state(seq, SEC2_SEQ_STATE_USED);
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err = sec2_write_cmd(sec2, cmd, queue_id, timeout);
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if (err != 0) {
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nvgpu_sec2_seq_set_state(seq, SEC2_SEQ_STATE_PENDING);
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}
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exit:
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return err;
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}
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