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jetson_36.
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95cde7ef1c | ||
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d1aa84175b | ||
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d137833257 | ||
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6475e2b9c3 |
@@ -1,7 +1,7 @@
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# NVIDIA Linux Open GPU Kernel Module Source
|
||||
|
||||
This is the source release of the NVIDIA Linux open GPU kernel modules,
|
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version 540.3.2.
|
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version 540.4.0.
|
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|
||||
|
||||
## How to Build
|
||||
@@ -17,7 +17,7 @@ as root:
|
||||
|
||||
Note that the kernel modules built here must be used with GSP
|
||||
firmware and user-space NVIDIA GPU driver components from a corresponding
|
||||
540.3.2 driver release. This can be achieved by installing
|
||||
540.4.0 driver release. This can be achieved by installing
|
||||
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
|
||||
option. E.g.,
|
||||
|
||||
@@ -180,7 +180,7 @@ software applications.
|
||||
## Compatible GPUs
|
||||
|
||||
The open-gpu-kernel-modules can be used on any Turing or later GPU
|
||||
(see the table below). However, in the 540.3.2 release,
|
||||
(see the table below). However, in the 540.4.0 release,
|
||||
GeForce and Workstation support is still considered alpha-quality.
|
||||
|
||||
To enable use of the open kernel modules on GeForce and Workstation GPUs,
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||||
@@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
|
||||
parameter to 1. For more details, see the NVIDIA GPU driver end user
|
||||
README here:
|
||||
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/540.3.2/README/kernel_open.html
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/540.4.0/README/kernel_open.html
|
||||
|
||||
In the below table, if three IDs are listed, the first is the PCI Device
|
||||
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
|
||||
|
||||
100
commitFile.txt
100
commitFile.txt
@@ -5,12 +5,12 @@ d13779dbbab1c776db15f462cd46b29f2c0f8c7c - Makefile
|
||||
5728867ce2e96b63b29367be6aa1c0e47bcafc8f - SECURITY.md
|
||||
6b73bf6a534ddc0f64e8ba88739381c3b7fb4b5c - nv-compiler.sh
|
||||
ac7f91dfb6c5c469d2d8196c6baebe46ede5aee0 - CHANGELOG.md
|
||||
e232781c94c96872c1404d4affff50acebd871bd - README.md
|
||||
fe4e34f7f517ffe6976a020c22fefcf24ec0c211 - README.md
|
||||
ec5f1eb408e0b650158e0310fb1ddd8e9b323a6f - CONTRIBUTING.md
|
||||
af3ee56442f16029cb9b13537477c384226b22fc - CODE_OF_CONDUCT.md
|
||||
61d353ba0c79a1eae91f759efb8508f3eef0cfd5 - kernel-open/Kbuild
|
||||
41123f5c3015f9a14cf35b7c75c5b720f5fbed07 - kernel-open/Kbuild
|
||||
4f4410c3c8db46e5a98d7a35f7d909a49de6cb43 - kernel-open/Makefile
|
||||
6a9b31e3d157dea5790b05752f5521d2870f88bc - kernel-open/conftest.sh
|
||||
aca7afeeee3cd44b43a8cc8aebacdffd0da96ff9 - kernel-open/conftest.sh
|
||||
0b1508742a1c5a04b6c3a4be1b48b506f4180848 - kernel-open/dkms.conf
|
||||
19a5da412ce1557b721b8550a4a80196f6162ba6 - kernel-open/common/inc/os_dsi_panel_props.h
|
||||
4750735d6f3b334499c81d499a06a654a052713d - kernel-open/common/inc/nv-caps.h
|
||||
@@ -33,7 +33,7 @@ d7ab0ee225361daacd280ff98848851933a10a98 - kernel-open/common/inc/nv-list-helper
|
||||
b02c378ac0521c380fc2403f0520949f785b1db6 - kernel-open/common/inc/nv-dmabuf.h
|
||||
689d6be9302d488000e57a329373feeb14e93798 - kernel-open/common/inc/nv-procfs-utils.h
|
||||
b417d06ed1845f5ed69181d8eb9de6b6a87fa973 - kernel-open/common/inc/nv-firmware.h
|
||||
e6c1a783642af932b1ed8e35810c768de492c070 - kernel-open/common/inc/nv-platform.h
|
||||
a69cfed9725a8ade97036a1cb795e9144be1836d - kernel-open/common/inc/nv-platform.h
|
||||
b986bc6591ba17a74ad81ec4c93347564c6d5165 - kernel-open/common/inc/nvkms-format.h
|
||||
fa267c903e9c449e62dbb6945906400d43417eff - kernel-open/common/inc/nvlimits.h
|
||||
143051f69a53db0e7c5d2f846a9c14d666e264b4 - kernel-open/common/inc/nv-kref.h
|
||||
@@ -53,11 +53,11 @@ d25291d32caef187daf3589ce4976e4fa6bec70d - kernel-open/common/inc/nv-time.h
|
||||
4856fe869a5f3141e5d7f7d1b0a6affad94cbc31 - kernel-open/common/inc/nv-pci.h
|
||||
95bf694a98ba78d5a19e66463b8adda631e6ce4c - kernel-open/common/inc/nvstatus.h
|
||||
b15c5fe5d969414640a2cb374b707c230e7597e4 - kernel-open/common/inc/nv-hash.h
|
||||
36c20e9c111e66601b025802f840e7b87d09cdde - kernel-open/common/inc/nvkms-kapi.h
|
||||
ba72879894c335c61a67f7bae9f6ea94c3b74e1f - kernel-open/common/inc/nvkms-kapi.h
|
||||
f428218ee6f5d0289602495a1cfb287db4fb0823 - kernel-open/common/inc/nv_uvm_interface.h
|
||||
1e7eec6561b04d2d21c3515987aaa116e9401c1f - kernel-open/common/inc/nv-kernel-interface-api.h
|
||||
d51449fa2fd19748007f2e98f0233c92b45f9572 - kernel-open/common/inc/nvkms-api-types.h
|
||||
de6913c5e5092a417530ac9f818497824eab7946 - kernel-open/common/inc/os-interface.h
|
||||
314f2400c5f4342ebec578c24689329ab79e497d - kernel-open/common/inc/nvkms-api-types.h
|
||||
c9120c6a33932c7514608601f82ea85d2386b84f - kernel-open/common/inc/os-interface.h
|
||||
ceac0fe7333f3a67b8fb63de42ab567dd905949f - kernel-open/common/inc/nv-ioctl-numa.h
|
||||
c75bfc368c6ce3fc2c1a0c5062834e90d822b365 - kernel-open/common/inc/nv-memdbg.h
|
||||
1d17329caf26cdf931122b3c3b7edf4932f43c38 - kernel-open/common/inc/nv-msi.h
|
||||
@@ -77,14 +77,14 @@ b8d361216db85fe897cbced2a9600507b7708c61 - kernel-open/nvidia/libspdm_hkdf_sha.c
|
||||
4e5a330fa40dab218821976ac1b530c649d48994 - kernel-open/nvidia/libspdm_ecc.c
|
||||
94c406f36836c3396b0ca08b4ff71496666b9c43 - kernel-open/nvidia/os-usermap.c
|
||||
7ac10bc4b3b1c5a261388c3f5f9ce0e9b35d7b44 - kernel-open/nvidia/nv-usermap.c
|
||||
5ac10d9b20ccd37e1e24d4a81b8ac8f83db981e4 - kernel-open/nvidia/nv-vtophys.c
|
||||
7af675f85642229b7e7de05dcadd622550fe7ad7 - kernel-open/nvidia/nv-vtophys.c
|
||||
d11ab03a617b29efcf00f85e24ebce60f91cf82c - kernel-open/nvidia/nv-backlight.c
|
||||
ef8fd76c55625aeaa71c9b789c4cf519ef6116b2 - kernel-open/nvidia/libspdm_hkdf.c
|
||||
cf90d9ea3abced81d182ab3c4161e1b5d3ad280d - kernel-open/nvidia/nv-rsync.h
|
||||
6710f4603a9d3e14bcaefdf415b1cfff9ec9b7ec - kernel-open/nvidia/libspdm_aead.c
|
||||
d68af9144d3d487308e73d0a52f4474f8047d6ca - kernel-open/nvidia/nv-gpio.c
|
||||
fc22bea3040ae178492cb9c7a62f1d0012b1c113 - kernel-open/nvidia/nv-procfs.c
|
||||
e7a9eb87524d092f9785e35806ef03d96aa3aff7 - kernel-open/nvidia/nv.c
|
||||
aa6cf0ed774330e4afe4eaa55b3463ed31a2f7ae - kernel-open/nvidia/nv.c
|
||||
e0aff92ee8ddec261d8f0d81c41f837503c4b571 - kernel-open/nvidia/nv-dsi-parse-panel-props.c
|
||||
9104dc5f36a825aaf1208b54b167965625d4a433 - kernel-open/nvidia/nv_uvm_interface.c
|
||||
fbae5663e3c278d8206d07ec6446ca4c2781795f - kernel-open/nvidia/nv-ibmnpu.h
|
||||
@@ -95,7 +95,7 @@ dc39c4ee87f4dc5f5ccc179a98e07ddb82bb8bce - kernel-open/nvidia/nv-modeset-interfa
|
||||
70a9117dce7471a07178d9456b146a033d6b544b - kernel-open/nvidia/nv-dma.c
|
||||
0a3ad5cdacfe156b02f53c0087bdc0ec9509cd6a - kernel-open/nvidia/nv-ipc-soc.c
|
||||
06e7ec77cd21c43f900984553a4960064753e444 - kernel-open/nvidia/nv-platform-pm.c
|
||||
c1ebcfec42f7898dd9d909eacd439d288b80523f - kernel-open/nvidia/os-mlock.c
|
||||
04596e9a57955df30de2f21122aa7e38f3c8825a - kernel-open/nvidia/os-mlock.c
|
||||
646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia/nv-kthread-q.c
|
||||
94344ec0af21bd9c7c7ab912f7bd3a8668a3e0aa - kernel-open/nvidia/os-pci.c
|
||||
6e669fe32e4b69dcdbc9739dc8a45fb800547d53 - kernel-open/nvidia/nv-p2p.c
|
||||
@@ -105,7 +105,7 @@ e8daae4e6106429378673988293aaa1fcd80f0eb - kernel-open/nvidia/nv-pci.c
|
||||
8c9fd9590d7e3ad333ae03d5f22b72ffbdbe6e70 - kernel-open/nvidia/nv-dmabuf.c
|
||||
6d4fbea733fdcd92fc6a8a5884e8bb359f9e8abd - kernel-open/nvidia/rmp2pdefines.h
|
||||
b71bf4426322ab59e78e2a1500509a5f4b2b71ab - kernel-open/nvidia/nv-pat.h
|
||||
e1f18e92457844913b9b6613d2f6dca73fc233c3 - kernel-open/nvidia/os-interface.c
|
||||
bb4b87fbfa85a21af5b3ed26cc8ff5cbaae78266 - kernel-open/nvidia/os-interface.c
|
||||
ce537a7d786bd11a4429bf7c59836d5373a66f61 - kernel-open/nvidia/nv-i2c.c
|
||||
8bedc7374d7a43250e49fb09139c511b489d45e3 - kernel-open/nvidia/nv-pci-table.h
|
||||
c7f1aaa6a5f3a3cdf1e5f80adf40b3c9f185fb94 - kernel-open/nvidia/nv-report-err.c
|
||||
@@ -113,7 +113,7 @@ c7f1aaa6a5f3a3cdf1e5f80adf40b3c9f185fb94 - kernel-open/nvidia/nv-report-err.c
|
||||
dd9e367cba9e0672c998ec6d570be38084a365ab - kernel-open/nvidia/libspdm_rand.c
|
||||
37654472e65659be229b5e35c6f25c0724929511 - kernel-open/nvidia/nv-frontend.c
|
||||
8f87a475c202458948025d1521968677fc11dd50 - kernel-open/nvidia/nv-msi.c
|
||||
e5d6dfa062d2d9533760f883bdd36a669d79b759 - kernel-open/nvidia/nv-platform.c
|
||||
6084c207652ea4bc02a6c94275cad00880acc059 - kernel-open/nvidia/nv-platform.c
|
||||
dd819a875c584bc469082fcf519779ea00b1d952 - kernel-open/nvidia/libspdm_aead_aes_gcm.c
|
||||
69f203ad21e643f7b7c85e7e86bd4b674a3536de - kernel-open/nvidia/nv-acpi.c
|
||||
cf98395acb4430a7c105218f7a4b5f7e810b39cf - kernel-open/nvidia/os-registry.c
|
||||
@@ -126,14 +126,14 @@ cf98395acb4430a7c105218f7a4b5f7e810b39cf - kernel-open/nvidia/os-registry.c
|
||||
9883eb32e5d4377c3dce1c7cb54d0e05c05e128b - kernel-open/nvidia/nv-mmap.c
|
||||
68d781e929d103e6fa55fa92b5d4f933fbfb6526 - kernel-open/nvidia/nv-report-err.h
|
||||
95ae148b016e4111122c2d9f8f004b53e78998f3 - kernel-open/nvidia/nv-memdbg.c
|
||||
e3806f50e77b4d6e854c4e84631a1d5fc0f4b710 - kernel-open/nvidia/nvidia.Kbuild
|
||||
af3ddc5641076d1618e5a0d5dcc16c63a3d7d011 - kernel-open/nvidia/nvidia.Kbuild
|
||||
6060392eec4e707ac61ebca3995b6a966eba7fc1 - kernel-open/nvidia/nv-p2p.h
|
||||
7b1bd10726481626dd51f4eebb693794561c20f6 - kernel-open/nvidia/nv-host1x.c
|
||||
11778961efc78ef488be5387fa3de0c1b761c0d9 - kernel-open/nvidia/libspdm_sha.c
|
||||
02b1936dd9a9e30141245209d79b8304b7f12eb9 - kernel-open/nvidia/nv-cray.c
|
||||
2f6e4c6ee6f809097c8b07a7b698e8614bf25e57 - kernel-open/nvidia/nv-caps.c
|
||||
9b701fe42a0e87d62c58b15c553086a608e89f7b - kernel-open/nvidia/nv-frontend.h
|
||||
e2da77ff1bc25c0b1de69af7c09e0bde26c34e30 - kernel-open/nvidia/libspdm_shash.c
|
||||
d2ce61cd7fc2c0d384f9caa40e98bdeb032bab86 - kernel-open/nvidia/libspdm_shash.c
|
||||
fa178a7209f56008e67b553a2c5ad1b2dd383aac - kernel-open/nvidia/hal/library/cryptlib/cryptlib_rng.h
|
||||
34de62da6f880ba8022299c77eddbb11d7fc68d2 - kernel-open/nvidia/hal/library/cryptlib/cryptlib_hash.h
|
||||
95b97f5a3ddcf73ed5d7fa0be9e27aec776d7c13 - kernel-open/nvidia/hal/library/cryptlib/cryptlib_rsa.h
|
||||
@@ -149,31 +149,31 @@ d5ddc354e191d6178625b0df8e8b34e8c3e4c474 - kernel-open/nvidia/library/spdm_lib_c
|
||||
19b5d633f4560d545f622ada0dd352d5aa02c651 - kernel-open/nvidia/library/cryptlib.h
|
||||
7398ff33b24fa58315cc40776bc3451e090aa437 - kernel-open/nvidia/internal/libspdm_lib_config.h
|
||||
487db563f4e5153ffc976fc2aa26636ebb4cd534 - kernel-open/nvidia-drm/nvidia-drm-crtc.h
|
||||
1f0cdee2468f842c06bb84aceef60e0723023084 - kernel-open/nvidia-drm/nvidia-drm-linux.c
|
||||
7c1eb7d5d928bb5677634cedde4a234266d4344d - kernel-open/nvidia-drm/nvidia-drm-linux.c
|
||||
8b2063f0cc2e328f4f986c2ce556cfb626c89810 - kernel-open/nvidia-drm/nvidia-drm-utils.c
|
||||
6d65ea9f067e09831a8196022bfe00a145bec270 - kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.h
|
||||
79bcf373ff7d728740716acde5e2d44e924efefa - kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
|
||||
fe9132110f104ff7ebba922ce6dd66a2d08a998d - kernel-open/nvidia-drm/nvidia-drm-modeset.c
|
||||
f454b9ae53a2c308d6909d197c2b9a6543f7d8c3 - kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
|
||||
4d390f6b4c50510ffa5aca47977ec12e47b3947c - kernel-open/nvidia-drm/nvidia-drm-modeset.c
|
||||
23586447526d9ffedd7878b6cf5ba00139fadb5e - kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.h
|
||||
99642b76e9a84b5a1d2e2f4a8c7fb7bcd77a44fd - kernel-open/nvidia-drm/nvidia-drm.h
|
||||
66b33e4ac9abe09835635f6776c1222deefad741 - kernel-open/nvidia-drm/nvidia-drm-fb.h
|
||||
2eba218d75f3802d7bab34d0dd6320f872b2d604 - kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h
|
||||
c52acdbc07f16aa78570d9e6a7f62e493264fde1 - kernel-open/nvidia-drm/nvidia-drm-helper.c
|
||||
dc0fe38909e2f38e919495b7b4f21652a035a3ee - kernel-open/nvidia-drm/nvidia-drm.c
|
||||
4b68b6cb0f98116376be36733f5ae60eec85d78d - kernel-open/nvidia-drm/nvidia-drm-ioctl.h
|
||||
ae6efc1bbec8a5e948b7244f4801f0b4b398f203 - kernel-open/nvidia-drm/nvidia-drm.c
|
||||
86666530006fc4446d7e3bbe175ce9d3350d8d81 - kernel-open/nvidia-drm/nvidia-drm-ioctl.h
|
||||
511ea7cd9e7778c6adc028ae13377c1a8856b72a - kernel-open/nvidia-drm/nvidia-drm-format.c
|
||||
9a882b31b2acc9e1ad3909c0061eee536e648aae - kernel-open/nvidia-drm/nvidia-drm-drv.h
|
||||
14b62226771ac7d69ea048b567bcf22ab6a59cb7 - kernel-open/nvidia-drm/nvidia-drm-drv.h
|
||||
b91df730fba3c2f9401321557bb1bc2e64bbf980 - kernel-open/nvidia-drm/nvidia-drm-connector.h
|
||||
646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia-drm/nv-kthread-q.c
|
||||
d9221522e02e18b037b8929fbc075dc3c1e58654 - kernel-open/nvidia-drm/nv-pci-table.c
|
||||
eb98761cdc99141ad937966e5533c57189db376a - kernel-open/nvidia-drm/nvidia-drm-fence.h
|
||||
eca70b3b8146903ec678a60eebb0462e6ccf4569 - kernel-open/nvidia-drm/nvidia-drm-encoder.h
|
||||
b1bc97e6e0564f1526dedaf8bb68d081fc509cc7 - kernel-open/nvidia-drm/nvidia-drm-helper.h
|
||||
273d0cafeb0f21bf9b7d189f2dc6278e1a3c9672 - kernel-open/nvidia-drm/nvidia-drm-os-interface.h
|
||||
55e26337c0d52b5ec4f6ab403e9306417d2893f8 - kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
|
||||
f92b90d05b58d7097b6762016b351a300eaf93cc - kernel-open/nvidia-drm/nvidia-drm-drv.c
|
||||
2a48c9643c836a1b0a0c133afa9439b4f5ce0feb - kernel-open/nvidia-drm/nvidia-drm-os-interface.h
|
||||
b83e4c3ba825a75233eaedb0ac33feed74a53ab7 - kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
|
||||
b8128c6806ef60d0f0c59bd93ee84fc0fdf47f62 - kernel-open/nvidia-drm/nvidia-drm-drv.c
|
||||
203295380efca7e422746805437b05ce22505424 - kernel-open/nvidia-drm/nvidia-drm-gem.c
|
||||
672afea77ca2c2575f278d9e182ba1188e35e971 - kernel-open/nvidia-drm/nvidia-drm-encoder.c
|
||||
c1a318e90decef16aa29768ea5c8946becc5a4a0 - kernel-open/nvidia-drm/nvidia-drm-encoder.c
|
||||
8bedc7374d7a43250e49fb09139c511b489d45e3 - kernel-open/nvidia-drm/nv-pci-table.h
|
||||
044071d60c8cc8ea66c6caaf1b70fe01c4081ad3 - kernel-open/nvidia-drm/nvidia-drm-conftest.h
|
||||
ec550cba2bebff2c5054b6e12fc43d81e37ade48 - kernel-open/nvidia-drm/nvidia-dma-fence-helper.h
|
||||
@@ -181,17 +181,17 @@ e362c64aa67b47becdbf5c8ba2a245e135adeedf - kernel-open/nvidia-drm/nvidia-drm-gem
|
||||
492a1b0b02dcd2d60f05ac670daeeddcaa4b0da5 - kernel-open/nvidia-drm/nvidia-dma-resv-helper.h
|
||||
61c61f91d1a29d6f7794a67eac337152b58aaac0 - kernel-open/nvidia-drm/nvidia-drm-connector.c
|
||||
97b6c56b1407de976898e0a8b5a8f38a5211f8bb - kernel-open/nvidia-drm/nvidia-drm-format.h
|
||||
c1af941dd5144b05995dcf5721652a4f126e175f - kernel-open/nvidia-drm/nvidia-drm-priv.h
|
||||
b4cdad1b38e8fdac0f2c3ef8ebeb73a83973eed1 - kernel-open/nvidia-drm/nvidia-drm-priv.h
|
||||
deb00fa4d1de972d93d8e72355d81ba87044c86f - kernel-open/nvidia-drm/nvidia-drm-fence.c
|
||||
8a8b431f45bd0fe477759c1527d792cb9a1fa3f5 - kernel-open/nvidia-drm/nvidia-drm-gem.h
|
||||
6528efa1f8061678b8543c5c0be8761cab860858 - kernel-open/nvidia-drm/nvidia-drm-modeset.h
|
||||
c4e015832f97c367b0717fce6cd56e5619ce712c - kernel-open/nvidia-drm/nvidia-drm.Kbuild
|
||||
7e87b94b550dbfba205959932a22cf943a4adb26 - kernel-open/nvidia-drm/nvidia-drm.Kbuild
|
||||
40b5613d1fbbe6b74bff67a5d07974ad321f75f0 - kernel-open/nvidia-drm/nvidia-drm-utils.h
|
||||
8da06bd922850e840c94ed380e3b92c63aecbf70 - kernel-open/nvidia-drm/nvidia-drm-fb.c
|
||||
c14c141137ddcf2b9fff0c66213098b2dbb7e868 - kernel-open/nvidia-drm/nvidia-drm-crtc.c
|
||||
50dd67b47a78026eb087020dadb9f706cdaa94d2 - kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
|
||||
5c05b2b133edb91665fbf937d8cea3a92089aa33 - kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
252660f72b80add6f6071dd0b86288dda8dbb168 - kernel-open/nvidia-modeset/nvkms.h
|
||||
2f49d56a57e1dcb1ded646bf606172890a0f2dc7 - kernel-open/nvidia-drm/nvidia-drm-crtc.c
|
||||
372ea4c8e7bbc0bdeb899e6f163c8f20c663ad22 - kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
|
||||
e02497b93f0f13d8e1624ff2effe417ec63bc2b0 - kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
0a0650835e8835d32418891a2fd25031f5d8770e - kernel-open/nvidia-modeset/nvkms.h
|
||||
646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia-modeset/nv-kthread-q.c
|
||||
7dbe6f8405e47c1380c6151c7c7d12b0b02ef7f4 - kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - kernel-open/nvidia-modeset/nvkms-ioctl.h
|
||||
@@ -363,7 +363,7 @@ e0c551dc47bc06f8dff5884affdeb05eb118609f - src/common/sdk/nvidia/inc/ctrl/ctrl00
|
||||
7edd8cdb8061ec137bc29d0dbbfbb5d169c0fd35 - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080perf.h
|
||||
ccba5f12df1bce4b4235eed5a1c7a0cd2612c2ce - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h
|
||||
a3328cf6633f9b04258eff05ce30e66cc6930310 - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080cipher.h
|
||||
316494234df96c6af34cc0bd2b1c791dc42ac92b - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
|
||||
a427892e601a4ca4f88cc5778ff78895324f3728 - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080unix.h
|
||||
92ff82d1045933baa79958a9f6efd451b0123e95 - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
|
||||
ec7b09fe14c31c175e0abfcfa85dee20d57d02b4 - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080clk.h
|
||||
68bdc682ee42784c09409cd581bb991f7fc1bf41 - src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h
|
||||
@@ -490,7 +490,7 @@ e670ffdd499c13e5025aceae5541426ab2ab0925 - src/common/inc/gps.h
|
||||
5257e84f2048b01258c78cec70987f158f6b0c44 - src/common/inc/nvlog_inc.h
|
||||
b58ed1b4372a5c84d5f3755b7090b196179a2729 - src/common/inc/nv_speculation_barrier.h
|
||||
d877f4b99ae7d18cc5c78b85e89c0a7e3f3e8418 - src/common/inc/nvPNPVendorIds.h
|
||||
b777cb738d82ba6f28169fcc7e28d12288642016 - src/common/inc/nvUnixVersion.h
|
||||
cd9253d1a83b171ca5aa514bc24ac87f2f9af961 - src/common/inc/nvUnixVersion.h
|
||||
1fc95a17ddb619570063f6707d6a395684bfa884 - src/common/inc/displayport/dpcd20.h
|
||||
90998aac8685a403fdec9ff875f7436373d76f71 - src/common/inc/displayport/dpcd14.h
|
||||
669268ea1660e9e5b876f90da003599ba01356bb - src/common/inc/displayport/displayport.h
|
||||
@@ -596,7 +596,7 @@ a1f52f0f78eec1d98b30b0f08bc1c5e88ae3d396 - src/common/modeset/hdmipacket/nvhdmip
|
||||
67db549636b67a32d646fb7fc6c8db2f13689ecc - src/common/modeset/hdmipacket/nvhdmipkt_9271.c
|
||||
e6d500269128cbd93790fe68fbcad5ba45c2ba7d - src/common/modeset/hdmipacket/nvhdmipkt_C371.c
|
||||
f2b434ed8bdd7624143654b7b3953d8c92e5a8e2 - src/common/modeset/hdmipacket/nvhdmipkt_common.h
|
||||
b882497ae393bf66a728dae395b64ac53602a1a5 - src/common/softfloat/nvidia/nv-softfloat.h
|
||||
33a5c7cd8cf4ecb7d9a76c9b623372949b538fc8 - src/common/softfloat/nvidia/nv-softfloat.h
|
||||
be9407a273620c0ba619b53ed72d59d52620c3e4 - src/common/softfloat/nvidia/platform.h
|
||||
f6d98979ab2d1e2b0d664333104130af6abbcad5 - src/common/softfloat/source/f64_to_i64_r_minMag.c
|
||||
21a6232d93734b01692689258a3fdfbbf4ff089d - src/common/softfloat/source/s_roundToUI32.c
|
||||
@@ -705,7 +705,7 @@ ae7d5cb2c57beeea12724e09d957e233a71c12a1 - src/nvidia/arch/nvalloc/unix/include/
|
||||
1e89b4a52a5cdc6cac511ff148c7448d53cf5d5c - src/nvidia/arch/nvalloc/unix/include/os_custom.h
|
||||
499e72dad20bcc283ee307471f8539b315211da4 - src/nvidia/arch/nvalloc/unix/include/nv-unix-nvos-params-wrappers.h
|
||||
5f2a30347378f2ed028c9fb7c8abea9b6032141c - src/nvidia/arch/nvalloc/unix/include/osapi.h
|
||||
de6913c5e5092a417530ac9f818497824eab7946 - src/nvidia/arch/nvalloc/unix/include/os-interface.h
|
||||
c9120c6a33932c7514608601f82ea85d2386b84f - src/nvidia/arch/nvalloc/unix/include/os-interface.h
|
||||
ddfedb3b81feb09ea9daadf1a7f63f6309ee6e3b - src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h
|
||||
9c7b09c55aabbd670c860bdaf8ec9e8ff254b5e9 - src/nvidia/arch/nvalloc/unix/include/nv-kernel-rmapi-ops.h
|
||||
1d8b347e4b92c340a0e9eac77e0f63b9fb4ae977 - src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numbers.h
|
||||
@@ -715,11 +715,11 @@ ddfedb3b81feb09ea9daadf1a7f63f6309ee6e3b - src/nvidia/arch/nvalloc/unix/include/
|
||||
63edc719390a814eb70290e709634d133ad198cc - src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
|
||||
11c6d988bccbdf49ac241d77e6363c7843a0191f - src/nvidia/arch/nvalloc/unix/src/power-management-tegra.c
|
||||
6ca29f3d6b38fb5d05ff222cd1b79ade811a74b2 - src/nvidia/arch/nvalloc/unix/src/osunix.c
|
||||
ff839a6e0535caf19fb52ec24d33f7368aada796 - src/nvidia/arch/nvalloc/unix/src/unix_console.c
|
||||
7ce04b5b6d90c9a433af667c8644b8e328af9968 - src/nvidia/arch/nvalloc/unix/src/unix_console.c
|
||||
b5b409625fde1b640e4e93276e35248f0fccfa4c - src/nvidia/arch/nvalloc/unix/src/gcc_helper.c
|
||||
16e1482d8a9287bc2fd3da28dd62066e4e3ff92b - src/nvidia/arch/nvalloc/unix/src/exports-stubs.c
|
||||
15920addb99f39201a7a7cc9c4e7a9e22c13d118 - src/nvidia/arch/nvalloc/unix/src/osinit.c
|
||||
4971626589ae66cc273ad11b80f0ab875fb39c05 - src/nvidia/arch/nvalloc/unix/src/osapi.c
|
||||
b7f20cd0a65957e5f5639cb561ca14893ee024cb - src/nvidia/arch/nvalloc/unix/src/osapi.c
|
||||
eccfc4f261fd8531254eb2961120073aac9847db - src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c
|
||||
690927567b5344c8030e2c52d91f824bb94e956c - src/nvidia/arch/nvalloc/unix/src/registry.c
|
||||
a28937330829b4f27a9da5e2c3776ceb293b6085 - src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c
|
||||
@@ -1069,7 +1069,7 @@ fc39cb6ac6e9d73bd1ab98890e6b253217d6cc90 - src/nvidia/src/kernel/diagnostics/nvl
|
||||
1fad27934185df50c1d91b5536d0df437618382f - src/nvidia/src/kernel/os/os_init.c
|
||||
c8c4af5a28740f1e66ff4e6e9c47fc6c981ce46b - src/nvidia/src/kernel/os/os_timer.c
|
||||
0e0c1b862bdba245297ffd4f725001fa2439cddf - src/nvidia/src/kernel/os/os_sanity.c
|
||||
1dc0be7577b4f7914743379943bcf0d5e236eb0b - src/nvidia/src/kernel/os/os_stubs.c
|
||||
0f10f992879cdea2a2e3d5f19589ad66b518a872 - src/nvidia/src/kernel/os/os_stubs.c
|
||||
b4dc306ae4d4f8850571e2fbbed0114d63f1ba93 - src/nvidia/src/kernel/rmapi/entry_points.c
|
||||
bac6ef63d11e87f9a4af3318d5be6860f861a0b9 - src/nvidia/src/kernel/rmapi/rpc_common.c
|
||||
96f763eef08f1954d3f07639053db2cde2a01e39 - src/nvidia/src/kernel/rmapi/rmapi.c
|
||||
@@ -1149,7 +1149,7 @@ c6e78a54a1b8d4ca6fe4b01d83e3199ea41606d7 - src/nvidia/src/kernel/gpu/mem_mgr/con
|
||||
f30ae0e8e1e32d0adb7e52b8995c277637b6bc2a - src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c
|
||||
3c463773f2f970b1764edb231d349164fe4341fc - src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
|
||||
2bb921b462c4b50d1f42b39b4728374c7433c8cb - src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102_base.c
|
||||
5a053caaa8eb655d9e0f7ab42ec1b3f0b72fb787 - src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
|
||||
cc1249dcc4c4530c59f0aa314dbcd8f7a69be009 - src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
|
||||
7f9874d9af6b937dac888a3ebb55a82c2a5de71b - src/nvidia/src/kernel/gpu/dce_client/dce_client.c
|
||||
d5d8ff429d3bda7103bafcb2dca94678efc8ddd8 - src/nvidia/src/kernel/gpu_mgr/gpu_group.c
|
||||
719d890f8160efe57e4c3267db65885ebb66cd03 - src/nvidia/src/kernel/gpu_mgr/gpu_db.c
|
||||
@@ -1204,11 +1204,11 @@ d05ef9a837f2927fe387e7d157ea76c7ef567807 - src/nvidia-modeset/include/nvkms-lut.
|
||||
15dddd9307fa7ac201bd9ebc1e35e6ac0d2cf6c9 - src/nvidia-modeset/include/nvkms-evo.h
|
||||
4a94381bd8c24b09193577d3f05d6d61f178e1cf - src/nvidia-modeset/include/nvkms-ctxdma.h
|
||||
11bae7c491bbb0ba4cad94b645d47c384191fa5c - src/nvidia-modeset/include/nvkms-flip.h
|
||||
c869ccfcda419d80b6691d3667c4e9196493065e - src/nvidia-modeset/include/nvkms-modeset-types.h
|
||||
041f03c5a566d8549843405cd3e6e0a3520d014d - src/nvidia-modeset/include/nvkms-modeset-types.h
|
||||
260b6ef87c755e55a803adad4ce49f2d57315f9a - src/nvidia-modeset/include/nvkms-event.h
|
||||
35fa1444c57f7adbbddddc612237f3ad38cdd78f - src/nvidia-modeset/include/nvkms-rmapi.h
|
||||
118d0ea84ff81de16fbdc2c7daf249ee5c82ed6e - src/nvidia-modeset/include/nvkms-modepool.h
|
||||
691731826d6daa3bb5a3847a3dd2424d513113c4 - src/nvidia-modeset/include/nvkms-types.h
|
||||
472c68eb149714b9fe9a5c3b052f60144e9ba297 - src/nvidia-modeset/include/nvkms-types.h
|
||||
4a33d410f090fd4f4dfc9a6de285f8e8fb1c9ced - src/nvidia-modeset/include/nvkms-surface.h
|
||||
b0d407b0413453ec71481f84cc448d090b90d609 - src/nvidia-modeset/include/nvkms-evo3.h
|
||||
8c7e0e15c1038fe518e98d8f86fafb250b10a1d2 - src/nvidia-modeset/include/nvkms-stereo.h
|
||||
@@ -1219,18 +1219,18 @@ a8fbb7a071c0e7b326f384fed7547e7b6ec81c3e - src/nvidia-modeset/include/dp/nvdp-ti
|
||||
ae43c46687d16b93189047d9eeed933a67e5571f - src/nvidia-modeset/include/dp/nvdp-connector.h
|
||||
727bd77cfbc9ac4989c2ab7eec171ceb516510aa - src/nvidia-modeset/kapi/include/nvkms-kapi-notifiers.h
|
||||
27612b72a77ac67cd468ac7f15948d2ad78defed - src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h
|
||||
67fe73dc7149daf807194bd9a0f96252cb452179 - src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
8a6f30959567fa85df3ded73a5c54c67a23b5fd3 - src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
01d943d6edb0c647c2b8dbc44460948665b03e7a - src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c
|
||||
ce42ceac4c4cf9d249d66ab57ae2f435cd9623fc - src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c
|
||||
80c2c9a2a05beb0202239db8b0dd7080ff21c194 - src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h
|
||||
36c20e9c111e66601b025802f840e7b87d09cdde - src/nvidia-modeset/kapi/interface/nvkms-kapi.h
|
||||
fd64ffbcc1efd446fb3352ceaa8bd4221b23a1d2 - src/nvidia-modeset/src/nvkms-modeset.c
|
||||
ba72879894c335c61a67f7bae9f6ea94c3b74e1f - src/nvidia-modeset/kapi/interface/nvkms-kapi.h
|
||||
89bd2f4757d3b901071e523a981903834cca2d7f - src/nvidia-modeset/src/nvkms-modeset.c
|
||||
b7232f4b4b8f0d4c395c241c451fc17b6ab84d7f - src/nvidia-modeset/src/nvkms-evo.c
|
||||
7d0e38f9d79e0c928bdc67276b8ecb0c18470b88 - src/nvidia-modeset/src/nvkms-hw-flip.c
|
||||
6a35b80a6995777dc9500cac9659e6f0f0c12d23 - src/nvidia-modeset/src/nvkms-cursor3.c
|
||||
710b38a93fee94fa4659309451bd4e7baa7ff0d6 - src/nvidia-modeset/src/nvkms-rm.c
|
||||
30ad7839985dea46e6b6d43499210a3056da51ad - src/nvidia-modeset/src/nvkms-utils-flip.c
|
||||
96296baa35ea2367f1fd6ee2c99fa0107c126849 - src/nvidia-modeset/src/nvkms-evo3.c
|
||||
1769a95e465762c8efa53cf17c40679754292003 - src/nvidia-modeset/src/nvkms-evo3.c
|
||||
b13bd89b5ac60ceab56e9c2398cf7668375ab7ad - src/nvidia-modeset/src/nvkms-flip.c
|
||||
3e723edf2a0a2f4f93032feb4aeaaf7fd0acddfa - src/nvidia-modeset/src/g_nvkms-evo-states.c
|
||||
761c8540278a1ffb9fe4aa0adb1b4ee95524787a - src/nvidia-modeset/src/nvkms-hal.c
|
||||
@@ -1240,7 +1240,7 @@ bd2e4a6102432d4ac1faf92b5d3db29e9e3cfafc - src/nvidia-modeset/src/nvkms-utils.c
|
||||
9a8746ee4a4e772b8ac13f06dc0de8a250fdb4c7 - src/nvidia-modeset/src/nvkms-ctxdma.c
|
||||
eb99e694dc088194091e33ed73c01b745c3b939e - src/nvidia-modeset/src/nvkms-hdmi.c
|
||||
2fa9d9b3cbeeb9406f2dd51a4f4a5d53844a31c9 - src/nvidia-modeset/src/nvkms-dpy.c
|
||||
a49319a235d8746b771a7c418277e168a291259f - src/nvidia-modeset/src/nvkms.c
|
||||
083cd2c0d7e9e0f351e15a5ad85cdbd50a583d13 - src/nvidia-modeset/src/nvkms.c
|
||||
dff88ceaf95239b51b60af915f92e389bb844425 - src/nvidia-modeset/src/nvkms-cursor.c
|
||||
2b304663f2a005b5ccdecfafb69a3407f2feeb18 - src/nvidia-modeset/src/nvkms-evo2.c
|
||||
94e9c19b7b6a5e56fd46b0885e7dd6fe698fe2df - src/nvidia-modeset/src/nvkms-prealloc.c
|
||||
@@ -1259,7 +1259,7 @@ f4a02d5b6cb1fa5d461514b21e13002ad9cfa1a4 - src/nvidia-modeset/src/nvkms-evo1.c
|
||||
6f2eb25d57d2dc3c1e5db869cfbdf556878d3332 - src/nvidia-modeset/src/nvkms-console-restore.c
|
||||
933829ff39c6d1fe41bd82a5af177f5059b4b69e - src/nvidia-modeset/src/nvkms-modepool.c
|
||||
403e6dbff0a607c2aecf3204c56633bd7b612ae2 - src/nvidia-modeset/src/nvkms-stereo.c
|
||||
bf1b007fceaa1c38771f9e7d1130f9c0c3eddd80 - src/nvidia-modeset/src/nvkms-lut.c
|
||||
93ab81a362c4ba29ed817dd14fbd75f2b36b62b8 - src/nvidia-modeset/src/nvkms-lut.c
|
||||
f96cd982b4c05351faa31d04ac30d6fa7c866bcb - src/nvidia-modeset/src/dp/nvdp-timer.cpp
|
||||
6b985fc50b5040ce1a81418bed73a60edb5d3289 - src/nvidia-modeset/src/dp/nvdp-timer.hpp
|
||||
a90b2c295271631b4c3abe6afb8dfd92d6b429c8 - src/nvidia-modeset/src/dp/nvdp-connector.cpp
|
||||
@@ -1269,10 +1269,10 @@ a2a4b7063fa903cc434163ebceb7c8d48f703c33 - src/nvidia-modeset/src/dp/nvdp-connec
|
||||
51af3c1ee6b74ee0c9add3fb7d50cbc502980789 - src/nvidia-modeset/src/dp/nvdp-evo-interface.hpp
|
||||
110ac212ee8832c3fa3c4f45d6d33eed0301e992 - src/nvidia-modeset/src/dp/nvdp-host.cpp
|
||||
69fed95ab3954dd5cb26590d02cd8ba09cdff1ac - src/nvidia-modeset/src/dp/nvdp-connector-event-sink.hpp
|
||||
50dd67b47a78026eb087020dadb9f706cdaa94d2 - src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
|
||||
252660f72b80add6f6071dd0b86288dda8dbb168 - src/nvidia-modeset/os-interface/include/nvkms.h
|
||||
4da2125966732a80fc154cea4b18b2372b12501e - src/nvidia-modeset/interface/nvkms-api.h
|
||||
372ea4c8e7bbc0bdeb899e6f163c8f20c663ad22 - src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
|
||||
0a0650835e8835d32418891a2fd25031f5d8770e - src/nvidia-modeset/os-interface/include/nvkms.h
|
||||
5c987d408208e74a7e0e50d79e96508b07955d8e - src/nvidia-modeset/interface/nvkms-api.h
|
||||
b986bc6591ba17a74ad81ec4c93347564c6d5165 - src/nvidia-modeset/interface/nvkms-format.h
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - src/nvidia-modeset/interface/nvkms-ioctl.h
|
||||
d51449fa2fd19748007f2e98f0233c92b45f9572 - src/nvidia-modeset/interface/nvkms-api-types.h
|
||||
314f2400c5f4342ebec578c24689329ab79e497d - src/nvidia-modeset/interface/nvkms-api-types.h
|
||||
8e3e74d2b3f45381e7b0012d930cf451cbd1728f - src/nvidia-modeset/interface/nvkms-sync.h
|
||||
|
||||
@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
|
||||
EXTRA_CFLAGS += -I$(src)
|
||||
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
|
||||
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"540.3.2\"
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"540.4.0\"
|
||||
|
||||
ifneq ($(SYSSRCHOST1X),)
|
||||
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
|
||||
@@ -290,7 +290,6 @@ NV_HEADER_PRESENCE_TESTS = \
|
||||
linux/of_platform.h \
|
||||
linux/of_device.h \
|
||||
linux/of_gpio.h \
|
||||
linux/of_clk.h \
|
||||
linux/gpio.h \
|
||||
linux/gpio/consumer.h \
|
||||
linux/interconnect.h \
|
||||
|
||||
@@ -35,6 +35,4 @@ int nv_platform_count_devices(void);
|
||||
int nv_soc_register_irqs(nv_state_t *nv);
|
||||
void nv_soc_free_irqs(nv_state_t *nv);
|
||||
|
||||
int nv_disable_simplefb_clocks(void);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -554,6 +554,23 @@ enum NvKmsInputColorSpace {
|
||||
|
||||
/* PQ, Rec.2020 unity */
|
||||
NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
|
||||
|
||||
/* sRGB colorspace with sRGB gamma transfer function */
|
||||
NVKMS_INPUT_COLORSPACE_SRGB = 3,
|
||||
|
||||
/* Rec709 colorspace with Rec709 gamma transfer function */
|
||||
NVKMS_INPUT_COLORSPACE_REC709 = 4,
|
||||
|
||||
/* Rec709 colorspace with linear (identity) gamma */
|
||||
NVKMS_INPUT_COLORSPACE_REC709_LINEAR = 5
|
||||
};
|
||||
|
||||
enum NvKmsOutputColorSpace {
|
||||
/* Unknown colorspace; no re-gamma will be applied */
|
||||
NVKMS_OUTPUT_COLORSPACE_NONE = 0,
|
||||
|
||||
/* sRGB gamma transfer function will be applied */
|
||||
NVKMS_OUTPUT_COLORSPACE_SRGB = 1
|
||||
};
|
||||
|
||||
enum NvKmsOutputTf {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -411,6 +411,14 @@ struct NvKmsKapiDynamicDisplayParams {
|
||||
NvBool forceDisconnected;
|
||||
};
|
||||
|
||||
struct NvKmsKapiVtFbParams {
|
||||
/* [OUT] VT framebuffer memory base address */
|
||||
NvU64 baseAddress;
|
||||
|
||||
/* [OUT] VT framebuffer memory size */
|
||||
NvU64 size;
|
||||
};
|
||||
|
||||
struct NvKmsKapiCreateSurfaceParams {
|
||||
|
||||
/* [IN] Parameter of each plane */
|
||||
@@ -455,6 +463,8 @@ typedef enum NvKmsKapiRegisterWaiterResultRec {
|
||||
NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED,
|
||||
} NvKmsKapiRegisterWaiterResult;
|
||||
|
||||
typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend);
|
||||
|
||||
struct NvKmsKapiFunctionsTable {
|
||||
|
||||
/*!
|
||||
@@ -540,8 +550,8 @@ struct NvKmsKapiFunctionsTable {
|
||||
);
|
||||
|
||||
/*!
|
||||
* Revoke permissions previously granted. Only one (dispIndex, head,
|
||||
* display) is currently supported.
|
||||
* Revoke modeset permissions previously granted. Only one (dispIndex,
|
||||
* head, display) is currently supported.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
@@ -558,6 +568,34 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvKmsKapiDisplay display
|
||||
);
|
||||
|
||||
/*!
|
||||
* Grant modeset sub-owner permissions to fd. This is used by clients to
|
||||
* convert drm 'master' permissions into nvkms sub-owner permission.
|
||||
*
|
||||
* \param [in] fd fd from opening /dev/nvidia-modeset.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*grantSubOwnership)
|
||||
(
|
||||
NvS32 fd,
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
|
||||
/*!
|
||||
* Revoke sub-owner permissions previously granted.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*revokeSubOwnership)
|
||||
(
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
|
||||
/*!
|
||||
* Registers for notification, via
|
||||
* NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified
|
||||
@@ -679,6 +717,20 @@ struct NvKmsKapiFunctionsTable {
|
||||
struct NvKmsKapiDynamicDisplayParams *params
|
||||
);
|
||||
|
||||
/*!
|
||||
* Get VT framebuffer information.
|
||||
*
|
||||
* \param [out] params Parameters containing the base address and size
|
||||
* of VT framebuffer memory
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*getVtFbInfo)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
struct NvKmsKapiVtFbParams *params
|
||||
);
|
||||
|
||||
/*!
|
||||
* Allocate some unformatted video memory of the specified size.
|
||||
*
|
||||
@@ -1336,6 +1388,15 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvU64 index,
|
||||
NvU64 new_value
|
||||
);
|
||||
|
||||
/*!
|
||||
* Set the callback function for suspending and resuming the display system.
|
||||
*/
|
||||
void
|
||||
(*setSuspendResumeCallback)
|
||||
(
|
||||
NvKmsKapiSuspendResumeCallbackFunc *function
|
||||
);
|
||||
};
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -162,7 +162,7 @@ NvBool NV_API_CALL os_is_vgx_hyper (void);
|
||||
NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32);
|
||||
NvBool NV_API_CALL os_is_grid_supported (void);
|
||||
NvU32 NV_API_CALL os_get_grid_csp_support (void);
|
||||
void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64, NvU64);
|
||||
void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *, NvU64, NvU64);
|
||||
void NV_API_CALL os_bug_check (NvU32, const char *);
|
||||
NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32);
|
||||
NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**);
|
||||
|
||||
137
kernel-open/conftest.sh
Executable file → Normal file
137
kernel-open/conftest.sh
Executable file → Normal file
@@ -1652,22 +1652,6 @@ compile_test() {
|
||||
fi
|
||||
;;
|
||||
|
||||
of_clk_get_parent_count)
|
||||
#
|
||||
# Determine if the of_clk_get_parent_count function is present.
|
||||
#
|
||||
CODE="
|
||||
#if defined(NV_LINUX_OF_CLK_H_PRESENT)
|
||||
#include <linux/of_clk.h>
|
||||
#endif
|
||||
void conftest_of_clk_get_parent_count(void)
|
||||
{
|
||||
of_clk_get_parent_count();
|
||||
}
|
||||
"
|
||||
compile_check_conftest "$CODE" "NV_OF_CLK_GET_PARENT_COUNT_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
of_node_to_nid)
|
||||
#
|
||||
# Determine if of_node_to_nid is present
|
||||
@@ -5106,20 +5090,22 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_PCI_CLASS_MULTIMEDIA_HD_AUDIO_PRESENT" "" "generic"
|
||||
;;
|
||||
|
||||
unsafe_follow_pfn)
|
||||
follow_pfn)
|
||||
#
|
||||
# Determine if unsafe_follow_pfn() is present.
|
||||
# Determine if follow_pfn() is present.
|
||||
#
|
||||
# unsafe_follow_pfn() was added by commit 69bacee7f9ad
|
||||
# ("mm: Add unsafe_follow_pfn") in v5.13-rc1.
|
||||
# follow_pfn() was added by commit 3b6748e2dd69
|
||||
# ("mm: introduce follow_pfn()") in v2.6.31-rc1, and removed
|
||||
# by commit 233eb0bf3b94 ("mm: remove follow_pfn")
|
||||
# from linux-next 233eb0bf3b94.
|
||||
#
|
||||
CODE="
|
||||
#include <linux/mm.h>
|
||||
void conftest_unsafe_follow_pfn(void) {
|
||||
unsafe_follow_pfn();
|
||||
void conftest_follow_pfn(void) {
|
||||
follow_pfn();
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_UNSAFE_FOLLOW_PFN_PRESENT" "" "functions"
|
||||
compile_check_conftest "$CODE" "NV_FOLLOW_PFN_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
drm_plane_atomic_check_has_atomic_state_arg)
|
||||
@@ -6459,6 +6445,21 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_HAS_DRIVER_ARG" "" "types"
|
||||
;;
|
||||
|
||||
crypto_tfm_ctx_aligned)
|
||||
# Determine if 'crypto_tfm_ctx_aligned' is defined.
|
||||
#
|
||||
# Removed by commit 25c74a39e0f6 ("crypto: hmac - remove unnecessary
|
||||
# alignment logic") in v6.7.
|
||||
#
|
||||
CODE="
|
||||
#include <crypto/algapi.h>
|
||||
void conftest_crypto_tfm_ctx_aligned(void) {
|
||||
(void)crypto_tfm_ctx_aligned();
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
crypto)
|
||||
#
|
||||
# Determine if we support various crypto functions.
|
||||
@@ -6485,6 +6486,96 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_CRYPTO_PRESENT" "" "symbols"
|
||||
;;
|
||||
|
||||
drm_aperture_remove_conflicting_framebuffers)
|
||||
#
|
||||
# Determine whether drm_aperture_remove_conflicting_framebuffers is present.
|
||||
#
|
||||
# drm_aperture_remove_conflicting_framebuffers was added in commit 2916059147ea
|
||||
# ("drm/aperture: Add infrastructure for aperture ownership) in
|
||||
# v5.14-rc1 (2021-04-12)
|
||||
#
|
||||
CODE="
|
||||
#if defined(NV_DRM_DRM_APERTURE_H_PRESENT)
|
||||
#include <drm/drm_aperture.h>
|
||||
#endif
|
||||
void conftest_drm_aperture_remove_conflicting_framebuffers(void) {
|
||||
drm_aperture_remove_conflicting_framebuffers();
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_FRAMEBUFFERS_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
drm_aperture_remove_conflicting_framebuffers_has_driver_arg)
|
||||
#
|
||||
# Determine whether drm_aperture_remove_conflicting_framebuffers
|
||||
# takes a struct drm_driver * as its fourth argument.
|
||||
#
|
||||
# Prior to commit 97c9bfe3f6605d41eb8f1206e6e0f62b31ba15d6, the
|
||||
# second argument was a char * pointer to the driver's name.
|
||||
#
|
||||
# To test if drm_aperture_remove_conflicting_framebuffers() has
|
||||
# a req_driver argument, define a function with the expected
|
||||
# signature and then define the corresponding function
|
||||
# implementation with the expected signature. Successful compilation
|
||||
# indicates that this function has the expected signature.
|
||||
#
|
||||
# This change occurred in commit 97c9bfe3f660 ("drm/aperture: Pass
|
||||
# DRM driver structure instead of driver name") in v5.15
|
||||
# (2021-06-29).
|
||||
#
|
||||
CODE="
|
||||
#if defined(NV_DRM_DRM_DRV_H_PRESENT)
|
||||
#include <drm/drm_drv.h>
|
||||
#endif
|
||||
#if defined(NV_DRM_DRM_APERTURE_H_PRESENT)
|
||||
#include <drm/drm_aperture.h>
|
||||
#endif
|
||||
typeof(drm_aperture_remove_conflicting_framebuffers) conftest_drm_aperture_remove_conflicting_framebuffers;
|
||||
int conftest_drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size,
|
||||
bool primary, const struct drm_driver *req_driver)
|
||||
{
|
||||
return 0;
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_FRAMEBUFFERS_HAS_DRIVER_ARG" "" "types"
|
||||
;;
|
||||
|
||||
drm_aperture_remove_conflicting_framebuffers_has_no_primary_arg)
|
||||
#
|
||||
# Determine whether drm_aperture_remove_conflicting_framebuffers
|
||||
# has its third argument as a bool.
|
||||
#
|
||||
# Prior to commit 62aeaeaa1b267c5149abee6b45967a5df3feed58, the
|
||||
# third argument was a bool for figuring out whether the legacy vga
|
||||
# stuff should be nuked, but it's only for pci devices and not
|
||||
# really needed in this function.
|
||||
#
|
||||
# To test if drm_aperture_remove_conflicting_framebuffers() has
|
||||
# a bool primary argument, define a function with the expected
|
||||
# signature and then define the corresponding function
|
||||
# implementation with the expected signature. Successful compilation
|
||||
# indicates that this function has the expected signature.
|
||||
#
|
||||
# This change occurred in commit 62aeaeaa1b26 ("drm/aperture: Remove
|
||||
# primary argument") in v6.5 (2023-04-16).
|
||||
#
|
||||
CODE="
|
||||
#if defined(NV_DRM_DRM_DRV_H_PRESENT)
|
||||
#include <drm/drm_drv.h>
|
||||
#endif
|
||||
#if defined(NV_DRM_DRM_APERTURE_H_PRESENT)
|
||||
#include <drm/drm_aperture.h>
|
||||
#endif
|
||||
typeof(drm_aperture_remove_conflicting_framebuffers) conftest_drm_aperture_remove_conflicting_framebuffers;
|
||||
int conftest_drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size,
|
||||
const struct drm_driver *req_driver)
|
||||
{
|
||||
return 0;
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_FRAMEBUFFERS_HAS_NO_PRIMARY_ARG" "" "types"
|
||||
;;
|
||||
|
||||
# When adding a new conftest entry, please use the correct format for
|
||||
# specifying the relevant upstream Linux kernel commit.
|
||||
#
|
||||
|
||||
@@ -652,6 +652,38 @@ static int nv_drm_plane_atomic_get_property(
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* nv_drm_plane_atomic_reset - plane state reset hook
|
||||
* @plane: DRM plane
|
||||
*
|
||||
* Allocate an empty DRM plane state.
|
||||
*/
|
||||
static void nv_drm_plane_atomic_reset(struct drm_plane *plane)
|
||||
{
|
||||
struct nv_drm_plane_state *nv_plane_state =
|
||||
nv_drm_calloc(1, sizeof(*nv_plane_state));
|
||||
|
||||
if (!nv_plane_state) {
|
||||
return;
|
||||
}
|
||||
|
||||
drm_atomic_helper_plane_reset(plane);
|
||||
|
||||
/*
|
||||
* The drm atomic helper function allocates a state object that is the wrong
|
||||
* size. Copy its contents into the one we allocated above and replace the
|
||||
* pointer.
|
||||
*/
|
||||
if (plane->state) {
|
||||
nv_plane_state->base = *plane->state;
|
||||
kfree(plane->state);
|
||||
plane->state = &nv_plane_state->base;
|
||||
} else {
|
||||
kfree(nv_plane_state);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static struct drm_plane_state *
|
||||
nv_drm_plane_atomic_duplicate_state(struct drm_plane *plane)
|
||||
{
|
||||
@@ -711,7 +743,7 @@ static const struct drm_plane_funcs nv_plane_funcs = {
|
||||
.update_plane = drm_atomic_helper_update_plane,
|
||||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
.destroy = nv_drm_plane_destroy,
|
||||
.reset = drm_atomic_helper_plane_reset,
|
||||
.reset = nv_drm_plane_atomic_reset,
|
||||
.atomic_get_property = nv_drm_plane_atomic_get_property,
|
||||
.atomic_set_property = nv_drm_plane_atomic_set_property,
|
||||
.atomic_duplicate_state = nv_drm_plane_atomic_duplicate_state,
|
||||
@@ -768,6 +800,36 @@ static inline void nv_drm_crtc_duplicate_req_head_modeset_config(
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* nv_drm_atomic_crtc_reset - crtc state reset hook
|
||||
* @crtc: DRM crtc
|
||||
*
|
||||
* Allocate an empty DRM crtc state.
|
||||
*/
|
||||
static void nv_drm_atomic_crtc_reset(struct drm_crtc *crtc)
|
||||
{
|
||||
struct nv_drm_crtc_state *nv_state = nv_drm_calloc(1, sizeof(*nv_state));
|
||||
|
||||
if (!nv_state) {
|
||||
return;
|
||||
}
|
||||
|
||||
drm_atomic_helper_crtc_reset(crtc);
|
||||
|
||||
/*
|
||||
* The drm atomic helper function allocates a state object that is the wrong
|
||||
* size. Copy its contents into the one we allocated above and replace the
|
||||
* pointer.
|
||||
*/
|
||||
if (crtc->state) {
|
||||
nv_state->base = *crtc->state;
|
||||
kfree(crtc->state);
|
||||
crtc->state = &nv_state->base;
|
||||
} else {
|
||||
kfree(nv_state);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* nv_drm_atomic_crtc_duplicate_state - crtc state duplicate hook
|
||||
* @crtc: DRM crtc
|
||||
@@ -829,7 +891,7 @@ static void nv_drm_atomic_crtc_destroy_state(struct drm_crtc *crtc,
|
||||
static struct drm_crtc_funcs nv_crtc_funcs = {
|
||||
.set_config = drm_atomic_helper_set_config,
|
||||
.page_flip = drm_atomic_helper_page_flip,
|
||||
.reset = drm_atomic_helper_crtc_reset,
|
||||
.reset = nv_drm_atomic_crtc_reset,
|
||||
.destroy = nv_drm_crtc_destroy,
|
||||
.atomic_duplicate_state = nv_drm_atomic_crtc_duplicate_state,
|
||||
.atomic_destroy_state = nv_drm_atomic_crtc_destroy_state,
|
||||
|
||||
@@ -60,7 +60,17 @@
|
||||
#include <drm/drm_ioctl.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
#include <drm/drm_aperture.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DRM_FBDEV_GENERIC_H_PRESENT)
|
||||
#include <drm/drm_fbdev_generic.h>
|
||||
#endif
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
/*
|
||||
* Commit fcd70cd36b9b ("drm: Split out drm_probe_helper.h")
|
||||
@@ -84,6 +94,11 @@
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#endif
|
||||
|
||||
static int nv_drm_revoke_modeset_permission(struct drm_device *dev,
|
||||
struct drm_file *filep,
|
||||
NvU32 dpyId);
|
||||
static int nv_drm_revoke_sub_ownership(struct drm_device *dev);
|
||||
|
||||
static struct nv_drm_device *dev_list = NULL;
|
||||
|
||||
static const char* nv_get_input_colorspace_name(
|
||||
@@ -383,6 +398,25 @@ static int nv_drm_create_properties(struct nv_drm_device *nv_dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* We can't just call drm_kms_helper_hotplug_event directly because
|
||||
* fbdev_generic may attempt to set a mode from inside the hotplug event
|
||||
* handler. Because kapi event handling runs on nvkms_kthread_q, this blocks
|
||||
* other event processing including the flip completion notifier expected by
|
||||
* nv_drm_atomic_commit.
|
||||
*
|
||||
* Defer hotplug event handling to a work item so that nvkms_kthread_q can
|
||||
* continue processing events while a DRM modeset is in progress.
|
||||
*/
|
||||
static void nv_drm_handle_hotplug_event(struct work_struct *work)
|
||||
{
|
||||
struct delayed_work *dwork = to_delayed_work(work);
|
||||
struct nv_drm_device *nv_dev =
|
||||
container_of(dwork, struct nv_drm_device, hotplug_event_work);
|
||||
|
||||
drm_kms_helper_hotplug_event(nv_dev->dev);
|
||||
}
|
||||
|
||||
static int nv_drm_load(struct drm_device *dev, unsigned long flags)
|
||||
{
|
||||
#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
|
||||
@@ -436,6 +470,22 @@ static int nv_drm_load(struct drm_device *dev, unsigned long flags)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
/*
|
||||
* If fbdev is enabled, take modeset ownership now before other DRM clients
|
||||
* can take master (and thus NVKMS ownership).
|
||||
*/
|
||||
if (nv_drm_fbdev_module_param) {
|
||||
if (!nvKms->grabOwnership(pDevice)) {
|
||||
nvKms->freeDevice(pDevice);
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to grab NVKMS modeset ownership");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
nv_dev->hasFramebufferConsole = NV_TRUE;
|
||||
}
|
||||
#endif
|
||||
|
||||
mutex_lock(&nv_dev->lock);
|
||||
|
||||
/* Set NvKmsKapiDevice */
|
||||
@@ -518,6 +568,7 @@ static int nv_drm_load(struct drm_device *dev, unsigned long flags)
|
||||
|
||||
/* Enable event handling */
|
||||
|
||||
INIT_DELAYED_WORK(&nv_dev->hotplug_event_work, nv_drm_handle_hotplug_event);
|
||||
atomic_set(&nv_dev->enable_event_handling, true);
|
||||
|
||||
init_waitqueue_head(&nv_dev->flip_event_wq);
|
||||
@@ -545,8 +596,20 @@ static void __nv_drm_unload(struct drm_device *dev)
|
||||
return;
|
||||
}
|
||||
|
||||
/* Release modeset ownership if fbdev is enabled */
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
if (nv_dev->hasFramebufferConsole) {
|
||||
drm_atomic_helper_shutdown(dev);
|
||||
nvKms->releaseOwnership(nv_dev->pDevice);
|
||||
}
|
||||
#endif
|
||||
|
||||
cancel_delayed_work_sync(&nv_dev->hotplug_event_work);
|
||||
mutex_lock(&nv_dev->lock);
|
||||
|
||||
WARN_ON(nv_dev->subOwnershipGranted);
|
||||
|
||||
/* Disable event handling */
|
||||
|
||||
atomic_set(&nv_dev->enable_event_handling, false);
|
||||
@@ -596,7 +659,12 @@ static int __nv_drm_master_set(struct drm_device *dev,
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
|
||||
if (!nvKms->grabOwnership(nv_dev->pDevice)) {
|
||||
/*
|
||||
* If this device is driving a framebuffer, then nvidia-drm already has
|
||||
* modeset ownership. Otherwise, grab ownership now.
|
||||
*/
|
||||
if (!nv_dev->hasFramebufferConsole &&
|
||||
!nvKms->grabOwnership(nv_dev->pDevice)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@@ -630,33 +698,39 @@ void nv_drm_master_drop(struct drm_device *dev, struct drm_file *file_priv)
|
||||
#endif
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
int err;
|
||||
|
||||
/*
|
||||
* After dropping nvkms modeset onwership, it is not guaranteed that
|
||||
* drm and nvkms modeset state will remain in sync. Therefore, disable
|
||||
* all outputs and crtcs before dropping nvkms modeset ownership.
|
||||
*
|
||||
* First disable all active outputs atomically and then disable each crtc one
|
||||
* by one, there is not helper function available to disable all crtcs
|
||||
* atomically.
|
||||
*/
|
||||
nv_drm_revoke_modeset_permission(dev, file_priv, 0);
|
||||
nv_drm_revoke_sub_ownership(dev);
|
||||
|
||||
drm_modeset_lock_all(dev);
|
||||
if (!nv_dev->hasFramebufferConsole) {
|
||||
int err;
|
||||
|
||||
if ((err = nv_drm_atomic_helper_disable_all(
|
||||
dev,
|
||||
dev->mode_config.acquire_ctx)) != 0) {
|
||||
/*
|
||||
* After dropping nvkms modeset onwership, it is not guaranteed that drm
|
||||
* and nvkms modeset state will remain in sync. Therefore, disable all
|
||||
* outputs and crtcs before dropping nvkms modeset ownership.
|
||||
*
|
||||
* First disable all active outputs atomically and then disable each
|
||||
* crtc one by one, there is not helper function available to disable
|
||||
* all crtcs atomically.
|
||||
*/
|
||||
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"nv_drm_atomic_helper_disable_all failed with error code %d !",
|
||||
err);
|
||||
drm_modeset_lock_all(dev);
|
||||
|
||||
if ((err = nv_drm_atomic_helper_disable_all(
|
||||
dev,
|
||||
dev->mode_config.acquire_ctx)) != 0) {
|
||||
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"nv_drm_atomic_helper_disable_all failed with error code %d !",
|
||||
err);
|
||||
}
|
||||
|
||||
drm_modeset_unlock_all(dev);
|
||||
|
||||
nvKms->releaseOwnership(nv_dev->pDevice);
|
||||
}
|
||||
|
||||
drm_modeset_unlock_all(dev);
|
||||
|
||||
nvKms->releaseOwnership(nv_dev->pDevice);
|
||||
}
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
|
||||
@@ -840,10 +914,10 @@ static NvU32 nv_drm_get_head_bit_from_connector(struct drm_connector *connector)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *filep)
|
||||
static int nv_drm_grant_modeset_permission(struct drm_device *dev,
|
||||
struct drm_nvidia_grant_permissions_params *params,
|
||||
struct drm_file *filep)
|
||||
{
|
||||
struct drm_nvidia_grant_permissions_params *params = data;
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct nv_drm_connector *target_nv_connector = NULL;
|
||||
struct nv_drm_crtc *target_nv_crtc = NULL;
|
||||
@@ -965,6 +1039,67 @@ done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nv_drm_grant_sub_ownership(struct drm_device *dev,
|
||||
struct drm_nvidia_grant_permissions_params *params)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct drm_modeset_acquire_ctx *pctx;
|
||||
#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3
|
||||
struct drm_modeset_acquire_ctx ctx;
|
||||
DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE,
|
||||
ret);
|
||||
pctx = &ctx;
|
||||
#else
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
pctx = dev->mode_config.acquire_ctx;
|
||||
#endif
|
||||
|
||||
if (nv_dev->subOwnershipGranted ||
|
||||
!nvKms->grantSubOwnership(params->fd, nv_dev->pDevice)) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* When creating an ownership grant, shut down all heads and disable flip
|
||||
* notifications.
|
||||
*/
|
||||
ret = nv_drm_atomic_helper_disable_all(dev, pctx);
|
||||
if (ret != 0) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"nv_drm_atomic_helper_disable_all failed with error code %d!",
|
||||
ret);
|
||||
}
|
||||
|
||||
atomic_set(&nv_dev->enable_event_handling, false);
|
||||
nv_dev->subOwnershipGranted = NV_TRUE;
|
||||
|
||||
ret = 0;
|
||||
|
||||
done:
|
||||
#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3
|
||||
DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
|
||||
#else
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nv_drm_grant_permission_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *filep)
|
||||
{
|
||||
struct drm_nvidia_grant_permissions_params *params = data;
|
||||
|
||||
if (params->type == NV_DRM_PERMISSIONS_TYPE_MODESET) {
|
||||
return nv_drm_grant_modeset_permission(dev, params, filep);
|
||||
} else if (params->type == NV_DRM_PERMISSIONS_TYPE_SUB_OWNER) {
|
||||
return nv_drm_grant_sub_ownership(dev, params);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static bool nv_drm_revoke_connector(struct nv_drm_device *nv_dev,
|
||||
struct nv_drm_connector *nv_connector)
|
||||
{
|
||||
@@ -982,8 +1117,8 @@ static bool nv_drm_revoke_connector(struct nv_drm_device *nv_dev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nv_drm_revoke_permission(struct drm_device *dev,
|
||||
struct drm_file *filep, NvU32 dpyId)
|
||||
static int nv_drm_revoke_modeset_permission(struct drm_device *dev,
|
||||
struct drm_file *filep, NvU32 dpyId)
|
||||
{
|
||||
struct drm_connector *connector;
|
||||
struct drm_crtc *crtc;
|
||||
@@ -1036,14 +1171,55 @@ static int nv_drm_revoke_permission(struct drm_device *dev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nv_drm_revoke_sub_ownership(struct drm_device *dev)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3
|
||||
struct drm_modeset_acquire_ctx ctx;
|
||||
DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE,
|
||||
ret);
|
||||
#else
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
#endif
|
||||
|
||||
if (!nv_dev->subOwnershipGranted) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (!nvKms->revokeSubOwnership(nv_dev->pDevice)) {
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to revoke sub-ownership from NVKMS");
|
||||
goto done;
|
||||
}
|
||||
|
||||
nv_dev->subOwnershipGranted = NV_FALSE;
|
||||
atomic_set(&nv_dev->enable_event_handling, true);
|
||||
ret = 0;
|
||||
|
||||
done:
|
||||
#if NV_DRM_MODESET_LOCK_ALL_END_ARGUMENT_COUNT == 3
|
||||
DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
|
||||
#else
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nv_drm_revoke_permission_ioctl(struct drm_device *dev, void *data,
|
||||
struct drm_file *filep)
|
||||
{
|
||||
struct drm_nvidia_revoke_permissions_params *params = data;
|
||||
if (!params->dpyId) {
|
||||
return -EINVAL;
|
||||
|
||||
if (params->type == NV_DRM_PERMISSIONS_TYPE_MODESET) {
|
||||
if (!params->dpyId) {
|
||||
return -EINVAL;
|
||||
}
|
||||
return nv_drm_revoke_modeset_permission(dev, filep, params->dpyId);
|
||||
} else if (params->type == NV_DRM_PERMISSIONS_TYPE_SUB_OWNER) {
|
||||
return nv_drm_revoke_sub_ownership(dev);
|
||||
}
|
||||
return nv_drm_revoke_permission(dev, filep, params->dpyId);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void nv_drm_postclose(struct drm_device *dev, struct drm_file *filep)
|
||||
@@ -1058,7 +1234,7 @@ static void nv_drm_postclose(struct drm_device *dev, struct drm_file *filep)
|
||||
dev->mode_config.num_connector > 0 &&
|
||||
dev->mode_config.connector_list.next != NULL &&
|
||||
dev->mode_config.connector_list.prev != NULL) {
|
||||
nv_drm_revoke_permission(dev, filep, 0);
|
||||
nv_drm_revoke_modeset_permission(dev, filep, 0);
|
||||
}
|
||||
}
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
@@ -1495,6 +1671,7 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info)
|
||||
struct nv_drm_device *nv_dev = NULL;
|
||||
struct drm_device *dev = NULL;
|
||||
struct device *device = gpu_info->os_device_ptr;
|
||||
bool bus_is_pci;
|
||||
|
||||
DRM_DEBUG(
|
||||
"Registering device for NVIDIA GPU ID 0x08%x",
|
||||
@@ -1528,8 +1705,15 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info)
|
||||
dev->dev_private = nv_dev;
|
||||
nv_dev->dev = dev;
|
||||
|
||||
bus_is_pci =
|
||||
#if defined(NV_LINUX)
|
||||
device->bus == &pci_bus_type;
|
||||
#elif defined(NV_BSD)
|
||||
devclass_find("pci");
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DEVICE_HAS_PDEV)
|
||||
if (device->bus == &pci_bus_type) {
|
||||
if (bus_is_pci) {
|
||||
dev->pdev = to_pci_dev(device);
|
||||
}
|
||||
#endif
|
||||
@@ -1541,6 +1725,42 @@ static void nv_drm_register_drm_device(const nv_gpu_info_t *gpu_info)
|
||||
goto failed_drm_register;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
if (nv_drm_fbdev_module_param &&
|
||||
drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
|
||||
if (bus_is_pci) {
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
|
||||
#if defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_HAS_DRIVER_ARG)
|
||||
drm_aperture_remove_conflicting_pci_framebuffers(pdev, &nv_drm_driver);
|
||||
#else
|
||||
drm_aperture_remove_conflicting_pci_framebuffers(pdev, nv_drm_driver.name);
|
||||
#endif
|
||||
} else {
|
||||
struct NvKmsKapiVtFbParams params;
|
||||
resource_size_t base, size = 0;
|
||||
|
||||
if (nvKms->getVtFbInfo(nv_dev->pDevice, ¶ms)) {
|
||||
|
||||
base = (resource_size_t) params.baseAddress;
|
||||
size = (resource_size_t) params.size;
|
||||
|
||||
#if defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_FRAMEBUFFERS_HAS_DRIVER_ARG)
|
||||
drm_aperture_remove_conflicting_framebuffers(base, size, false, &nv_drm_driver);
|
||||
#elif defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_FRAMEBUFFERS_HAS_NO_PRIMARY_ARG)
|
||||
drm_aperture_remove_conflicting_framebuffers(base, size, &nv_drm_driver);
|
||||
#else
|
||||
drm_aperture_remove_conflicting_framebuffers(base, size, false, nv_drm_driver.name);
|
||||
#endif
|
||||
} else {
|
||||
NV_DRM_DEV_LOG_WARN(nv_dev, "Failed to get framebuffer console info");
|
||||
}
|
||||
}
|
||||
drm_fbdev_generic_setup(dev, 32);
|
||||
}
|
||||
#endif /* defined(NV_DRM_FBDEV_GENERIC_AVAILABLE) */
|
||||
|
||||
/* Add NVIDIA-DRM device into list */
|
||||
|
||||
nv_dev->next = dev_list;
|
||||
@@ -1610,9 +1830,10 @@ void nv_drm_remove_devices(void)
|
||||
{
|
||||
while (dev_list != NULL) {
|
||||
struct nv_drm_device *next = dev_list->next;
|
||||
struct drm_device *dev = dev_list->dev;
|
||||
|
||||
drm_dev_unregister(dev_list->dev);
|
||||
nv_drm_dev_free(dev_list->dev);
|
||||
drm_dev_unregister(dev);
|
||||
nv_drm_dev_free(dev);
|
||||
|
||||
nv_drm_free(dev_list);
|
||||
|
||||
@@ -1620,4 +1841,79 @@ void nv_drm_remove_devices(void)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle system suspend and resume.
|
||||
*
|
||||
* Normally, a DRM driver would use drm_mode_config_helper_suspend() to save the
|
||||
* current state on suspend and drm_mode_config_helper_resume() to restore it
|
||||
* after resume. This works for upstream drivers because user-mode tasks are
|
||||
* frozen before the suspend hook is called.
|
||||
*
|
||||
* In the case of nvidia-drm, the suspend hook is also called when 'suspend' is
|
||||
* written to /proc/driver/nvidia/suspend, before user-mode tasks are frozen.
|
||||
* However, we don't actually need to save and restore the display state because
|
||||
* the driver requires a VT switch to an unused VT before suspending and a
|
||||
* switch back to the application (or fbdev console) on resume. The DRM client
|
||||
* (or fbdev helper functions) will restore the appropriate mode on resume.
|
||||
*
|
||||
*/
|
||||
void nv_drm_suspend_resume(NvBool suspend)
|
||||
{
|
||||
static DEFINE_MUTEX(nv_drm_suspend_mutex);
|
||||
static NvU32 nv_drm_suspend_count = 0;
|
||||
struct nv_drm_device *nv_dev;
|
||||
|
||||
mutex_lock(&nv_drm_suspend_mutex);
|
||||
|
||||
/*
|
||||
* Count the number of times the driver is asked to suspend. Suspend all DRM
|
||||
* devices on the first suspend call and resume them on the last resume
|
||||
* call. This is necessary because the kernel may call nvkms_suspend()
|
||||
* simultaneously for each GPU, but NVKMS itself also suspends all GPUs on
|
||||
* the first call.
|
||||
*/
|
||||
if (suspend) {
|
||||
if (nv_drm_suspend_count++ > 0) {
|
||||
goto done;
|
||||
}
|
||||
} else {
|
||||
BUG_ON(nv_drm_suspend_count == 0);
|
||||
|
||||
if (--nv_drm_suspend_count > 0) {
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
|
||||
nv_dev = dev_list;
|
||||
|
||||
/*
|
||||
* NVKMS shuts down all heads on suspend. Update DRM state accordingly.
|
||||
*/
|
||||
for (nv_dev = dev_list; nv_dev; nv_dev = nv_dev->next) {
|
||||
struct drm_device *dev = nv_dev->dev;
|
||||
|
||||
if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (suspend) {
|
||||
drm_kms_helper_poll_disable(dev);
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 1);
|
||||
#endif
|
||||
drm_mode_config_reset(dev);
|
||||
} else {
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
drm_fb_helper_set_suspend_unlocked(dev->fb_helper, 0);
|
||||
#endif
|
||||
drm_kms_helper_poll_enable(dev);
|
||||
}
|
||||
}
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
|
||||
done:
|
||||
mutex_unlock(&nv_drm_suspend_mutex);
|
||||
}
|
||||
|
||||
#endif /* NV_DRM_AVAILABLE */
|
||||
|
||||
@@ -31,6 +31,8 @@ int nv_drm_probe_devices(void);
|
||||
|
||||
void nv_drm_remove_devices(void);
|
||||
|
||||
void nv_drm_suspend_resume(NvBool suspend);
|
||||
|
||||
#endif /* defined(NV_DRM_AVAILABLE) */
|
||||
|
||||
#endif /* __NVIDIA_DRM_DRV_H__ */
|
||||
|
||||
@@ -300,7 +300,7 @@ void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
|
||||
|
||||
nv_drm_connector_mark_connection_status_dirty(nv_encoder->nv_connector);
|
||||
|
||||
drm_kms_helper_hotplug_event(dev);
|
||||
schedule_delayed_work(&nv_dev->hotplug_event_work, 0);
|
||||
}
|
||||
|
||||
void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
@@ -347,6 +347,6 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
drm_reinit_primary_mode_group(dev);
|
||||
#endif
|
||||
|
||||
drm_kms_helper_hotplug_event(dev);
|
||||
schedule_delayed_work(&nv_dev->hotplug_event_work, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -180,7 +180,35 @@ static void *__nv_drm_gem_nvkms_prime_vmap(
|
||||
}
|
||||
}
|
||||
|
||||
return nv_nvkms_memory->pWriteCombinedIORemapAddress;
|
||||
if (nv_nvkms_memory->physically_mapped) {
|
||||
return nv_nvkms_memory->pWriteCombinedIORemapAddress;
|
||||
}
|
||||
|
||||
/*
|
||||
* If this buffer isn't physically mapped, it might be backed by struct
|
||||
* pages. Use vmap in that case. Do a noncached mapping for system memory
|
||||
* as display is non io-coherent device in case of Tegra.
|
||||
*/
|
||||
if (nv_nvkms_memory->pages_count > 0) {
|
||||
return nv_drm_vmap(nv_nvkms_memory->pages,
|
||||
nv_nvkms_memory->pages_count,
|
||||
false);
|
||||
}
|
||||
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
static void __nv_drm_gem_nvkms_prime_vunmap(
|
||||
struct nv_drm_gem_object *nv_gem,
|
||||
void *address)
|
||||
{
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
|
||||
to_nv_nvkms_memory(nv_gem);
|
||||
|
||||
if (!nv_nvkms_memory->physically_mapped &&
|
||||
nv_nvkms_memory->pages_count > 0) {
|
||||
nv_drm_vunmap(address);
|
||||
}
|
||||
}
|
||||
|
||||
static int __nv_drm_gem_map_nvkms_memory_offset(
|
||||
@@ -228,6 +256,7 @@ const struct nv_drm_gem_object_funcs nv_gem_nvkms_memory_ops = {
|
||||
.free = __nv_drm_gem_nvkms_memory_free,
|
||||
.prime_dup = __nv_drm_gem_nvkms_prime_dup,
|
||||
.prime_vmap = __nv_drm_gem_nvkms_prime_vmap,
|
||||
.prime_vunmap = __nv_drm_gem_nvkms_prime_vunmap,
|
||||
.mmap = __nv_drm_gem_nvkms_mmap,
|
||||
.handle_vma_fault = __nv_drm_gem_nvkms_handle_vma_fault,
|
||||
.create_mmap_offset = __nv_drm_gem_map_nvkms_memory_offset,
|
||||
|
||||
@@ -64,7 +64,8 @@ static void *__nv_drm_gem_user_memory_prime_vmap(
|
||||
struct nv_drm_gem_user_memory *nv_user_memory = to_nv_user_memory(nv_gem);
|
||||
|
||||
return nv_drm_vmap(nv_user_memory->pages,
|
||||
nv_user_memory->pages_count);
|
||||
nv_user_memory->pages_count,
|
||||
true);
|
||||
}
|
||||
|
||||
static void __nv_drm_gem_user_memory_prime_vunmap(
|
||||
|
||||
@@ -289,13 +289,20 @@ struct drm_nvidia_get_connector_id_for_dpy_id_params {
|
||||
uint32_t connectorId; /* OUT */
|
||||
};
|
||||
|
||||
enum drm_nvidia_permissions_type {
|
||||
NV_DRM_PERMISSIONS_TYPE_MODESET = 2,
|
||||
NV_DRM_PERMISSIONS_TYPE_SUB_OWNER = 3
|
||||
};
|
||||
|
||||
struct drm_nvidia_grant_permissions_params {
|
||||
int32_t fd; /* IN */
|
||||
uint32_t dpyId; /* IN */
|
||||
uint32_t type; /* IN */
|
||||
};
|
||||
|
||||
struct drm_nvidia_revoke_permissions_params {
|
||||
uint32_t dpyId; /* IN */
|
||||
uint32_t type; /* IN */
|
||||
};
|
||||
|
||||
struct drm_nvidia_semsurf_fence_ctx_create_params {
|
||||
|
||||
@@ -51,6 +51,14 @@ MODULE_PARM_DESC(
|
||||
bool nv_drm_modeset_module_param = false;
|
||||
module_param_named(modeset, nv_drm_modeset_module_param, bool, 0400);
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
MODULE_PARM_DESC(
|
||||
fbdev,
|
||||
"Create a framebuffer device (1 = enable, 0 = disable (default)) (EXPERIMENTAL)");
|
||||
bool nv_drm_fbdev_module_param = false;
|
||||
module_param_named(fbdev, nv_drm_fbdev_module_param, bool, 0400);
|
||||
#endif
|
||||
|
||||
void *nv_drm_calloc(size_t nmemb, size_t size)
|
||||
{
|
||||
size_t total_size = nmemb * size;
|
||||
@@ -156,9 +164,15 @@ void nv_drm_unlock_user_pages(unsigned long pages_count, struct page **pages)
|
||||
nv_drm_free(pages);
|
||||
}
|
||||
|
||||
void *nv_drm_vmap(struct page **pages, unsigned long pages_count)
|
||||
void *nv_drm_vmap(struct page **pages, unsigned long pages_count, bool cached)
|
||||
{
|
||||
return vmap(pages, pages_count, VM_USERMAP, PAGE_KERNEL);
|
||||
pgprot_t prot = PAGE_KERNEL;
|
||||
|
||||
if (!cached) {
|
||||
prot = pgprot_noncached(PAGE_KERNEL);
|
||||
}
|
||||
|
||||
return vmap(pages, pages_count, VM_USERMAP, prot);
|
||||
}
|
||||
|
||||
void nv_drm_vunmap(void *address)
|
||||
|
||||
@@ -237,6 +237,14 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* If sub-owner permission was granted to another NVKMS client, disallow
|
||||
* modesets through the DRM interface.
|
||||
*/
|
||||
if (nv_dev->subOwnershipGranted) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memset(requested_config, 0, sizeof(*requested_config));
|
||||
|
||||
/* Loop over affected crtcs and construct NvKmsKapiRequestedModeSetConfig */
|
||||
@@ -547,6 +555,9 @@ int nv_drm_atomic_commit(struct drm_device *dev,
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Flip event timeout on head %u", nv_crtc->head);
|
||||
while (!list_empty(&nv_crtc->flip_list)) {
|
||||
__nv_drm_handle_flip_event(nv_crtc);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -58,10 +58,18 @@ typedef struct nv_timer nv_drm_timer;
|
||||
#error "Need to define kernel timer callback primitives for this OS"
|
||||
#endif /* else defined(NV_LINUX) */
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_SETUP_PRESENT) && defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
|
||||
#define NV_DRM_FBDEV_GENERIC_AVAILABLE
|
||||
#endif
|
||||
|
||||
struct page;
|
||||
|
||||
/* Set to true when the atomic modeset feature is enabled. */
|
||||
extern bool nv_drm_modeset_module_param;
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
/* Set to true when the nvidia-drm driver should install a framebuffer device */
|
||||
extern bool nv_drm_fbdev_module_param;
|
||||
#endif
|
||||
|
||||
void *nv_drm_calloc(size_t nmemb, size_t size);
|
||||
|
||||
@@ -76,7 +84,7 @@ int nv_drm_lock_user_pages(unsigned long address,
|
||||
|
||||
void nv_drm_unlock_user_pages(unsigned long pages_count, struct page **pages);
|
||||
|
||||
void *nv_drm_vmap(struct page **pages, unsigned long pages_count);
|
||||
void *nv_drm_vmap(struct page **pages, unsigned long pages_count, bool cached);
|
||||
|
||||
void nv_drm_vunmap(void *address);
|
||||
|
||||
|
||||
@@ -126,6 +126,7 @@ struct nv_drm_device {
|
||||
NvU64 modifiers[6 /* block linear */ + 1 /* linear */ + 1 /* terminator */];
|
||||
#endif
|
||||
|
||||
struct delayed_work hotplug_event_work;
|
||||
atomic_t enable_event_handling;
|
||||
|
||||
/**
|
||||
@@ -146,6 +147,8 @@ struct nv_drm_device {
|
||||
NvBool hasVideoMemory;
|
||||
|
||||
NvBool supportsSyncpts;
|
||||
NvBool subOwnershipGranted;
|
||||
NvBool hasFramebufferConsole;
|
||||
|
||||
struct drm_property *nv_out_fence_property;
|
||||
struct drm_property *nv_input_colorspace_property;
|
||||
|
||||
@@ -84,6 +84,9 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += list_is_first
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += timer_setup
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_fence_set_error
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += sync_file_get_fence
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_generic_setup
|
||||
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type
|
||||
@@ -140,3 +143,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_dumb_destroy
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += fence_ops_use_64bit_seqno
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers_has_driver_arg
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers_has_no_primary_arg
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg
|
||||
|
||||
@@ -45,6 +45,7 @@ int nv_drm_init(void)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
nvKms->setSuspendResumeCallback(nv_drm_suspend_resume);
|
||||
return nv_drm_probe_devices();
|
||||
#else
|
||||
return 0;
|
||||
@@ -54,6 +55,7 @@ int nv_drm_init(void)
|
||||
void nv_drm_exit(void)
|
||||
{
|
||||
#if defined(NV_DRM_AVAILABLE)
|
||||
nvKms->setSuspendResumeCallback(NULL);
|
||||
nv_drm_remove_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -682,6 +682,8 @@ nvkms_event_queue_changed(nvkms_per_open_handle_t *pOpenKernel,
|
||||
|
||||
static void nvkms_suspend(NvU32 gpuId)
|
||||
{
|
||||
nvKmsKapiSuspendResume(NV_TRUE /* suspend */);
|
||||
|
||||
if (gpuId == 0) {
|
||||
nvkms_write_lock_pm_lock();
|
||||
}
|
||||
@@ -700,6 +702,8 @@ static void nvkms_resume(NvU32 gpuId)
|
||||
if (gpuId == 0) {
|
||||
nvkms_write_unlock_pm_lock();
|
||||
}
|
||||
|
||||
nvKmsKapiSuspendResume(NV_FALSE /* suspend */);
|
||||
}
|
||||
|
||||
|
||||
@@ -1452,6 +1456,26 @@ void nvkms_close_from_kapi(struct nvkms_per_open *popen)
|
||||
nvkms_close_pm_unlocked(popen);
|
||||
}
|
||||
|
||||
NvBool nvkms_ioctl_from_kapi_try_pmlock
|
||||
(
|
||||
struct nvkms_per_open *popen,
|
||||
NvU32 cmd, void *params_address, const size_t param_size
|
||||
)
|
||||
{
|
||||
NvBool ret;
|
||||
|
||||
if (nvkms_read_trylock_pm_lock()) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
ret = nvkms_ioctl_common(popen,
|
||||
cmd,
|
||||
(NvU64)(NvUPtr)params_address, param_size) == 0;
|
||||
nvkms_read_unlock_pm_lock();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
NvBool nvkms_ioctl_from_kapi
|
||||
(
|
||||
struct nvkms_per_open *popen,
|
||||
|
||||
@@ -329,6 +329,16 @@ NvBool nvkms_ioctl_from_kapi
|
||||
NvU32 cmd, void *params_address, const size_t params_size
|
||||
);
|
||||
|
||||
/*!
|
||||
* Like nvkms_ioctl_from_kapi, but return NV_FALSE instead of waiting if the
|
||||
* power management read lock cannot be acquired.
|
||||
*/
|
||||
NvBool nvkms_ioctl_from_kapi_try_pmlock
|
||||
(
|
||||
struct nvkms_per_open *popen,
|
||||
NvU32 cmd, void *params_address, const size_t params_size
|
||||
);
|
||||
|
||||
/*!
|
||||
* APIs for locking.
|
||||
*/
|
||||
|
||||
@@ -66,6 +66,8 @@ enum NvKmsClientType {
|
||||
NVKMS_CLIENT_KERNEL_SPACE,
|
||||
};
|
||||
|
||||
struct NvKmsPerOpenDev;
|
||||
|
||||
NvBool nvKmsIoctl(
|
||||
void *pOpenVoid,
|
||||
NvU32 cmd,
|
||||
@@ -101,7 +103,11 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
struct NvKmsKapiFunctionsTable *funcsTable
|
||||
);
|
||||
|
||||
void nvKmsKapiSuspendResume(NvBool suspend);
|
||||
|
||||
NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness);
|
||||
NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness);
|
||||
|
||||
NvBool nvKmsOpenDevHasSubOwnerPermissionOrBetter(const struct NvKmsPerOpenDev *pOpenDev);
|
||||
|
||||
#endif /* __NV_KMS_H__ */
|
||||
|
||||
@@ -23,6 +23,12 @@
|
||||
|
||||
#include "internal_crypt_lib.h"
|
||||
|
||||
#ifdef USE_LKCA
|
||||
#ifndef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT
|
||||
#include <crypto/internal/hash.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void *lkca_hash_new(const char* alg_name)
|
||||
{
|
||||
#ifndef USE_LKCA
|
||||
@@ -87,9 +93,24 @@ bool lkca_hmac_duplicate(struct shash_desc *dst, struct shash_desc const *src)
|
||||
|
||||
struct crypto_shash *src_tfm = src->tfm;
|
||||
struct crypto_shash *dst_tfm = dst->tfm;
|
||||
int ss = crypto_shash_statesize(dst_tfm);
|
||||
|
||||
#ifdef NV_CRYPTO_TFM_CTX_ALIGNED_PRESENT
|
||||
char *src_ipad = crypto_tfm_ctx_aligned(&src_tfm->base);
|
||||
char *dst_ipad = crypto_tfm_ctx_aligned(&dst_tfm->base);
|
||||
int ss = crypto_shash_statesize(dst_tfm);
|
||||
#else
|
||||
int ctx_size = crypto_shash_alg(dst_tfm)->base.cra_ctxsize;
|
||||
char *src_ipad = crypto_shash_ctx(src_tfm);
|
||||
char *dst_ipad = crypto_shash_ctx(dst_tfm);
|
||||
/*
|
||||
* Actual struct definition is hidden, so I assume data we need is at
|
||||
* the end. In 6.0 the struct has a pointer to crpyto_shash followed by:
|
||||
* 'u8 ipad[statesize];', then 'u8 opad[statesize];'
|
||||
*/
|
||||
src_ipad += ctx_size - 2 * ss;
|
||||
dst_ipad += ctx_size - 2 * ss;
|
||||
#endif
|
||||
|
||||
memcpy(dst_ipad, src_ipad, crypto_shash_blocksize(src->tfm));
|
||||
memcpy(dst_ipad + ss, src_ipad + ss, crypto_shash_blocksize(src->tfm));
|
||||
crypto_shash_clear_flags(dst->tfm, CRYPTO_TFM_NEED_KEY);
|
||||
|
||||
@@ -1385,57 +1385,3 @@ NvBool nv_get_hdcp_enabled(nv_state_t *nv)
|
||||
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
int nv_disable_simplefb_clocks(void)
|
||||
{
|
||||
int status = 0;
|
||||
static bool is_coldboot = true;
|
||||
|
||||
#if defined(CONFIG_FB) && defined(NV_NUM_REGISTERED_FB_PRESENT)
|
||||
if (num_registered_fb > 0)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_registered_fb; i++)
|
||||
{
|
||||
if (!registered_fb[i])
|
||||
continue;
|
||||
|
||||
#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
|
||||
struct clk *clock;
|
||||
struct device_node *np = NULL;
|
||||
unsigned int clk_count = 0;
|
||||
int j;
|
||||
|
||||
np = of_find_node_by_name(NULL, "framebuffer");
|
||||
if ((np != NULL) && of_device_is_available(np) && is_coldboot)
|
||||
{
|
||||
#if defined(NV_LINUX_OF_CLK_H_PRESENT) && defined(NV_OF_CLK_GET_PARENT_COUNT_PRESENT)
|
||||
clk_count = of_clk_get_parent_count(np);
|
||||
for (j = 0; j < clk_count; j++)
|
||||
{
|
||||
clock = of_clk_get(np, j);
|
||||
if (IS_ERR(clock))
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "clock %d not found %ld\n", j, PTR_ERR(clock));
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (__clk_is_enabled(clock))
|
||||
{
|
||||
clk_disable_unprepare(clock);
|
||||
}
|
||||
clk_put(clock);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
is_coldboot = false;
|
||||
}
|
||||
of_node_put(np);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
NvU64 NV_API_CALL nv_get_kern_phys_address(NvU64 address)
|
||||
{
|
||||
/* direct-mapped kernel address */
|
||||
if (virt_addr_valid(address))
|
||||
if (virt_addr_valid((void *)address))
|
||||
return __pa(address);
|
||||
|
||||
nv_printf(NV_DBG_ERRORS,
|
||||
|
||||
@@ -1255,15 +1255,6 @@ static int nv_start_device(nv_state_t *nv, nvidia_stack_t *sp)
|
||||
goto failed;
|
||||
}
|
||||
|
||||
rc = nv_disable_simplefb_clocks();
|
||||
if (rc)
|
||||
{
|
||||
NV_DEV_PRINTF(NV_DBG_ERRORS, nv,
|
||||
"nv_disable_simplefb_clocks failed, status %d\n",
|
||||
rc);
|
||||
goto failed;
|
||||
}
|
||||
|
||||
{
|
||||
const NvU8 *uuid = rm_get_gpu_uuid_raw(sp, nv);
|
||||
|
||||
|
||||
@@ -161,7 +161,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += pci_enable_atomic_ops_to_root
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += vga_tryget
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += cc_platform_has
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += seq_read_iter
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += unsafe_follow_pfn
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += follow_pfn
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_get
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_gem_object_put_unlocked
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += add_memory_driver_managed
|
||||
@@ -196,7 +196,6 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += get_task_ioprio
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += mdev_set_iommu_device
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += offline_and_remove_memory
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += of_clk_get_parent_count
|
||||
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_of_node_to_nid
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_sme_active
|
||||
@@ -227,6 +226,7 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_clear_in
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_alloc_mem_from_gscco
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tsec_comms_free_gscco_mem
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += crypto
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pte
|
||||
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops
|
||||
|
||||
@@ -1201,12 +1201,13 @@ void NV_API_CALL os_get_screen_info(
|
||||
NvU32 *pFbHeight,
|
||||
NvU32 *pFbDepth,
|
||||
NvU32 *pFbPitch,
|
||||
NvU64 *pFbSize,
|
||||
NvU64 consoleBar1Address,
|
||||
NvU64 consoleBar2Address
|
||||
)
|
||||
{
|
||||
*pPhysicalAddress = 0;
|
||||
*pFbWidth = *pFbHeight = *pFbDepth = *pFbPitch = 0;
|
||||
*pFbWidth = *pFbHeight = *pFbDepth = *pFbPitch = *pFbSize = 0;
|
||||
|
||||
#if defined(CONFIG_FB) && defined(NV_NUM_REGISTERED_FB_PRESENT)
|
||||
if (num_registered_fb > 0)
|
||||
@@ -1224,6 +1225,7 @@ void NV_API_CALL os_get_screen_info(
|
||||
*pFbHeight = registered_fb[i]->var.yres;
|
||||
*pFbDepth = registered_fb[i]->var.bits_per_pixel;
|
||||
*pFbPitch = registered_fb[i]->fix.line_length;
|
||||
*pFbSize = registered_fb[i]->fix.smem_len;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -30,10 +30,28 @@ static inline int nv_follow_pfn(struct vm_area_struct *vma,
|
||||
unsigned long address,
|
||||
unsigned long *pfn)
|
||||
{
|
||||
#if defined(NV_UNSAFE_FOLLOW_PFN_PRESENT)
|
||||
return unsafe_follow_pfn(vma, address, pfn);
|
||||
#else
|
||||
#if defined(NV_FOLLOW_PFN_PRESENT)
|
||||
return follow_pfn(vma, address, pfn);
|
||||
#else
|
||||
#if NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte
|
||||
int status = 0;
|
||||
spinlock_t *ptl;
|
||||
pte_t *ptep;
|
||||
|
||||
if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
|
||||
return status;
|
||||
|
||||
status = follow_pte(vma, address, &ptep, &ptl);
|
||||
if (status)
|
||||
return status;
|
||||
*pfn = pte_pfn(ptep_get(ptep));
|
||||
|
||||
// The lock is acquired inside follow_pte()
|
||||
pte_unmap_unlock(ptep, ptl);
|
||||
return 0;
|
||||
#else // NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte
|
||||
return -1;
|
||||
#endif // NV_IS_EXPORT_SYMBOL_PRESENT_follow_pte
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
rel-36_lws2_eng_2025-09-23
|
||||
jetson_36.4.3
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
|
||||
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
|
||||
|
||||
#define NV_VERSION_STRING "540.3.2"
|
||||
#define NV_VERSION_STRING "540.4.0"
|
||||
|
||||
#else
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -88,6 +88,8 @@ typedef struct NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS {
|
||||
NvU16 height; /* out */
|
||||
NvU16 depth; /* out */
|
||||
NvU16 pitch; /* out */
|
||||
NV_DECLARE_ALIGNED(NvU64 baseAddress, 8); /* out */
|
||||
NV_DECLARE_ALIGNED(NvU64 size, 8); /* out */
|
||||
} NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS;
|
||||
|
||||
/* _ctrl0080unix_h_ */
|
||||
|
||||
@@ -55,6 +55,11 @@ INLINE NvU32 F32viewAsNvU32(float32_t f)
|
||||
return f.v;
|
||||
}
|
||||
|
||||
INLINE NvU16 F16viewAsNvU16(float16_t f)
|
||||
{
|
||||
return f.v;
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert the value of a float32_t to an NvU16.
|
||||
*
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 - 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -37,6 +37,7 @@ typedef struct {
|
||||
NVDpyIdList dpyIdList;
|
||||
NVAttributesSetEvoRec attributes;
|
||||
struct NvKmsSetLutCommonParams lut;
|
||||
enum NvKmsOutputColorSpace outputColorSpace;
|
||||
NVDispStereoParamsEvoRec stereo;
|
||||
NVDscInfoEvoRec dscInfo;
|
||||
NVDispHeadInfoFrameStateEvoRec infoFrame;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -924,10 +924,13 @@ typedef struct _NVEvoSubDeviceRec {
|
||||
|
||||
} NVEvoSubDeviceRec;
|
||||
|
||||
enum NvKmsLUTState {
|
||||
NvKmsLUTStateUninitialized = 0,
|
||||
NvKmsLUTStateIdentity = 1,
|
||||
NvKmsLUTStatePQ = 2,
|
||||
enum NVKMS_GAMMA_LUT {
|
||||
NVKMS_GAMMA_LUT_IDENTITY = 0,
|
||||
NVKMS_GAMMA_LUT_SRGB = 1,
|
||||
NVKMS_GAMMA_LUT_PQ = 2,
|
||||
|
||||
// Must be last, used to track number of colorspaces.
|
||||
NVKMS_GAMMA_LUT_LAST = 3,
|
||||
};
|
||||
|
||||
/* Device-specific EVO state (subdevice- and channel-independent) */
|
||||
@@ -978,6 +981,13 @@ typedef struct _NVEvoDevRec {
|
||||
*/
|
||||
NvBool modesetOwnerChanged;
|
||||
|
||||
/*!
|
||||
* modesetSubOwner points to the pOpenDev of the client that called
|
||||
* NVKMS_IOCTL_ACQUIRE_PERMISSIONS with a file descriptor that grants
|
||||
* NV_KMS_PERMISSIONS_TYPE_SUB_OWNER.
|
||||
*/
|
||||
const struct NvKmsPerOpenDev *modesetSubOwner;
|
||||
|
||||
/*!
|
||||
* NVEvoDevRec::numSubDevices is the number of GPUs in the SLI
|
||||
* device. This is the number of NVEvoSubDevPtrs in
|
||||
@@ -1193,9 +1203,8 @@ typedef struct _NVEvoDevRec {
|
||||
nvkms_timer_handle_t *updateTimer;
|
||||
} disp[NVKMS_MAX_SUBDEVICES];
|
||||
} apiHead[NVKMS_MAX_HEADS_PER_DISP];
|
||||
NVLutSurfaceEvoPtr defaultLut;
|
||||
enum NvKmsLUTState defaultBaseLUTState[NVKMS_MAX_SUBDEVICES];
|
||||
enum NvKmsLUTState defaultOutputLUTState[NVKMS_MAX_SUBDEVICES];
|
||||
// Identity, sRGB, and PQ LUTs.
|
||||
NVLutSurfaceEvoPtr gammaLUTs[NVKMS_GAMMA_LUT_LAST];
|
||||
} lut;
|
||||
|
||||
/*! stores pre-syncpts */
|
||||
@@ -1749,6 +1758,8 @@ typedef struct _NVDispHeadStateEvoRec {
|
||||
NvBool baseLutEnabled : 1;
|
||||
} lut;
|
||||
|
||||
enum NvKmsOutputColorSpace outputColorSpace;
|
||||
|
||||
/*
|
||||
* The api head can be mapped onto the N harware heads, a frame presented
|
||||
* by the api head gets split horizontally into N tiles, 'tilePosition'
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -554,6 +554,23 @@ enum NvKmsInputColorSpace {
|
||||
|
||||
/* PQ, Rec.2020 unity */
|
||||
NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
|
||||
|
||||
/* sRGB colorspace with sRGB gamma transfer function */
|
||||
NVKMS_INPUT_COLORSPACE_SRGB = 3,
|
||||
|
||||
/* Rec709 colorspace with Rec709 gamma transfer function */
|
||||
NVKMS_INPUT_COLORSPACE_REC709 = 4,
|
||||
|
||||
/* Rec709 colorspace with linear (identity) gamma */
|
||||
NVKMS_INPUT_COLORSPACE_REC709_LINEAR = 5
|
||||
};
|
||||
|
||||
enum NvKmsOutputColorSpace {
|
||||
/* Unknown colorspace; no re-gamma will be applied */
|
||||
NVKMS_OUTPUT_COLORSPACE_NONE = 0,
|
||||
|
||||
/* sRGB gamma transfer function will be applied */
|
||||
NVKMS_OUTPUT_COLORSPACE_SRGB = 1
|
||||
};
|
||||
|
||||
enum NvKmsOutputTf {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -267,6 +267,7 @@ enum NvKmsIoctlCommand {
|
||||
NVKMS_IOCTL_ENABLE_VBLANK_SYNC_OBJECT,
|
||||
NVKMS_IOCTL_DISABLE_VBLANK_SYNC_OBJECT,
|
||||
NVKMS_IOCTL_NOTIFY_VBLANK,
|
||||
NVKMS_IOCTL_QUERY_VT_FB_DATA,
|
||||
};
|
||||
|
||||
|
||||
@@ -916,7 +917,12 @@ struct NvKmsFlipCommonParams {
|
||||
NvBool specified;
|
||||
} colorRange;
|
||||
|
||||
/* This field has no effect right now. */
|
||||
/*
|
||||
* Specifies the input colorspace and gamma encoding.
|
||||
* If this is specified as any non-NONE colorspace, the driver will
|
||||
* load a predefined ILUT for that colorspace, and that will take
|
||||
* precedence over any custom LUTs the client supplies.
|
||||
*/
|
||||
struct {
|
||||
enum NvKmsInputColorSpace val;
|
||||
NvBool specified;
|
||||
@@ -1465,6 +1471,19 @@ struct NvKmsQueryDpyDynamicDataParams {
|
||||
struct NvKmsQueryDpyDynamicDataReply reply; /*! out */
|
||||
};
|
||||
|
||||
struct NvKmsQueryVtFbDataRequest {
|
||||
NvKmsDeviceHandle deviceHandle;
|
||||
};
|
||||
|
||||
struct NvKmsQueryVtFbDataReply {
|
||||
NvU64 baseAddress;
|
||||
NvU64 size;
|
||||
};
|
||||
|
||||
struct NvKmsQueryVtFbDataParams {
|
||||
struct NvKmsQueryVtFbDataRequest request; /*! in */
|
||||
struct NvKmsQueryVtFbDataReply reply; /*! out */
|
||||
};
|
||||
|
||||
/*!
|
||||
* NVKMS_IOCTL_VALIDATE_MODE_INDEX: Validate a particular mode from a
|
||||
@@ -1791,10 +1810,27 @@ struct NvKmsSetModeOneHeadRequest {
|
||||
struct NvKmsSize viewPortSizeIn;
|
||||
|
||||
/*!
|
||||
* Describe the LUT to be used with the modeset.
|
||||
* Clients can supply custom ILUT and OLUT ramps through this variable. If
|
||||
* a client wishes to use a custom ILUT/OLUT, they must specify
|
||||
* NVKMS_INPUT_COLORSPACE_NONE (see NvKmsInputColorSpace in
|
||||
* FlipCommonParams) and NVKMS_OUTPUT_COLORSPACE_NONE (see
|
||||
* NvKmsOutputColorSpace below), otherwise the predefined LUTs for the
|
||||
* specified input/output colorspaces will be used instead.
|
||||
*/
|
||||
struct NvKmsSetLutCommonParams lut;
|
||||
|
||||
/*!
|
||||
* If specified, this will determine the gamma encoding of the output.
|
||||
* Note: this will take precendence over a custom output lut ramp if that
|
||||
* is also supplied via the `lut` member variable above.
|
||||
* Note: if neither this nor a custom OLUT is specified, the driver will
|
||||
* default to an Identity OLUT (i.e. no regamma).
|
||||
*/
|
||||
struct {
|
||||
NvBool specified;
|
||||
enum NvKmsOutputColorSpace val;
|
||||
} outputColorSpace;
|
||||
|
||||
/*!
|
||||
* Describe the surfaces to present on this head.
|
||||
*/
|
||||
@@ -3189,6 +3225,11 @@ struct NvKmsSetLayerPositionParams {
|
||||
*
|
||||
* Releasing modeset ownership enables console hotplug handling. See the
|
||||
* explanation in the comment for enableConsoleHotplugHandling above.
|
||||
*
|
||||
* If modeset ownership is held by nvidia-drm, then NVKMS_IOCTL_GRAB_OWNERSHIP
|
||||
* will fail. Clients should open the corresponding DRM device node, acquire
|
||||
* 'master' on it, and then use DRM_NVIDIA_GRANT_PERMISSIONS with permission
|
||||
* type NV_DRM_PERMISSIONS_TYPE_SUB_OWNER to acquire sub-owner permission.
|
||||
*/
|
||||
|
||||
struct NvKmsGrabOwnershipRequest {
|
||||
@@ -3227,8 +3268,9 @@ struct NvKmsReleaseOwnershipParams {
|
||||
* successfully called NVKMS_IOCTL_GRAB_OWNERSHIP) is allowed to flip
|
||||
* or set modes.
|
||||
*
|
||||
* However, the modeset owner can grant various permissions to other
|
||||
* clients through the following steps:
|
||||
* However, the modeset owner or another NVKMS client with
|
||||
* NV_KMS_PERMISSIONS_TYPE_SUB_OWNER permission can grant various
|
||||
* permissions to other clients through the following steps:
|
||||
*
|
||||
* - The modeset owner should open /dev/nvidia-modeset, and call
|
||||
* NVKMS_IOCTL_GRANT_PERMISSIONS to define a set of permissions
|
||||
@@ -3277,6 +3319,7 @@ struct NvKmsReleaseOwnershipParams {
|
||||
enum NvKmsPermissionsType {
|
||||
NV_KMS_PERMISSIONS_TYPE_FLIPPING = 1,
|
||||
NV_KMS_PERMISSIONS_TYPE_MODESET = 2,
|
||||
NV_KMS_PERMISSIONS_TYPE_SUB_OWNER = 3,
|
||||
};
|
||||
|
||||
struct NvKmsFlipPermissions {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -411,6 +411,14 @@ struct NvKmsKapiDynamicDisplayParams {
|
||||
NvBool forceDisconnected;
|
||||
};
|
||||
|
||||
struct NvKmsKapiVtFbParams {
|
||||
/* [OUT] VT framebuffer memory base address */
|
||||
NvU64 baseAddress;
|
||||
|
||||
/* [OUT] VT framebuffer memory size */
|
||||
NvU64 size;
|
||||
};
|
||||
|
||||
struct NvKmsKapiCreateSurfaceParams {
|
||||
|
||||
/* [IN] Parameter of each plane */
|
||||
@@ -455,6 +463,8 @@ typedef enum NvKmsKapiRegisterWaiterResultRec {
|
||||
NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED,
|
||||
} NvKmsKapiRegisterWaiterResult;
|
||||
|
||||
typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend);
|
||||
|
||||
struct NvKmsKapiFunctionsTable {
|
||||
|
||||
/*!
|
||||
@@ -540,8 +550,8 @@ struct NvKmsKapiFunctionsTable {
|
||||
);
|
||||
|
||||
/*!
|
||||
* Revoke permissions previously granted. Only one (dispIndex, head,
|
||||
* display) is currently supported.
|
||||
* Revoke modeset permissions previously granted. Only one (dispIndex,
|
||||
* head, display) is currently supported.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
@@ -558,6 +568,34 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvKmsKapiDisplay display
|
||||
);
|
||||
|
||||
/*!
|
||||
* Grant modeset sub-owner permissions to fd. This is used by clients to
|
||||
* convert drm 'master' permissions into nvkms sub-owner permission.
|
||||
*
|
||||
* \param [in] fd fd from opening /dev/nvidia-modeset.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*grantSubOwnership)
|
||||
(
|
||||
NvS32 fd,
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
|
||||
/*!
|
||||
* Revoke sub-owner permissions previously granted.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*revokeSubOwnership)
|
||||
(
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
|
||||
/*!
|
||||
* Registers for notification, via
|
||||
* NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified
|
||||
@@ -679,6 +717,20 @@ struct NvKmsKapiFunctionsTable {
|
||||
struct NvKmsKapiDynamicDisplayParams *params
|
||||
);
|
||||
|
||||
/*!
|
||||
* Get VT framebuffer information.
|
||||
*
|
||||
* \param [out] params Parameters containing the base address and size
|
||||
* of VT framebuffer memory
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*getVtFbInfo)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
struct NvKmsKapiVtFbParams *params
|
||||
);
|
||||
|
||||
/*!
|
||||
* Allocate some unformatted video memory of the specified size.
|
||||
*
|
||||
@@ -1336,6 +1388,15 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvU64 index,
|
||||
NvU64 new_value
|
||||
);
|
||||
|
||||
/*!
|
||||
* Set the callback function for suspending and resuming the display system.
|
||||
*/
|
||||
void
|
||||
(*setSuspendResumeCallback)
|
||||
(
|
||||
NvKmsKapiSuspendResumeCallbackFunc *function
|
||||
);
|
||||
};
|
||||
|
||||
/** @} */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -915,6 +915,51 @@ static NvBool RevokePermissions
|
||||
sizeof(paramsRevoke));
|
||||
}
|
||||
|
||||
static NvBool GrantSubOwnership
|
||||
(
|
||||
NvS32 fd,
|
||||
struct NvKmsKapiDevice *device
|
||||
)
|
||||
{
|
||||
struct NvKmsGrantPermissionsParams paramsGrant = { };
|
||||
struct NvKmsPermissions *perm = ¶msGrant.request.permissions;
|
||||
|
||||
if (device->hKmsDevice == 0x0) {
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
perm->type = NV_KMS_PERMISSIONS_TYPE_SUB_OWNER;
|
||||
|
||||
paramsGrant.request.fd = fd;
|
||||
paramsGrant.request.deviceHandle = device->hKmsDevice;
|
||||
|
||||
return nvkms_ioctl_from_kapi(device->pKmsOpen,
|
||||
NVKMS_IOCTL_GRANT_PERMISSIONS, ¶msGrant,
|
||||
sizeof(paramsGrant));
|
||||
}
|
||||
|
||||
static NvBool RevokeSubOwnership
|
||||
(
|
||||
struct NvKmsKapiDevice *device
|
||||
)
|
||||
{
|
||||
struct NvKmsRevokePermissionsParams paramsRevoke = { };
|
||||
|
||||
if (device->hKmsDevice == 0x0) {
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
paramsRevoke.request.permissionsTypeBitmask =
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING) |
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET) |
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER);
|
||||
paramsRevoke.request.deviceHandle = device->hKmsDevice;
|
||||
|
||||
return nvkms_ioctl_from_kapi(device->pKmsOpen,
|
||||
NVKMS_IOCTL_REVOKE_PERMISSIONS, ¶msRevoke,
|
||||
sizeof(paramsRevoke));
|
||||
}
|
||||
|
||||
static NvBool DeclareEventInterest
|
||||
(
|
||||
const struct NvKmsKapiDevice *device,
|
||||
@@ -1289,6 +1334,40 @@ done:
|
||||
return status;
|
||||
}
|
||||
|
||||
static NvBool GetVtFbInfo
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
struct NvKmsKapiVtFbParams *pParam
|
||||
)
|
||||
{
|
||||
struct NvKmsQueryVtFbDataParams params = { };
|
||||
NvBool status = NV_FALSE;
|
||||
|
||||
if (device == NULL || pParam == NULL) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
params.request.deviceHandle = device->hKmsDevice;
|
||||
status = nvkms_ioctl_from_kapi(device->pKmsOpen,
|
||||
NVKMS_IOCTL_QUERY_VT_FB_DATA,
|
||||
¶ms, sizeof(params));
|
||||
|
||||
if (!status)
|
||||
{
|
||||
nvKmsKapiLogDeviceDebug(
|
||||
device,
|
||||
"Failed to query VT framebuffer information");
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
pParam->baseAddress = params.reply.baseAddress;
|
||||
pParam->size = params.reply.size;
|
||||
|
||||
done:
|
||||
return status;
|
||||
}
|
||||
|
||||
static void FreeMemory
|
||||
(
|
||||
struct NvKmsKapiDevice *device, struct NvKmsKapiMemory *memory
|
||||
@@ -2883,9 +2962,9 @@ static NvBool KmsSetMode(
|
||||
goto done;
|
||||
}
|
||||
|
||||
status = nvkms_ioctl_from_kapi(device->pKmsOpen,
|
||||
NVKMS_IOCTL_SET_MODE,
|
||||
params, sizeof(*params));
|
||||
status = nvkms_ioctl_from_kapi_try_pmlock(device->pKmsOpen,
|
||||
NVKMS_IOCTL_SET_MODE,
|
||||
params, sizeof(*params));
|
||||
|
||||
if (!status) {
|
||||
nvKmsKapiLogDeviceDebug(
|
||||
@@ -3042,9 +3121,9 @@ static NvBool KmsFlip(
|
||||
goto done;
|
||||
}
|
||||
|
||||
status = nvkms_ioctl_from_kapi(device->pKmsOpen,
|
||||
NVKMS_IOCTL_FLIP,
|
||||
params, sizeof(*params));
|
||||
status = nvkms_ioctl_from_kapi_try_pmlock(device->pKmsOpen,
|
||||
NVKMS_IOCTL_FLIP,
|
||||
params, sizeof(*params));
|
||||
|
||||
if (!status) {
|
||||
nvKmsKapiLogDeviceDebug(
|
||||
@@ -3271,6 +3350,30 @@ static NvBool GetCRC32
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
static NvKmsKapiSuspendResumeCallbackFunc *pSuspendResumeFunc;
|
||||
|
||||
void nvKmsKapiSuspendResume
|
||||
(
|
||||
NvBool suspend
|
||||
)
|
||||
{
|
||||
if (pSuspendResumeFunc) {
|
||||
pSuspendResumeFunc(suspend);
|
||||
}
|
||||
}
|
||||
|
||||
static void nvKmsKapiSetSuspendResumeCallback
|
||||
(
|
||||
NvKmsKapiSuspendResumeCallbackFunc *function
|
||||
)
|
||||
{
|
||||
if (pSuspendResumeFunc && function) {
|
||||
nvKmsKapiLogDebug("Kapi suspend/resume callback function already registered");
|
||||
}
|
||||
|
||||
pSuspendResumeFunc = function;
|
||||
}
|
||||
|
||||
NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
(
|
||||
struct NvKmsKapiFunctionsTable *funcsTable
|
||||
@@ -3298,6 +3401,8 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
|
||||
funcsTable->grantPermissions = GrantPermissions;
|
||||
funcsTable->revokePermissions = RevokePermissions;
|
||||
funcsTable->grantSubOwnership = GrantSubOwnership;
|
||||
funcsTable->revokeSubOwnership = RevokeSubOwnership;
|
||||
|
||||
funcsTable->declareEventInterest = DeclareEventInterest;
|
||||
|
||||
@@ -3308,6 +3413,8 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
funcsTable->getStaticDisplayInfo = GetStaticDisplayInfo;
|
||||
funcsTable->getDynamicDisplayInfo = GetDynamicDisplayInfo;
|
||||
|
||||
funcsTable->getVtFbInfo = GetVtFbInfo;
|
||||
|
||||
funcsTable->allocateVideoMemory = AllocateVideoMemory;
|
||||
funcsTable->allocateSystemMemory = AllocateSystemMemory;
|
||||
funcsTable->importMemory = ImportMemory;
|
||||
@@ -3347,6 +3454,7 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
nvKmsKapiUnregisterSemaphoreSurfaceCallback;
|
||||
funcsTable->setSemaphoreSurfaceValue =
|
||||
nvKmsKapiSetSemaphoreSurfaceValue;
|
||||
funcsTable->setSuspendResumeCallback = nvKmsKapiSetSuspendResumeCallback;
|
||||
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
@@ -329,6 +329,16 @@ NvBool nvkms_ioctl_from_kapi
|
||||
NvU32 cmd, void *params_address, const size_t params_size
|
||||
);
|
||||
|
||||
/*!
|
||||
* Like nvkms_ioctl_from_kapi, but return NV_FALSE instead of waiting if the
|
||||
* power management read lock cannot be acquired.
|
||||
*/
|
||||
NvBool nvkms_ioctl_from_kapi_try_pmlock
|
||||
(
|
||||
struct nvkms_per_open *popen,
|
||||
NvU32 cmd, void *params_address, const size_t params_size
|
||||
);
|
||||
|
||||
/*!
|
||||
* APIs for locking.
|
||||
*/
|
||||
|
||||
@@ -66,6 +66,8 @@ enum NvKmsClientType {
|
||||
NVKMS_CLIENT_KERNEL_SPACE,
|
||||
};
|
||||
|
||||
struct NvKmsPerOpenDev;
|
||||
|
||||
NvBool nvKmsIoctl(
|
||||
void *pOpenVoid,
|
||||
NvU32 cmd,
|
||||
@@ -101,7 +103,11 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
struct NvKmsKapiFunctionsTable *funcsTable
|
||||
);
|
||||
|
||||
void nvKmsKapiSuspendResume(NvBool suspend);
|
||||
|
||||
NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness);
|
||||
NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness);
|
||||
|
||||
NvBool nvKmsOpenDevHasSubOwnerPermissionOrBetter(const struct NvKmsPerOpenDev *pOpenDev);
|
||||
|
||||
#endif /* __NV_KMS_H__ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -39,6 +39,7 @@
|
||||
#include "nvkms-dpy.h"
|
||||
#include "nvkms-vrr.h"
|
||||
#include "nvkms-ctxdma.h"
|
||||
#include "nvkms-lut.h"
|
||||
|
||||
#include <nvmisc.h>
|
||||
|
||||
@@ -73,6 +74,283 @@
|
||||
/** Number of CRCs supported by hardware on NVC37D hardware SF/SOR, Comp, RG Ovf and Count */
|
||||
#define NV_EVO3_NUM_CRC_FLAGS 4
|
||||
|
||||
#define SRGB_EOTF_LUT_NUM_ENTRIES 935
|
||||
#define SRGB_OETF_LUT_NUM_ENTRIES 178
|
||||
#define PQ_EOTF_LUT_NUM_ENTRIES 508
|
||||
#define PQ_OETF_LUT_NUM_ENTRIES 337
|
||||
|
||||
// These values are 16bit floating point.
|
||||
static const NvU16 sRGBEOTFLUTEntries[SRGB_EOTF_LUT_NUM_ENTRIES] = {
|
||||
0x0000, 0x018c, 0x0319, 0x04a5, 0x0631, 0x07be, 0x08a5, 0x096b, 0x0a31,
|
||||
0x0af7, 0x0bbe, 0x0c42, 0x0ca5, 0x0d08, 0x0d6b, 0x0dce, 0x0e31, 0x0e94,
|
||||
0x0ef7, 0x0f5a, 0x0fbe, 0x1010, 0x1042, 0x1073, 0x10a5, 0x10d6, 0x1108,
|
||||
0x113a, 0x116b, 0x119d, 0x11ce, 0x1200, 0x1231, 0x1263, 0x1294, 0x12c6,
|
||||
0x12f7, 0x1329, 0x135a, 0x138c, 0x13be, 0x13ef, 0x1410, 0x1429, 0x1442,
|
||||
0x145b, 0x1473, 0x148c, 0x14a5, 0x14be, 0x14d6, 0x14ef, 0x1508, 0x1521,
|
||||
0x153a, 0x1552, 0x156b, 0x1584, 0x159d, 0x15b5, 0x15ce, 0x15e7, 0x1600,
|
||||
0x1618, 0x1631, 0x1694, 0x16f7, 0x175a, 0x17be, 0x1810, 0x1842, 0x1873,
|
||||
0x18a5, 0x18d6, 0x1908, 0x193a, 0x196b, 0x199d, 0x19ce, 0x1a00, 0x1a31,
|
||||
0x1a94, 0x1af7, 0x1b5a, 0x1bbe, 0x1c11, 0x1c44, 0x1c79, 0x1cb0, 0x1cb7,
|
||||
0x1cbd, 0x1cc4, 0x1ccb, 0x1cd2, 0x1cd9, 0x1ce0, 0x1ce8, 0x1cef, 0x1cf6,
|
||||
0x1cfd, 0x1d04, 0x1d0b, 0x1d12, 0x1d1a, 0x1d21, 0x1d28, 0x1d30, 0x1d37,
|
||||
0x1d3e, 0x1d46, 0x1d4d, 0x1d54, 0x1d5c, 0x1d63, 0x1d6b, 0x1d72, 0x1d7a,
|
||||
0x1d82, 0x1d89, 0x1d91, 0x1d98, 0x1da0, 0x1da8, 0x1daf, 0x1db7, 0x1dbf,
|
||||
0x1dc7, 0x1dcf, 0x1dd6, 0x1dde, 0x1de6, 0x1dee, 0x1df6, 0x1dfe, 0x1e06,
|
||||
0x1e0e, 0x1e16, 0x1e1e, 0x1e26, 0x1e2e, 0x1e36, 0x1e3e, 0x1e47, 0x1e4f,
|
||||
0x1e57, 0x1e5f, 0x1e67, 0x1e70, 0x1e78, 0x1e80, 0x1e89, 0x1e91, 0x1e9a,
|
||||
0x1ede, 0x1f23, 0x1f6b, 0x1fb4, 0x1ffe, 0x2025, 0x204c, 0x2074, 0x209c,
|
||||
0x20c6, 0x20f0, 0x211b, 0x2147, 0x2174, 0x21a1, 0x21d0, 0x21ff, 0x222f,
|
||||
0x2260, 0x2292, 0x22c5, 0x22f9, 0x232d, 0x2363, 0x2399, 0x23d1, 0x2404,
|
||||
0x2421, 0x243e, 0x245b, 0x2479, 0x2498, 0x249b, 0x249f, 0x24a3, 0x24a7,
|
||||
0x24ab, 0x24af, 0x24b3, 0x24b7, 0x24ba, 0x24be, 0x24c2, 0x24c6, 0x24ca,
|
||||
0x24ce, 0x24d2, 0x24d6, 0x24da, 0x24de, 0x24e2, 0x24e6, 0x24ea, 0x24ee,
|
||||
0x24f2, 0x24f6, 0x24fa, 0x24fe, 0x2502, 0x2506, 0x250a, 0x250e, 0x2512,
|
||||
0x2516, 0x251a, 0x251e, 0x2522, 0x2526, 0x252a, 0x252e, 0x2532, 0x2537,
|
||||
0x253b, 0x253f, 0x2543, 0x2547, 0x254b, 0x254f, 0x2554, 0x2558, 0x255c,
|
||||
0x2560, 0x2564, 0x2569, 0x256d, 0x2571, 0x2575, 0x2579, 0x257e, 0x2582,
|
||||
0x2586, 0x258b, 0x258f, 0x2593, 0x2597, 0x259c, 0x25a0, 0x25a4, 0x25a9,
|
||||
0x25ad, 0x25b1, 0x25b6, 0x25ba, 0x25be, 0x25c3, 0x25c7, 0x25cb, 0x25d0,
|
||||
0x25d4, 0x25d9, 0x25dd, 0x25e1, 0x25e6, 0x25ea, 0x25ef, 0x25f3, 0x25f8,
|
||||
0x25fc, 0x2601, 0x2605, 0x260a, 0x260e, 0x2613, 0x2617, 0x261c, 0x2620,
|
||||
0x2625, 0x2629, 0x262e, 0x2632, 0x2637, 0x263b, 0x2640, 0x2645, 0x2649,
|
||||
0x264e, 0x2652, 0x2657, 0x265c, 0x2660, 0x2665, 0x2669, 0x266e, 0x2673,
|
||||
0x2677, 0x267c, 0x2681, 0x2686, 0x268a, 0x268f, 0x2694, 0x2698, 0x269d,
|
||||
0x26a2, 0x26a7, 0x26ab, 0x26b0, 0x26b5, 0x26ba, 0x26be, 0x26e5, 0x270c,
|
||||
0x2734, 0x275c, 0x2784, 0x27ad, 0x27d7, 0x2800, 0x282b, 0x2857, 0x2884,
|
||||
0x28b2, 0x28b5, 0x28b8, 0x28bb, 0x28be, 0x28c1, 0x28c4, 0x28c6, 0x28c9,
|
||||
0x28cc, 0x28cf, 0x28d2, 0x28d5, 0x28d8, 0x28db, 0x28de, 0x28e1, 0x28e4,
|
||||
0x28e7, 0x28ea, 0x28ed, 0x28f0, 0x28f3, 0x28f6, 0x28f9, 0x28fc, 0x28ff,
|
||||
0x2902, 0x2905, 0x2908, 0x290b, 0x290e, 0x2911, 0x2914, 0x2917, 0x291a,
|
||||
0x291d, 0x2920, 0x2923, 0x2926, 0x2929, 0x292d, 0x2930, 0x2933, 0x2936,
|
||||
0x2939, 0x293c, 0x293f, 0x2942, 0x2945, 0x2948, 0x294c, 0x294f, 0x2952,
|
||||
0x2955, 0x2958, 0x295b, 0x295e, 0x2961, 0x2965, 0x2968, 0x296b, 0x296e,
|
||||
0x2971, 0x2974, 0x2978, 0x297b, 0x297e, 0x2981, 0x2984, 0x2987, 0x298b,
|
||||
0x298e, 0x2991, 0x2994, 0x2997, 0x299b, 0x299e, 0x29a1, 0x29a4, 0x29a8,
|
||||
0x29ab, 0x29ae, 0x29b1, 0x29b5, 0x29b8, 0x29bb, 0x29be, 0x29c2, 0x29c5,
|
||||
0x29c8, 0x29cb, 0x29cf, 0x29d2, 0x29d5, 0x29d9, 0x29dc, 0x29df, 0x29e3,
|
||||
0x29e6, 0x29e9, 0x29ed, 0x29f0, 0x29f3, 0x29f7, 0x29fa, 0x29fd, 0x2a01,
|
||||
0x2a04, 0x2a07, 0x2a0b, 0x2a0e, 0x2a11, 0x2a15, 0x2a18, 0x2a1c, 0x2a1f,
|
||||
0x2a22, 0x2a26, 0x2a29, 0x2a2c, 0x2a30, 0x2a33, 0x2a37, 0x2a3a, 0x2a3e,
|
||||
0x2a41, 0x2a44, 0x2a48, 0x2a80, 0x2ab8, 0x2af2, 0x2b2d, 0x2ba6, 0x2c12,
|
||||
0x2c53, 0x2c97, 0x2c9b, 0x2c9f, 0x2ca4, 0x2ca8, 0x2cac, 0x2cb1, 0x2cb5,
|
||||
0x2cb9, 0x2cbe, 0x2cc2, 0x2cc7, 0x2ccb, 0x2ccf, 0x2cd4, 0x2cd8, 0x2cdd,
|
||||
0x2ce1, 0x2ce6, 0x2cea, 0x2cef, 0x2cf3, 0x2cf8, 0x2cfc, 0x2d01, 0x2d05,
|
||||
0x2d0a, 0x2d0e, 0x2d13, 0x2d17, 0x2d1c, 0x2d20, 0x2d25, 0x2d2e, 0x2d37,
|
||||
0x2d41, 0x2d4a, 0x2d53, 0x2d5d, 0x2d66, 0x2d70, 0x2d79, 0x2d83, 0x2d8c,
|
||||
0x2d96, 0x2d9f, 0x2da9, 0x2db3, 0x2dbd, 0x2de4, 0x2e0c, 0x2e35, 0x2e5e,
|
||||
0x2e88, 0x2eb2, 0x2ede, 0x2f09, 0x2f63, 0x2fbf, 0x300f, 0x303f, 0x3071,
|
||||
0x30a4, 0x30d9, 0x310e, 0x3110, 0x3112, 0x3114, 0x3115, 0x3117, 0x3119,
|
||||
0x311a, 0x311c, 0x311e, 0x3120, 0x3121, 0x3123, 0x3125, 0x3126, 0x3128,
|
||||
0x312a, 0x312c, 0x312d, 0x312f, 0x3131, 0x3132, 0x3134, 0x3136, 0x3138,
|
||||
0x3139, 0x313b, 0x313d, 0x313f, 0x3140, 0x3142, 0x3144, 0x3146, 0x3147,
|
||||
0x3149, 0x314b, 0x314d, 0x314e, 0x3150, 0x3152, 0x3154, 0x3155, 0x3157,
|
||||
0x3159, 0x315b, 0x315c, 0x315e, 0x3160, 0x3162, 0x3163, 0x3165, 0x3167,
|
||||
0x3169, 0x316a, 0x316c, 0x316e, 0x3170, 0x3172, 0x3173, 0x3175, 0x3177,
|
||||
0x3179, 0x317a, 0x317c, 0x317e, 0x3180, 0x3182, 0x3183, 0x3185, 0x3187,
|
||||
0x3189, 0x318b, 0x318c, 0x318e, 0x3190, 0x3192, 0x3194, 0x3195, 0x3197,
|
||||
0x3199, 0x319b, 0x319d, 0x319e, 0x31a0, 0x31a2, 0x31a4, 0x31a6, 0x31a7,
|
||||
0x31a9, 0x31ab, 0x31ad, 0x31af, 0x31b1, 0x31b2, 0x31b4, 0x31b6, 0x31b8,
|
||||
0x31ba, 0x31bc, 0x31bd, 0x31bf, 0x31c1, 0x31c3, 0x31c5, 0x31c7, 0x31c8,
|
||||
0x31ca, 0x31cc, 0x31ce, 0x31d0, 0x31d2, 0x31d3, 0x31d5, 0x31d7, 0x31d9,
|
||||
0x31db, 0x31dd, 0x31df, 0x31e0, 0x31e2, 0x31e4, 0x31e6, 0x31e8, 0x31ea,
|
||||
0x31ec, 0x31ed, 0x31ef, 0x31f1, 0x31f3, 0x31f5, 0x31f7, 0x31f9, 0x31fb,
|
||||
0x31fc, 0x31fe, 0x3200, 0x3202, 0x3204, 0x3206, 0x3208, 0x320a, 0x320c,
|
||||
0x320d, 0x320f, 0x3211, 0x3213, 0x3215, 0x3217, 0x3219, 0x321b, 0x321d,
|
||||
0x321e, 0x3220, 0x3222, 0x3224, 0x3226, 0x3228, 0x322a, 0x322c, 0x322e,
|
||||
0x3230, 0x3232, 0x3233, 0x3235, 0x3237, 0x3239, 0x323b, 0x323d, 0x323f,
|
||||
0x3241, 0x3243, 0x3245, 0x3247, 0x3249, 0x324b, 0x324d, 0x324e, 0x3250,
|
||||
0x3252, 0x3254, 0x3256, 0x3258, 0x325a, 0x325c, 0x325e, 0x3260, 0x3262,
|
||||
0x3264, 0x3266, 0x3268, 0x326a, 0x326c, 0x326e, 0x328d, 0x32ad, 0x32cd,
|
||||
0x32ee, 0x3330, 0x3373, 0x33b8, 0x33ff, 0x3448, 0x3494, 0x34e2, 0x34f6,
|
||||
0x350a, 0x351f, 0x3533, 0x355d, 0x3588, 0x358d, 0x3593, 0x3598, 0x359e,
|
||||
0x35a3, 0x35a8, 0x35ae, 0x35b3, 0x35b9, 0x35be, 0x35c4, 0x35c9, 0x35cf,
|
||||
0x35d4, 0x35da, 0x35df, 0x363a, 0x3669, 0x3698, 0x36f9, 0x375d, 0x37c4,
|
||||
0x3817, 0x384e, 0x3886, 0x38c1, 0x38fc, 0x38fd, 0x38fe, 0x38ff, 0x3900,
|
||||
0x3901, 0x3902, 0x3903, 0x3904, 0x3905, 0x3906, 0x3907, 0x3908, 0x3909,
|
||||
0x390a, 0x390b, 0x390c, 0x390d, 0x390d, 0x390e, 0x390f, 0x3910, 0x3911,
|
||||
0x3912, 0x3913, 0x3914, 0x3915, 0x3916, 0x3917, 0x3918, 0x3919, 0x391a,
|
||||
0x391b, 0x391c, 0x391d, 0x391e, 0x391f, 0x3920, 0x3921, 0x3922, 0x3923,
|
||||
0x3924, 0x3925, 0x3925, 0x3926, 0x3927, 0x3928, 0x3929, 0x392a, 0x392b,
|
||||
0x392c, 0x392d, 0x392e, 0x392f, 0x3930, 0x3931, 0x3932, 0x3933, 0x3934,
|
||||
0x3935, 0x3936, 0x3937, 0x3938, 0x3939, 0x393a, 0x393c, 0x393e, 0x3940,
|
||||
0x3942, 0x3944, 0x3946, 0x3948, 0x3949, 0x394b, 0x394d, 0x394f, 0x3951,
|
||||
0x3953, 0x3955, 0x3957, 0x3959, 0x395b, 0x395d, 0x395f, 0x3961, 0x3963,
|
||||
0x3965, 0x3967, 0x3969, 0x396b, 0x396d, 0x396f, 0x3971, 0x3973, 0x3975,
|
||||
0x3977, 0x3979, 0x397b, 0x397d, 0x397f, 0x3981, 0x3983, 0x3985, 0x3987,
|
||||
0x3989, 0x398b, 0x398d, 0x398f, 0x3991, 0x3993, 0x3995, 0x3997, 0x3999,
|
||||
0x399b, 0x399d, 0x399f, 0x39a1, 0x39a3, 0x39a5, 0x39a7, 0x39aa, 0x39ac,
|
||||
0x39ae, 0x39b0, 0x39b2, 0x39b4, 0x39b6, 0x39b8, 0x39ba, 0x39fc, 0x3a01,
|
||||
0x3a05, 0x3a09, 0x3a0d, 0x3a12, 0x3a16, 0x3a1a, 0x3a1e, 0x3a23, 0x3a27,
|
||||
0x3a2b, 0x3a30, 0x3a34, 0x3a38, 0x3a3c, 0x3a41, 0x3a87, 0x3a8b, 0x3a90,
|
||||
0x3a94, 0x3a99, 0x3a9d, 0x3aa2, 0x3aa6, 0x3aab, 0x3aaf, 0x3ab4, 0x3ab8,
|
||||
0x3abd, 0x3ac1, 0x3ac6, 0x3aca, 0x3acf, 0x3af3, 0x3b18, 0x3b64, 0x3bb1,
|
||||
0x3c00, 0x3c28, 0x3c52, 0x3c7c, 0x3ca7, 0x3cd3, 0x3d00, 0x3d00
|
||||
};
|
||||
|
||||
static const NvU16 sRGBEOTFLUTVSSHeader[16] = {
|
||||
0xbce6, 0xf66d, 0x2b64, 0x0000,
|
||||
0xa529, 0xb124, 0x04ad, 0x0000,
|
||||
0x4280, 0x0004, 0xc000, 0x0000,
|
||||
0x082d, 0x0006, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
// These values are 16bit fixed-point.
|
||||
static const NvU16 sRGBOETFLUTEntries[SRGB_OETF_LUT_NUM_ENTRIES] = {
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0004,
|
||||
0x0008, 0x000c, 0x0018, 0x0034, 0x0068, 0x00d0, 0x019c, 0x033c,
|
||||
0x0674, 0x0744, 0x0814, 0x08e0, 0x09b0, 0x0a80, 0x0b44, 0x0c00,
|
||||
0x0cb8, 0x0e10, 0x0f54, 0x1084, 0x11a4, 0x12b8, 0x13c0, 0x14bc,
|
||||
0x15b0, 0x177c, 0x192c, 0x1ac4, 0x1c44, 0x1db4, 0x1f14, 0x2064,
|
||||
0x21a8, 0x22e4, 0x2410, 0x2534, 0x2650, 0x2764, 0x2870, 0x2974,
|
||||
0x2a74, 0x2b6c, 0x2c5c, 0x2d4c, 0x2e34, 0x2f18, 0x2ff4, 0x30d0,
|
||||
0x31a4, 0x3348, 0x34dc, 0x3660, 0x37dc, 0x394c, 0x3ab0, 0x3c0c,
|
||||
0x3d60, 0x3eac, 0x3ff0, 0x412c, 0x4260, 0x4390, 0x44bc, 0x45e0,
|
||||
0x46fc, 0x4928, 0x4b44, 0x4d4c, 0x4f48, 0x5130, 0x5310, 0x54e0,
|
||||
0x56a4, 0x5860, 0x5a10, 0x5bb4, 0x5d54, 0x5ee8, 0x6074, 0x61f8,
|
||||
0x6378, 0x6660, 0x6930, 0x6be4, 0x6e88, 0x7118, 0x7394, 0x7600,
|
||||
0x7860, 0x7aac, 0x7cec, 0x7f20, 0x8148, 0x8364, 0x8578, 0x8780,
|
||||
0x897c, 0x8b70, 0x8d5c, 0x8f40, 0x911c, 0x92f0, 0x94bc, 0x9684,
|
||||
0x9840, 0x99fc, 0x9bac, 0x9d58, 0x9f00, 0xa0a0, 0xa23c, 0xa3d0,
|
||||
0xa564, 0xa6f0, 0xa878, 0xa9fc, 0xab78, 0xacf4, 0xae68, 0xafdc,
|
||||
0xb14c, 0xb2b4, 0xb41c, 0xb580, 0xb6e0, 0xb83c, 0xb994, 0xbaec,
|
||||
0xbc3c, 0xbed8, 0xc16c, 0xc3f0, 0xc66c, 0xc8dc, 0xcb44, 0xcda0,
|
||||
0xcff4, 0xd240, 0xd484, 0xd6c0, 0xd8f4, 0xdb20, 0xdd44, 0xdf64,
|
||||
0xe17c, 0xe38c, 0xe598, 0xe79c, 0xe99c, 0xeb94, 0xed88, 0xef74,
|
||||
0xf160, 0xf344, 0xf520, 0xf6fc, 0xf8d0, 0xfaa4, 0xfc70, 0xfe38,
|
||||
0xfffc, 0xfffc
|
||||
};
|
||||
|
||||
static const NvU16 sRGBOETFLUTVSSHeader[16] = {
|
||||
0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0xdb00, 0xb248, 0x0000,
|
||||
0x0005, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
/*
|
||||
* The two arrays below specify the PQ EOTF transfer function that's used to
|
||||
* convert from PQ encoded L'M'S' fixed-point to linear LMS FP16. This transfer
|
||||
* function is the inverse of the OETF curve.
|
||||
*/
|
||||
const NvU16 PQEOTFLUTEntries[PQ_EOTF_LUT_NUM_ENTRIES] = {
|
||||
0x0000, 0x0001, 0x0003, 0x0005, 0x0008, 0x000C, 0x0011, 0x0016, 0x001B,
|
||||
0x0022, 0x0028, 0x002F, 0x0037, 0x003F, 0x0048, 0x0051, 0x005A, 0x0064,
|
||||
0x006F, 0x007A, 0x0085, 0x0091, 0x009E, 0x00AB, 0x00B8, 0x00C6, 0x00D4,
|
||||
0x00E3, 0x00F3, 0x0102, 0x0113, 0x0123, 0x0135, 0x0146, 0x0158, 0x016B,
|
||||
0x017E, 0x0192, 0x01A6, 0x01BB, 0x01D0, 0x01E5, 0x01FC, 0x0212, 0x0229,
|
||||
0x0241, 0x0259, 0x0272, 0x028B, 0x02A4, 0x02BE, 0x02D9, 0x02F4, 0x0310,
|
||||
0x032C, 0x0349, 0x0366, 0x0384, 0x03A2, 0x03C1, 0x03E0, 0x0400, 0x0421,
|
||||
0x0442, 0x0463, 0x0485, 0x04A8, 0x04CB, 0x04EF, 0x0513, 0x0538, 0x055D,
|
||||
0x0583, 0x05AA, 0x05D1, 0x05F9, 0x0621, 0x064A, 0x0673, 0x069D, 0x06C7,
|
||||
0x06F3, 0x071E, 0x074B, 0x0777, 0x07A5, 0x07D3, 0x0801, 0x0819, 0x0830,
|
||||
0x0849, 0x0861, 0x087A, 0x0893, 0x08AD, 0x08C7, 0x08E1, 0x08FB, 0x0916,
|
||||
0x0931, 0x094C, 0x0968, 0x0984, 0x09A0, 0x09BD, 0x09DA, 0x09F7, 0x0A15,
|
||||
0x0A33, 0x0A51, 0x0A70, 0x0A8F, 0x0AAE, 0x0ACE, 0x0AEE, 0x0B0E, 0x0B2F,
|
||||
0x0B50, 0x0B71, 0x0B93, 0x0BB5, 0x0BD7, 0x0BFA, 0x0C0F, 0x0C20, 0x0C32,
|
||||
0x0C44, 0x0C56, 0x0C69, 0x0CB5, 0x0D03, 0x0D55, 0x0DA9, 0x0E01, 0x0E5B,
|
||||
0x0EB9, 0x0F1B, 0x0F7F, 0x0FE7, 0x1029, 0x1061, 0x109A, 0x10D5, 0x1111,
|
||||
0x1150, 0x1190, 0x11D3, 0x1217, 0x125E, 0x12A6, 0x12F0, 0x133D, 0x138B,
|
||||
0x13DC, 0x1417, 0x1442, 0x146D, 0x149A, 0x14C8, 0x14F7, 0x1527, 0x1558,
|
||||
0x158B, 0x15BF, 0x15F4, 0x162A, 0x1662, 0x169B, 0x16D5, 0x1711, 0x174E,
|
||||
0x178C, 0x17CC, 0x1806, 0x1828, 0x184A, 0x186D, 0x18B4, 0x18FF, 0x194D,
|
||||
0x199E, 0x19F3, 0x1A4B, 0x1AA7, 0x1B06, 0x1B37, 0x1B69, 0x1B9B, 0x1BCF,
|
||||
0x1C02, 0x1C1D, 0x1C38, 0x1C54, 0x1C70, 0x1C8D, 0x1CAB, 0x1CC9, 0x1CE7,
|
||||
0x1D06, 0x1D26, 0x1D46, 0x1D88, 0x1DCC, 0x1E13, 0x1E5C, 0x1EA8, 0x1EF6,
|
||||
0x1F47, 0x1F9A, 0x1FF1, 0x2025, 0x2053, 0x2082, 0x20B3, 0x20E6, 0x211A,
|
||||
0x214F, 0x2187, 0x21C0, 0x21FA, 0x2237, 0x2275, 0x22B5, 0x22F7, 0x233B,
|
||||
0x23C9, 0x2430, 0x247F, 0x24D3, 0x252B, 0x2589, 0x25EB, 0x2653, 0x26C1,
|
||||
0x2734, 0x27AD, 0x2817, 0x2838, 0x285A, 0x287C, 0x28A0, 0x28C5, 0x28EA,
|
||||
0x2911, 0x2938, 0x2960, 0x298A, 0x29B4, 0x29DF, 0x2A0C, 0x2A39, 0x2A68,
|
||||
0x2A98, 0x2AFA, 0x2B62, 0x2BCE, 0x2C20, 0x2C5B, 0x2C99, 0x2CDA, 0x2D1E,
|
||||
0x2D65, 0x2DB0, 0x2DFD, 0x2E4E, 0x2EA3, 0x2EFC, 0x2F58, 0x2FB8, 0x300E,
|
||||
0x3043, 0x307A, 0x30B3, 0x30D0, 0x30EE, 0x310D, 0x312C, 0x314C, 0x316D,
|
||||
0x318E, 0x31B0, 0x31D3, 0x31F6, 0x321A, 0x323F, 0x3265, 0x328B, 0x32B2,
|
||||
0x32DA, 0x332D, 0x3383, 0x33DC, 0x341D, 0x344D, 0x347F, 0x34B4, 0x34EA,
|
||||
0x3523, 0x355E, 0x359B, 0x35DB, 0x361D, 0x3662, 0x36A9, 0x36F3, 0x3740,
|
||||
0x3791, 0x37E4, 0x381D, 0x384A, 0x3879, 0x38A9, 0x38DB, 0x3910, 0x3946,
|
||||
0x397E, 0x39B8, 0x39F5, 0x3A34, 0x3A75, 0x3AB9, 0x3AFF, 0x3B48, 0x3B94,
|
||||
0x3BE2, 0x3C1A, 0x3C44, 0x3C70, 0x3C9D, 0x3CA0, 0x3CA3, 0x3CA6, 0x3CA9,
|
||||
0x3CAC, 0x3CAF, 0x3CB1, 0x3CB4, 0x3CB7, 0x3CBA, 0x3CBD, 0x3CC0, 0x3CC3,
|
||||
0x3CC6, 0x3CC9, 0x3CCC, 0x3CCF, 0x3CD2, 0x3CD5, 0x3CD8, 0x3CDB, 0x3CDE,
|
||||
0x3CE1, 0x3CE4, 0x3CE7, 0x3CEA, 0x3CEE, 0x3CF1, 0x3CF4, 0x3CF7, 0x3CFA,
|
||||
0x3CFD, 0x3D00, 0x3D03, 0x3D06, 0x3D09, 0x3D0D, 0x3D10, 0x3D13, 0x3D16,
|
||||
0x3D19, 0x3D1C, 0x3D20, 0x3D23, 0x3D26, 0x3D29, 0x3D2C, 0x3D30, 0x3D33,
|
||||
0x3D36, 0x3D39, 0x3D3D, 0x3D40, 0x3D43, 0x3D46, 0x3D4A, 0x3D4D, 0x3D50,
|
||||
0x3D54, 0x3D57, 0x3D5A, 0x3D5D, 0x3D61, 0x3D64, 0x3D9B, 0x3DD3, 0x3E0D,
|
||||
0x3E4A, 0x3E89, 0x3ECA, 0x3F0E, 0x3F54, 0x3F9C, 0x3FE8, 0x401B, 0x4043,
|
||||
0x406D, 0x4099, 0x40C6, 0x40F4, 0x4124, 0x4156, 0x418A, 0x41C0, 0x41F8,
|
||||
0x4232, 0x426D, 0x42AB, 0x42EB, 0x432E, 0x4373, 0x43BA, 0x4428, 0x4479,
|
||||
0x44D0, 0x452D, 0x4591, 0x45FC, 0x466F, 0x46EB, 0x472C, 0x476F, 0x47B5,
|
||||
0x47FE, 0x4824, 0x484B, 0x4874, 0x489D, 0x48F5, 0x4954, 0x4986, 0x49B9,
|
||||
0x49EF, 0x4A26, 0x4A5F, 0x4A9B, 0x4AD9, 0x4B19, 0x4B9F, 0x4C18, 0x4C66,
|
||||
0x4CBA, 0x4CE6, 0x4D13, 0x4D43, 0x4D74, 0x4DA7, 0x4DDC, 0x4E12, 0x4E4B,
|
||||
0x4E86, 0x4EC3, 0x4F02, 0x4F44, 0x4F88, 0x4FCE, 0x500C, 0x5032, 0x5082,
|
||||
0x50D8, 0x5106, 0x5135, 0x5166, 0x5199, 0x5205, 0x5278, 0x52F5, 0x537C,
|
||||
0x53C3, 0x5406, 0x542D, 0x5454, 0x54A9, 0x5503, 0x550F, 0x551B, 0x5527,
|
||||
0x5533, 0x5540, 0x554C, 0x5559, 0x5565, 0x5572, 0x557F, 0x558C, 0x5599,
|
||||
0x55A7, 0x55B4, 0x55C1, 0x55CF, 0x5607, 0x5641, 0x567E, 0x56BC, 0x56FE,
|
||||
0x5741, 0x5788, 0x57D1, 0x57D1
|
||||
};
|
||||
|
||||
const NvU32 EotfPQ512SegSizesLog2[64] = {
|
||||
6, 6, 4, 4, 4, 3, 4, 3, 3, 3, 2, 2, 2, 3, 3, 2,
|
||||
2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
6, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1, 2,
|
||||
2, 1, 1, 2, 2, 2, 2, 1, 2, 1, 1, 2, 1, 4, 2, 2,
|
||||
};
|
||||
|
||||
/*
|
||||
* The two arrays below specify the PQ OETF transfer function that's used to
|
||||
* convert from linear LMS FP16 to PQ encoded L'M'S' fixed-point.
|
||||
*/
|
||||
static const NvU16 PQOETFLUTEntries[PQ_OETF_LUT_NUM_ENTRIES] = {
|
||||
0x0000, 0x000C, 0x0014, 0x001C, 0x0028, 0x003C, 0x005C, 0x008C, 0x00D0,
|
||||
0x0134, 0x0184, 0x01C8, 0x0238, 0x029C, 0x033C, 0x03C4, 0x043C, 0x04A4,
|
||||
0x0504, 0x0560, 0x0600, 0x0690, 0x0714, 0x078C, 0x07FC, 0x0864, 0x08C8,
|
||||
0x0924, 0x0980, 0x09D4, 0x0A24, 0x0A70, 0x0B04, 0x0B90, 0x0C10, 0x0C88,
|
||||
0x0CFC, 0x0D68, 0x0DD4, 0x0E38, 0x0EF4, 0x0FA4, 0x1048, 0x10E4, 0x1174,
|
||||
0x1200, 0x1284, 0x1304, 0x13F4, 0x14D0, 0x159C, 0x165C, 0x1714, 0x17C0,
|
||||
0x1864, 0x1900, 0x1A28, 0x1B34, 0x1C30, 0x1D1C, 0x1DFC, 0x1ECC, 0x1F94,
|
||||
0x2050, 0x2104, 0x21B0, 0x2258, 0x22F8, 0x2390, 0x2424, 0x24B4, 0x2540,
|
||||
0x25C4, 0x2648, 0x26C4, 0x2740, 0x27B8, 0x282C, 0x289C, 0x290C, 0x29E0,
|
||||
0x2AAC, 0x2B70, 0x2C2C, 0x2CE0, 0x2D90, 0x2E38, 0x2ED8, 0x2F74, 0x300C,
|
||||
0x30A0, 0x3130, 0x31BC, 0x3244, 0x32C8, 0x3348, 0x3440, 0x352C, 0x360C,
|
||||
0x36E4, 0x37B4, 0x387C, 0x393C, 0x39F8, 0x3AA8, 0x3B58, 0x3C00, 0x3CA4,
|
||||
0x3D44, 0x3DDC, 0x3E74, 0x3F04, 0x401C, 0x4128, 0x4228, 0x431C, 0x4408,
|
||||
0x44E8, 0x45C4, 0x4694, 0x475C, 0x4820, 0x48DC, 0x4994, 0x4A48, 0x4AF4,
|
||||
0x4B9C, 0x4C3C, 0x4D78, 0x4EA0, 0x4FBC, 0x50CC, 0x51D0, 0x52CC, 0x53BC,
|
||||
0x54A0, 0x5580, 0x5658, 0x5728, 0x57F0, 0x58B4, 0x5974, 0x5A2C, 0x5ADC,
|
||||
0x5C34, 0x5D7C, 0x5EB4, 0x5FDC, 0x60F4, 0x6204, 0x630C, 0x6404, 0x64F8,
|
||||
0x65E0, 0x66C4, 0x679C, 0x6870, 0x693C, 0x6A04, 0x6AC4, 0x6C38, 0x6D94,
|
||||
0x6EE4, 0x7020, 0x7150, 0x7274, 0x738C, 0x7498, 0x7598, 0x7694, 0x7784,
|
||||
0x786C, 0x794C, 0x7A24, 0x7AF8, 0x7BC4, 0x7D50, 0x7EC4, 0x8024, 0x8174,
|
||||
0x82B4, 0x83E8, 0x850C, 0x8628, 0x8738, 0x883C, 0x8938, 0x8A2C, 0x8B18,
|
||||
0x8BFC, 0x8CD8, 0x8DB0, 0x8F4C, 0x90D0, 0x9240, 0x939C, 0x94EC, 0x962C,
|
||||
0x975C, 0x9880, 0x999C, 0x9AAC, 0x9BB0, 0x9CAC, 0x9DA0, 0x9E8C, 0x9F70,
|
||||
0xA04C, 0xA1F4, 0xA384, 0xA500, 0xA664, 0xA7BC, 0xA904, 0xAA3C, 0xAB6C,
|
||||
0xAC8C, 0xADA0, 0xAEAC, 0xAFAC, 0xB0A4, 0xB194, 0xB27C, 0xB360, 0xB510,
|
||||
0xB6A4, 0xB824, 0xB994, 0xBAF0, 0xBC3C, 0xBD78, 0xBEA8, 0xBFCC, 0xC0E4,
|
||||
0xC1F0, 0xC2F4, 0xC3F0, 0xC4E4, 0xC5CC, 0xC6B0, 0xC78C, 0xC860, 0xC930,
|
||||
0xC9F8, 0xCABC, 0xCB7C, 0xCC38, 0xCCEC, 0xCD9C, 0xCE48, 0xCEF0, 0xCF94,
|
||||
0xD034, 0xD0D4, 0xD16C, 0xD200, 0xD294, 0xD324, 0xD3B4, 0xD43C, 0xD4C4,
|
||||
0xD54C, 0xD5CC, 0xD650, 0xD6CC, 0xD748, 0xD7C4, 0xD83C, 0xD8B0, 0xD924,
|
||||
0xD994, 0xDA08, 0xDAE0, 0xDBB4, 0xDC84, 0xDD4C, 0xDE10, 0xDECC, 0xDF84,
|
||||
0xE038, 0xE0E8, 0xE194, 0xE238, 0xE2DC, 0xE37C, 0xE418, 0xE4B0, 0xE544,
|
||||
0xE5D4, 0xE664, 0xE6F0, 0xE778, 0xE800, 0xE884, 0xE904, 0xE984, 0xEA00,
|
||||
0xEA7C, 0xEAF4, 0xEB68, 0xEBDC, 0xEC50, 0xECC0, 0xED30, 0xEE08, 0xEED8,
|
||||
0xEFA4, 0xF068, 0xF128, 0xF1E4, 0xF298, 0xF348, 0xF3F4, 0xF49C, 0xF540,
|
||||
0xF5E0, 0xF67C, 0xF714, 0xF7A8, 0xF83C, 0xF8CC, 0xF958, 0xF9E0, 0xFA68,
|
||||
0xFAEC, 0xFB6C, 0xFBE8, 0xFC64, 0xFCE0, 0xFD58, 0xFDCC, 0xFE40, 0xFEB4,
|
||||
0xFF24, 0xFF90, 0xFFFC, 0xFFFC,
|
||||
};
|
||||
|
||||
static const NvU32 OetfPQ512SegSizesLog2[33] = {
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 3, 3,
|
||||
3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
|
||||
5,
|
||||
};
|
||||
|
||||
enum FMTCoeffType
|
||||
{
|
||||
FMT_COEFF_TYPE_IDENTITY = 0,
|
||||
@@ -126,18 +404,6 @@ UpdateCompositionC5(NVDevEvoPtr pDevEvo,
|
||||
NvBool bypassComposition,
|
||||
enum NvKmsSurfaceMemoryFormat format);
|
||||
|
||||
static void
|
||||
EvoSetupIdentityOutputLutC5(NVEvoLutDataRec *pData,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss);
|
||||
|
||||
static void
|
||||
EvoSetupIdentityBaseLutC5(NVEvoLutDataRec *pData,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss);
|
||||
|
||||
ct_assert(NV_EVO_LOCK_PIN_0 >
|
||||
NVC37D_HEAD_SET_CONTROL_MASTER_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1);
|
||||
|
||||
@@ -366,87 +632,6 @@ static const struct NvKmsCscMatrix LMSToRec2020RGB = {{
|
||||
{ 0x1ff964, 0x1fe6a4, 0x11ff4, 0 },
|
||||
}};
|
||||
|
||||
/*
|
||||
* The two arrays below specify the PQ OETF transfer function that's used to
|
||||
* convert from linear LMS FP16 to PQ encoded L'M'S' fixed-point.
|
||||
*/
|
||||
static const NvU32 OetfPQ512SegSizesLog2[] = {
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 3, 3,
|
||||
3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5,
|
||||
5,
|
||||
};
|
||||
|
||||
static const NvU16 OetfPQ512Entries[] = {
|
||||
0x0000, 0x000C, 0x0014, 0x001C, 0x0028, 0x003C, 0x005C, 0x008C, 0x00D0, 0x0134, 0x0184, 0x01C8, 0x0238, 0x029C, 0x033C, 0x03C4,
|
||||
0x043C, 0x04A4, 0x0504, 0x0560, 0x0600, 0x0690, 0x0714, 0x078C, 0x07FC, 0x0864, 0x08C8, 0x0924, 0x0980, 0x09D4, 0x0A24, 0x0A70,
|
||||
0x0B04, 0x0B90, 0x0C10, 0x0C88, 0x0CFC, 0x0D68, 0x0DD4, 0x0E38, 0x0EF4, 0x0FA4, 0x1048, 0x10E4, 0x1174, 0x1200, 0x1284, 0x1304,
|
||||
0x13F4, 0x14D0, 0x159C, 0x165C, 0x1714, 0x17C0, 0x1864, 0x1900, 0x1A28, 0x1B34, 0x1C30, 0x1D1C, 0x1DFC, 0x1ECC, 0x1F94, 0x2050,
|
||||
0x2104, 0x21B0, 0x2258, 0x22F8, 0x2390, 0x2424, 0x24B4, 0x2540, 0x25C4, 0x2648, 0x26C4, 0x2740, 0x27B8, 0x282C, 0x289C, 0x290C,
|
||||
0x29E0, 0x2AAC, 0x2B70, 0x2C2C, 0x2CE0, 0x2D90, 0x2E38, 0x2ED8, 0x2F74, 0x300C, 0x30A0, 0x3130, 0x31BC, 0x3244, 0x32C8, 0x3348,
|
||||
0x3440, 0x352C, 0x360C, 0x36E4, 0x37B4, 0x387C, 0x393C, 0x39F8, 0x3AA8, 0x3B58, 0x3C00, 0x3CA4, 0x3D44, 0x3DDC, 0x3E74, 0x3F04,
|
||||
0x401C, 0x4128, 0x4228, 0x431C, 0x4408, 0x44E8, 0x45C4, 0x4694, 0x475C, 0x4820, 0x48DC, 0x4994, 0x4A48, 0x4AF4, 0x4B9C, 0x4C3C,
|
||||
0x4D78, 0x4EA0, 0x4FBC, 0x50CC, 0x51D0, 0x52CC, 0x53BC, 0x54A0, 0x5580, 0x5658, 0x5728, 0x57F0, 0x58B4, 0x5974, 0x5A2C, 0x5ADC,
|
||||
0x5C34, 0x5D7C, 0x5EB4, 0x5FDC, 0x60F4, 0x6204, 0x630C, 0x6404, 0x64F8, 0x65E0, 0x66C4, 0x679C, 0x6870, 0x693C, 0x6A04, 0x6AC4,
|
||||
0x6C38, 0x6D94, 0x6EE4, 0x7020, 0x7150, 0x7274, 0x738C, 0x7498, 0x7598, 0x7694, 0x7784, 0x786C, 0x794C, 0x7A24, 0x7AF8, 0x7BC4,
|
||||
0x7D50, 0x7EC4, 0x8024, 0x8174, 0x82B4, 0x83E8, 0x850C, 0x8628, 0x8738, 0x883C, 0x8938, 0x8A2C, 0x8B18, 0x8BFC, 0x8CD8, 0x8DB0,
|
||||
0x8F4C, 0x90D0, 0x9240, 0x939C, 0x94EC, 0x962C, 0x975C, 0x9880, 0x999C, 0x9AAC, 0x9BB0, 0x9CAC, 0x9DA0, 0x9E8C, 0x9F70, 0xA04C,
|
||||
0xA1F4, 0xA384, 0xA500, 0xA664, 0xA7BC, 0xA904, 0xAA3C, 0xAB6C, 0xAC8C, 0xADA0, 0xAEAC, 0xAFAC, 0xB0A4, 0xB194, 0xB27C, 0xB360,
|
||||
0xB510, 0xB6A4, 0xB824, 0xB994, 0xBAF0, 0xBC3C, 0xBD78, 0xBEA8, 0xBFCC, 0xC0E4, 0xC1F0, 0xC2F4, 0xC3F0, 0xC4E4, 0xC5CC, 0xC6B0,
|
||||
0xC78C, 0xC860, 0xC930, 0xC9F8, 0xCABC, 0xCB7C, 0xCC38, 0xCCEC, 0xCD9C, 0xCE48, 0xCEF0, 0xCF94, 0xD034, 0xD0D4, 0xD16C, 0xD200,
|
||||
0xD294, 0xD324, 0xD3B4, 0xD43C, 0xD4C4, 0xD54C, 0xD5CC, 0xD650, 0xD6CC, 0xD748, 0xD7C4, 0xD83C, 0xD8B0, 0xD924, 0xD994, 0xDA08,
|
||||
0xDAE0, 0xDBB4, 0xDC84, 0xDD4C, 0xDE10, 0xDECC, 0xDF84, 0xE038, 0xE0E8, 0xE194, 0xE238, 0xE2DC, 0xE37C, 0xE418, 0xE4B0, 0xE544,
|
||||
0xE5D4, 0xE664, 0xE6F0, 0xE778, 0xE800, 0xE884, 0xE904, 0xE984, 0xEA00, 0xEA7C, 0xEAF4, 0xEB68, 0xEBDC, 0xEC50, 0xECC0, 0xED30,
|
||||
0xEE08, 0xEED8, 0xEFA4, 0xF068, 0xF128, 0xF1E4, 0xF298, 0xF348, 0xF3F4, 0xF49C, 0xF540, 0xF5E0, 0xF67C, 0xF714, 0xF7A8, 0xF83C,
|
||||
0xF8CC, 0xF958, 0xF9E0, 0xFA68, 0xFAEC, 0xFB6C, 0xFBE8, 0xFC64, 0xFCE0, 0xFD58, 0xFDCC, 0xFE40, 0xFEB4, 0xFF24, 0xFF90, 0xFFFC,
|
||||
};
|
||||
|
||||
/*
|
||||
* The two arrays below specify the PQ EOTF transfer function that's used to
|
||||
* convert from PQ encoded L'M'S' fixed-point to linear LMS FP16. This transfer
|
||||
* function is the inverse of the OETF curve.
|
||||
*/
|
||||
static const NvU32 EotfPQ512SegSizesLog2[] = {
|
||||
6, 6, 4, 4, 4, 3, 4, 3, 3, 3, 2, 2, 2, 3, 3, 2,
|
||||
2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
||||
6, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1, 2,
|
||||
2, 1, 1, 2, 2, 2, 2, 1, 2, 1, 1, 2, 1, 4, 2, 2,
|
||||
};
|
||||
|
||||
static const NvU16 EotfPQ512Entries[] = {
|
||||
0x0000, 0x0001, 0x0003, 0x0005, 0x0008, 0x000C, 0x0011, 0x0016, 0x001B, 0x0022, 0x0028, 0x002F, 0x0037, 0x003F, 0x0048, 0x0051,
|
||||
0x005A, 0x0064, 0x006F, 0x007A, 0x0085, 0x0091, 0x009E, 0x00AB, 0x00B8, 0x00C6, 0x00D4, 0x00E3, 0x00F3, 0x0102, 0x0113, 0x0123,
|
||||
0x0135, 0x0146, 0x0158, 0x016B, 0x017E, 0x0192, 0x01A6, 0x01BB, 0x01D0, 0x01E5, 0x01FC, 0x0212, 0x0229, 0x0241, 0x0259, 0x0272,
|
||||
0x028B, 0x02A4, 0x02BE, 0x02D9, 0x02F4, 0x0310, 0x032C, 0x0349, 0x0366, 0x0384, 0x03A2, 0x03C1, 0x03E0, 0x0400, 0x0421, 0x0442,
|
||||
0x0463, 0x0485, 0x04A8, 0x04CB, 0x04EF, 0x0513, 0x0538, 0x055D, 0x0583, 0x05AA, 0x05D1, 0x05F9, 0x0621, 0x064A, 0x0673, 0x069D,
|
||||
0x06C7, 0x06F3, 0x071E, 0x074B, 0x0777, 0x07A5, 0x07D3, 0x0801, 0x0819, 0x0830, 0x0849, 0x0861, 0x087A, 0x0893, 0x08AD, 0x08C7,
|
||||
0x08E1, 0x08FB, 0x0916, 0x0931, 0x094C, 0x0968, 0x0984, 0x09A0, 0x09BD, 0x09DA, 0x09F7, 0x0A15, 0x0A33, 0x0A51, 0x0A70, 0x0A8F,
|
||||
0x0AAE, 0x0ACE, 0x0AEE, 0x0B0E, 0x0B2F, 0x0B50, 0x0B71, 0x0B93, 0x0BB5, 0x0BD7, 0x0BFA, 0x0C0F, 0x0C20, 0x0C32, 0x0C44, 0x0C56,
|
||||
0x0C69, 0x0CB5, 0x0D03, 0x0D55, 0x0DA9, 0x0E01, 0x0E5B, 0x0EB9, 0x0F1B, 0x0F7F, 0x0FE7, 0x1029, 0x1061, 0x109A, 0x10D5, 0x1111,
|
||||
0x1150, 0x1190, 0x11D3, 0x1217, 0x125E, 0x12A6, 0x12F0, 0x133D, 0x138B, 0x13DC, 0x1417, 0x1442, 0x146D, 0x149A, 0x14C8, 0x14F7,
|
||||
0x1527, 0x1558, 0x158B, 0x15BF, 0x15F4, 0x162A, 0x1662, 0x169B, 0x16D5, 0x1711, 0x174E, 0x178C, 0x17CC, 0x1806, 0x1828, 0x184A,
|
||||
0x186D, 0x18B4, 0x18FF, 0x194D, 0x199E, 0x19F3, 0x1A4B, 0x1AA7, 0x1B06, 0x1B37, 0x1B69, 0x1B9B, 0x1BCF, 0x1C02, 0x1C1D, 0x1C38,
|
||||
0x1C54, 0x1C70, 0x1C8D, 0x1CAB, 0x1CC9, 0x1CE7, 0x1D06, 0x1D26, 0x1D46, 0x1D88, 0x1DCC, 0x1E13, 0x1E5C, 0x1EA8, 0x1EF6, 0x1F47,
|
||||
0x1F9A, 0x1FF1, 0x2025, 0x2053, 0x2082, 0x20B3, 0x20E6, 0x211A, 0x214F, 0x2187, 0x21C0, 0x21FA, 0x2237, 0x2275, 0x22B5, 0x22F7,
|
||||
0x233B, 0x23C9, 0x2430, 0x247F, 0x24D3, 0x252B, 0x2589, 0x25EB, 0x2653, 0x26C1, 0x2734, 0x27AD, 0x2817, 0x2838, 0x285A, 0x287C,
|
||||
0x28A0, 0x28C5, 0x28EA, 0x2911, 0x2938, 0x2960, 0x298A, 0x29B4, 0x29DF, 0x2A0C, 0x2A39, 0x2A68, 0x2A98, 0x2AFA, 0x2B62, 0x2BCE,
|
||||
0x2C20, 0x2C5B, 0x2C99, 0x2CDA, 0x2D1E, 0x2D65, 0x2DB0, 0x2DFD, 0x2E4E, 0x2EA3, 0x2EFC, 0x2F58, 0x2FB8, 0x300E, 0x3043, 0x307A,
|
||||
0x30B3, 0x30D0, 0x30EE, 0x310D, 0x312C, 0x314C, 0x316D, 0x318E, 0x31B0, 0x31D3, 0x31F6, 0x321A, 0x323F, 0x3265, 0x328B, 0x32B2,
|
||||
0x32DA, 0x332D, 0x3383, 0x33DC, 0x341D, 0x344D, 0x347F, 0x34B4, 0x34EA, 0x3523, 0x355E, 0x359B, 0x35DB, 0x361D, 0x3662, 0x36A9,
|
||||
0x36F3, 0x3740, 0x3791, 0x37E4, 0x381D, 0x384A, 0x3879, 0x38A9, 0x38DB, 0x3910, 0x3946, 0x397E, 0x39B8, 0x39F5, 0x3A34, 0x3A75,
|
||||
0x3AB9, 0x3AFF, 0x3B48, 0x3B94, 0x3BE2, 0x3C1A, 0x3C44, 0x3C70, 0x3C9D, 0x3CA0, 0x3CA3, 0x3CA6, 0x3CA9, 0x3CAC, 0x3CAF, 0x3CB1,
|
||||
0x3CB4, 0x3CB7, 0x3CBA, 0x3CBD, 0x3CC0, 0x3CC3, 0x3CC6, 0x3CC9, 0x3CCC, 0x3CCF, 0x3CD2, 0x3CD5, 0x3CD8, 0x3CDB, 0x3CDE, 0x3CE1,
|
||||
0x3CE4, 0x3CE7, 0x3CEA, 0x3CEE, 0x3CF1, 0x3CF4, 0x3CF7, 0x3CFA, 0x3CFD, 0x3D00, 0x3D03, 0x3D06, 0x3D09, 0x3D0D, 0x3D10, 0x3D13,
|
||||
0x3D16, 0x3D19, 0x3D1C, 0x3D20, 0x3D23, 0x3D26, 0x3D29, 0x3D2C, 0x3D30, 0x3D33, 0x3D36, 0x3D39, 0x3D3D, 0x3D40, 0x3D43, 0x3D46,
|
||||
0x3D4A, 0x3D4D, 0x3D50, 0x3D54, 0x3D57, 0x3D5A, 0x3D5D, 0x3D61, 0x3D64, 0x3D9B, 0x3DD3, 0x3E0D, 0x3E4A, 0x3E89, 0x3ECA, 0x3F0E,
|
||||
0x3F54, 0x3F9C, 0x3FE8, 0x401B, 0x4043, 0x406D, 0x4099, 0x40C6, 0x40F4, 0x4124, 0x4156, 0x418A, 0x41C0, 0x41F8, 0x4232, 0x426D,
|
||||
0x42AB, 0x42EB, 0x432E, 0x4373, 0x43BA, 0x4428, 0x4479, 0x44D0, 0x452D, 0x4591, 0x45FC, 0x466F, 0x46EB, 0x472C, 0x476F, 0x47B5,
|
||||
0x47FE, 0x4824, 0x484B, 0x4874, 0x489D, 0x48F5, 0x4954, 0x4986, 0x49B9, 0x49EF, 0x4A26, 0x4A5F, 0x4A9B, 0x4AD9, 0x4B19, 0x4B9F,
|
||||
0x4C18, 0x4C66, 0x4CBA, 0x4CE6, 0x4D13, 0x4D43, 0x4D74, 0x4DA7, 0x4DDC, 0x4E12, 0x4E4B, 0x4E86, 0x4EC3, 0x4F02, 0x4F44, 0x4F88,
|
||||
0x4FCE, 0x500C, 0x5032, 0x5082, 0x50D8, 0x5106, 0x5135, 0x5166, 0x5199, 0x5205, 0x5278, 0x52F5, 0x537C, 0x53C3, 0x5406, 0x542D,
|
||||
0x5454, 0x54A9, 0x5503, 0x550F, 0x551B, 0x5527, 0x5533, 0x5540, 0x554C, 0x5559, 0x5565, 0x5572, 0x557F, 0x558C, 0x5599, 0x55A7,
|
||||
0x55B4, 0x55C1, 0x55CF, 0x5607, 0x5641, 0x567E, 0x56BC, 0x56FE, 0x5741, 0x5788, 0x57D1,
|
||||
};
|
||||
|
||||
#define TMO_LUT_NUM_SEGMENTS 64
|
||||
#define TMO_LUT_SEG_SIZE_LOG2 4
|
||||
#define TMO_LUT_NUM_ENTRIES 1024
|
||||
@@ -1023,19 +1208,19 @@ static void EvoInitChannelC5(NVDevEvoPtr pDevEvo, NVEvoChannelPtr pChannel)
|
||||
NVEvoWindowCaps *pWinCaps =
|
||||
&pDevEvo->gpus[0].capabilities.window[pChannel->instance];
|
||||
NvU32 csc0SizesLen = ARRAY_LEN(OetfPQ512SegSizesLog2);
|
||||
NvU32 csc0EntriesLen = ARRAY_LEN(OetfPQ512Entries);
|
||||
NvU32 csc0EntriesLen = PQ_OETF_LUT_NUM_ENTRIES;
|
||||
NvU32 csc1SizesLen = ARRAY_LEN(EotfPQ512SegSizesLog2);
|
||||
NvU32 csc1EntriesLen = ARRAY_LEN(EotfPQ512Entries);
|
||||
NvU32 csc1EntriesLen = PQ_EOTF_LUT_NUM_ENTRIES;
|
||||
|
||||
InitTaps5ScalerCoefficientsC5(pDevEvo, pChannel, TRUE);
|
||||
|
||||
if (pWinCaps->cscLUTsPresent) {
|
||||
InitCsc0LUT(pChannel,
|
||||
OetfPQ512SegSizesLog2, csc0SizesLen,
|
||||
OetfPQ512Entries, csc0EntriesLen);
|
||||
PQOETFLUTEntries, csc0EntriesLen);
|
||||
InitCsc1LUT(pChannel,
|
||||
EotfPQ512SegSizesLog2, csc1SizesLen,
|
||||
EotfPQ512Entries, csc1EntriesLen);
|
||||
PQEOTFLUTEntries, csc1EntriesLen);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1097,25 +1282,138 @@ static void EvoSetFMTMatrixC5(
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
FillLut(NVEvoLutEntryRec *pEntry, const NvU16 *lut, const NvU32 numLutEntries,
|
||||
const NvU16 *vssHeader)
|
||||
{
|
||||
NvU32 i = 0;
|
||||
|
||||
if ((pEntry == NULL) || (lut == NULL) || (vssHeader == NULL)) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
// VSS header
|
||||
for (i = 0; i < NV_LUT_VSS_HEADER_SIZE; i++) {
|
||||
// 4 * i because there are 4 NvU16s per NVEvoLutEntryRec.
|
||||
nvkms_memcpy(&(pEntry[i]), vssHeader + (4 * i), sizeof(NVEvoLutEntryRec));
|
||||
}
|
||||
|
||||
// nvdisplay 3 uses FP16 entries in the ILUT and 16-bit fixed-point entries
|
||||
// in the OLUT. Both are stored as NvU16.
|
||||
for (i = 0; i < numLutEntries; i++) {
|
||||
pEntry[NV_LUT_VSS_HEADER_SIZE + i].Red =
|
||||
pEntry[NV_LUT_VSS_HEADER_SIZE + i].Green =
|
||||
pEntry[NV_LUT_VSS_HEADER_SIZE + i].Blue = lut[i];
|
||||
}
|
||||
|
||||
done:
|
||||
return;
|
||||
}
|
||||
|
||||
// TODO(mtrost): refactor to populate PQ ILUT/OLUT with generic FillLut()
|
||||
// function instead.
|
||||
static void EvoSetupPQEotfBaseLutC5(NVEvoLutDataRec *pData)
|
||||
{
|
||||
NvU32 lutDataStartingIndex = NV_LUT_VSS_HEADER_SIZE;
|
||||
NvU32 eotfTableIdx;
|
||||
NvU64 vssHead = 0;
|
||||
NvU32 lutEntryCounter = 0, i;
|
||||
|
||||
// VSS Header
|
||||
for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) {
|
||||
vssHead = 0;
|
||||
for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < ARRAY_LEN(EotfPQ512SegSizesLog2))); i++) {
|
||||
NvU64 temp = EotfPQ512SegSizesLog2[(lutEntryCounter * 16) + i];
|
||||
temp = temp << (i * 3);
|
||||
vssHead |= temp;
|
||||
}
|
||||
nvkms_memcpy(&(pData->base[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec));
|
||||
}
|
||||
|
||||
for (eotfTableIdx = 0; eotfTableIdx < PQ_EOTF_LUT_NUM_ENTRIES; eotfTableIdx++) {
|
||||
/*
|
||||
* Values are in range [0.0, 125.0], will be scaled back by OLUT.
|
||||
* XXX HDR TODO: Divide by 125.0 if output mode is not HDR?
|
||||
*/
|
||||
pData->base[eotfTableIdx + lutDataStartingIndex].Red =
|
||||
pData->base[eotfTableIdx + lutDataStartingIndex].Green =
|
||||
pData->base[eotfTableIdx + lutDataStartingIndex].Blue =
|
||||
PQEOTFLUTEntries[eotfTableIdx];
|
||||
}
|
||||
}
|
||||
|
||||
// TODO(mtrost): refactor to populate PQ ILUT/OLUT with generic FillLut()
|
||||
// function instead.
|
||||
static void EvoSetupPQOetfOutputLutC5(NVEvoLutDataRec *pData)
|
||||
{
|
||||
NvU32 lutDataStartingIndex = NV_LUT_VSS_HEADER_SIZE;
|
||||
NvU32 oetfTableIdx;
|
||||
NvU64 vssHead = 0;
|
||||
NvU32 lutEntryCounter = 0, i;
|
||||
|
||||
// VSS Header
|
||||
for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) {
|
||||
vssHead = 0;
|
||||
for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < ARRAY_LEN(OetfPQ512SegSizesLog2))); i++) {
|
||||
NvU64 temp = OetfPQ512SegSizesLog2[(lutEntryCounter * 16) + i];
|
||||
temp = temp << (i * 3);
|
||||
vssHead |= temp;
|
||||
}
|
||||
nvkms_memcpy(&(pData->output[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec));
|
||||
}
|
||||
|
||||
for (oetfTableIdx = 0; oetfTableIdx < PQ_OETF_LUT_NUM_ENTRIES; oetfTableIdx++) {
|
||||
pData->output[oetfTableIdx + lutDataStartingIndex].Red =
|
||||
pData->output[oetfTableIdx + lutDataStartingIndex].Green =
|
||||
pData->output[oetfTableIdx + lutDataStartingIndex].Blue =
|
||||
PQOETFLUTEntries[oetfTableIdx];
|
||||
}
|
||||
}
|
||||
|
||||
static void PopulateIdentityLut(NVEvoLutDataRec *pData)
|
||||
{
|
||||
NvU32 i = 0;
|
||||
|
||||
for (i = 0; i < NV_NUM_EVO_LUT_ENTRIES - 1; i++) {
|
||||
// nvdisplay 3 uses FP16 entries in the ILUT.
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + i].Red =
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + i].Green =
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + i].Blue = nvUnorm10ToFp16(i).v;
|
||||
|
||||
// nvdisplay 3 uses 16-bit fixed-point entries in the OLUT.
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + i].Red =
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + i].Green =
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + i].Blue = (i << (16 - 10));
|
||||
}
|
||||
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES - 1] =
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES - 2];
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES - 1] =
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES - 2];
|
||||
}
|
||||
|
||||
void nvEvoInitDefaultLutC5(NVDevEvoPtr pDevEvo)
|
||||
{
|
||||
NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut;
|
||||
NvU16 sd;
|
||||
|
||||
nvAssert(pLut);
|
||||
|
||||
for (sd = 0; sd < pDevEvo->numSubDevices; sd++) {
|
||||
NvU32 lutSize;
|
||||
NvBool isLutModeVss;
|
||||
NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd];
|
||||
|
||||
EvoSetupIdentityBaseLutC5(pData,
|
||||
&pDevEvo->lut.defaultBaseLUTState[sd],
|
||||
&lutSize, &isLutModeVss);
|
||||
// Populate Identity ILUT and OLUT.
|
||||
NVEvoLutDataRec *pData =
|
||||
pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_IDENTITY]->subDeviceAddress[sd];
|
||||
PopulateIdentityLut(pData);
|
||||
|
||||
EvoSetupIdentityOutputLutC5(pData,
|
||||
&pDevEvo->lut.defaultOutputLUTState[sd],
|
||||
&lutSize, &isLutModeVss);
|
||||
// Populate sRGB ILUT (degamma) and OLUT (regamma).
|
||||
pData = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_SRGB]->subDeviceAddress[sd];
|
||||
FillLut(pData->base, sRGBEOTFLUTEntries,
|
||||
SRGB_EOTF_LUT_NUM_ENTRIES, sRGBEOTFLUTVSSHeader);
|
||||
FillLut(pData->output, sRGBOETFLUTEntries,
|
||||
SRGB_OETF_LUT_NUM_ENTRIES, sRGBOETFLUTVSSHeader);
|
||||
|
||||
// Populate PQ ILUT (degamma) and OLUT (regamma).
|
||||
pData = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_PQ]->subDeviceAddress[sd];
|
||||
EvoSetupPQEotfBaseLutC5(pData);
|
||||
EvoSetupPQOetfOutputLutC5(pData);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4284,97 +4582,14 @@ EvoFlipC3(NVDevEvoPtr pDevEvo,
|
||||
format);
|
||||
}
|
||||
|
||||
static void EvoSetupPQEotfBaseLutC5(NVEvoLutDataRec *pData,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss)
|
||||
{
|
||||
NvU32 lutDataStartingIndex = NV_LUT_VSS_HEADER_SIZE;
|
||||
NvU32 numEotfPQ512Entries = ARRAY_LEN(EotfPQ512Entries);
|
||||
NvU32 eotfTableIdx;
|
||||
NvU64 vssHead = 0;
|
||||
NvU32 lutEntryCounter = 0, i;
|
||||
|
||||
// Skip LUT data init if already done
|
||||
if (*lutState == NvKmsLUTStatePQ) {
|
||||
goto skipInit;
|
||||
}
|
||||
|
||||
// VSS Header
|
||||
for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) {
|
||||
vssHead = 0;
|
||||
for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < ARRAY_LEN(EotfPQ512SegSizesLog2))); i++) {
|
||||
NvU64 temp = EotfPQ512SegSizesLog2[(lutEntryCounter * 16) + i];
|
||||
temp = temp << (i * 3);
|
||||
vssHead |= temp;
|
||||
}
|
||||
nvkms_memcpy(&(pData->base[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec));
|
||||
}
|
||||
|
||||
for (eotfTableIdx = 0; eotfTableIdx < numEotfPQ512Entries; eotfTableIdx++) {
|
||||
/*
|
||||
* Values are in range [0.0, 125.0], will be scaled back by OLUT.
|
||||
* XXX HDR TODO: Divide by 125.0 if output mode is not HDR?
|
||||
*/
|
||||
pData->base[eotfTableIdx + lutDataStartingIndex].Red =
|
||||
pData->base[eotfTableIdx + lutDataStartingIndex].Green =
|
||||
pData->base[eotfTableIdx + lutDataStartingIndex].Blue =
|
||||
EotfPQ512Entries[eotfTableIdx];
|
||||
}
|
||||
|
||||
// Copy the last entry for interpolation
|
||||
pData->base[numEotfPQ512Entries + lutDataStartingIndex].Red =
|
||||
pData->base[numEotfPQ512Entries + lutDataStartingIndex - 1].Red;
|
||||
pData->base[numEotfPQ512Entries + lutDataStartingIndex].Green =
|
||||
pData->base[numEotfPQ512Entries + lutDataStartingIndex - 1].Green;
|
||||
pData->base[numEotfPQ512Entries + lutDataStartingIndex].Blue =
|
||||
pData->base[numEotfPQ512Entries + lutDataStartingIndex - 1].Blue;
|
||||
|
||||
skipInit:
|
||||
*lutState = NvKmsLUTStatePQ;
|
||||
*lutSize = NV_LUT_VSS_HEADER_SIZE + numEotfPQ512Entries + 1;
|
||||
*isLutModeVss = TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
EvoSetupIdentityBaseLutC5(NVEvoLutDataRec *pData,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss)
|
||||
{
|
||||
int i;
|
||||
|
||||
// Skip LUT data init if already done
|
||||
if (*lutState == NvKmsLUTStateIdentity) {
|
||||
goto skipInit;
|
||||
}
|
||||
|
||||
ct_assert(NV_NUM_EVO_LUT_ENTRIES == 1025);
|
||||
|
||||
// nvdisplay 3 uses FP16 entries in the ILUT.
|
||||
for (i = 0; i < 1024; i++) {
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + i].Red =
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + i].Green =
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + i].Blue = nvUnorm10ToFp16(i).v;
|
||||
}
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + 1024] =
|
||||
pData->base[NV_LUT_VSS_HEADER_SIZE + 1023];
|
||||
|
||||
skipInit:
|
||||
*lutState = NvKmsLUTStateIdentity;
|
||||
*lutSize = NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES;
|
||||
*isLutModeVss = FALSE;
|
||||
}
|
||||
|
||||
static void SetILUTSurfaceAddress(
|
||||
NVEvoChannelPtr pChannel,
|
||||
const NVSurfaceDescriptor *pSurfaceDesc,
|
||||
NvU32 ctxDma,
|
||||
NvU32 offset)
|
||||
{
|
||||
NvU32 ctxDmaHandle = pSurfaceDesc ? pSurfaceDesc->ctxDmaHandle : 0;
|
||||
|
||||
nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_CONTEXT_DMA_ILUT, 1);
|
||||
nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57E, _SET_CONTEXT_DMA_ILUT, _HANDLE, ctxDmaHandle));
|
||||
nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57E, _SET_CONTEXT_DMA_ILUT, _HANDLE, ctxDma));
|
||||
|
||||
nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_OFFSET_ILUT, 1);
|
||||
nvDmaSetEvoMethodData(pChannel, DRF_NUM(C57E, _SET_OFFSET_ILUT, _ORIGIN, offset));
|
||||
@@ -4392,8 +4607,9 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo,
|
||||
NvU32 hTaps, vTaps;
|
||||
NvBool scaling = FALSE;
|
||||
NVLutSurfaceEvoPtr pLutSurfaceEvo = NULL;
|
||||
NvU32 lutSize = NV_NUM_EVO_LUT_ENTRIES;
|
||||
NvU32 lutSize = NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES;
|
||||
NvBool isLutModeVss = FALSE;
|
||||
NvU32 ctxDma = 0;
|
||||
|
||||
NvU32 win = NV_EVO_CHANNEL_MASK_WINDOW_NUMBER(pChannel->channelMask);
|
||||
NvU32 head = pDevEvo->headForWindow[win];
|
||||
@@ -4402,12 +4618,6 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo,
|
||||
const NvU32 sd = (sdMask == 0) ? 0 : nv_ffs(sdMask) - 1;
|
||||
const NVDispHeadStateEvoRec *pHeadState = &pDevEvo->pDispEvo[sd]->headState[head];
|
||||
|
||||
// XXX HDR TODO: Handle other colorspaces
|
||||
// XXX HDR TODO: Enable custom input LUTs with HDR
|
||||
if (pHwState->colorSpace != NVKMS_INPUT_COLORSPACE_BT2100_PQ) {
|
||||
pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState);
|
||||
}
|
||||
|
||||
if (!EvoFlipC3Common(pDevEvo, pChannel, pHwState, updateState, head)) {
|
||||
ConfigureTmoLut(pDevEvo, pHwState, pChannel);
|
||||
return;
|
||||
@@ -4472,38 +4682,70 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo,
|
||||
// unless the surface being displayed is already FP16 to begin with.
|
||||
if ((format == NvKmsSurfaceMemoryFormatRF16GF16BF16AF16) ||
|
||||
(format == NvKmsSurfaceMemoryFormatRF16GF16BF16XF16) || bypassComposition) {
|
||||
// Assert that the colorspace is a linear encoding.
|
||||
nvAssert((pHwState->colorSpace == NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR) ||
|
||||
(pHwState->colorSpace == NVKMS_INPUT_COLORSPACE_NONE));
|
||||
pLutSurfaceEvo = NULL;
|
||||
} else if (!pLutSurfaceEvo) {
|
||||
NVEvoLutDataRec *pData = NULL;
|
||||
|
||||
pLutSurfaceEvo = pDevEvo->lut.defaultLut;
|
||||
pData = pLutSurfaceEvo->subDeviceAddress[sd];
|
||||
|
||||
nvAssert(pData);
|
||||
|
||||
(pHwState->colorSpace == NVKMS_INPUT_COLORSPACE_NONE) ||
|
||||
(pHwState->colorSpace == NVKMS_INPUT_COLORSPACE_REC709_LINEAR));
|
||||
ctxDma = 0;
|
||||
} else if (pHwState->colorSpace != NVKMS_INPUT_COLORSPACE_NONE) {
|
||||
switch (pHwState->colorSpace) {
|
||||
case NVKMS_INPUT_COLORSPACE_BT2100_PQ:
|
||||
EvoSetupPQEotfBaseLutC5(pData,
|
||||
&pDevEvo->lut.defaultBaseLUTState[sd],
|
||||
&lutSize, &isLutModeVss);
|
||||
ctxDma = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_SRGB]->surfaceDesc.ctxDmaHandle;
|
||||
lutSize = NV_LUT_VSS_HEADER_SIZE + PQ_EOTF_LUT_NUM_ENTRIES;
|
||||
isLutModeVss = TRUE;
|
||||
break;
|
||||
case NVKMS_INPUT_COLORSPACE_NONE:
|
||||
EvoSetupIdentityBaseLutC5(pData,
|
||||
&pDevEvo->lut.defaultBaseLUTState[sd],
|
||||
&lutSize, &isLutModeVss);
|
||||
case NVKMS_INPUT_COLORSPACE_REC709:
|
||||
// When the output is sRGB, We use sRGB degamma instead of
|
||||
// Rec709 degamma because Rec709 gamma-encoded inputs are
|
||||
// are designed to be compatible with sRGB in the sense
|
||||
// that a signal encoded using Rec709 has the correct
|
||||
// amount of gamma for displaying it properly in the
|
||||
// viewing environment of sRGB. As a result, we don't want
|
||||
// a situation where a Rec709 input is degammaed with
|
||||
// Rec709 and regammaed with sRGB, as that would alter the
|
||||
// signal's gamma. Instead, we apply a symmetric sRGB
|
||||
// degamma and sRGB regamma so they cancel each other out.
|
||||
// Therefore, given a gamma-encoded input signal, the
|
||||
// de/regamma process is purely for conversion to and from
|
||||
// linear space for the sake of linear processing
|
||||
// operations.
|
||||
ctxDma = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_SRGB]->surfaceDesc.ctxDmaHandle;
|
||||
lutSize = NV_LUT_VSS_HEADER_SIZE + SRGB_EOTF_LUT_NUM_ENTRIES;
|
||||
isLutModeVss = TRUE;
|
||||
break;
|
||||
// TODO(mtrost): add support for Rec709 EOTF LUT when the output
|
||||
// is not sRGB.
|
||||
case NVKMS_INPUT_COLORSPACE_SRGB:
|
||||
ctxDma = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_SRGB]->surfaceDesc.ctxDmaHandle;
|
||||
lutSize = NV_LUT_VSS_HEADER_SIZE + SRGB_EOTF_LUT_NUM_ENTRIES;
|
||||
isLutModeVss = TRUE;
|
||||
break;
|
||||
case NVKMS_INPUT_COLORSPACE_REC709_LINEAR:
|
||||
default: // XXX HDR TODO: Handle other colorspaces
|
||||
nvAssert(FALSE);
|
||||
EvoSetupIdentityBaseLutC5(pData,
|
||||
&pDevEvo->lut.defaultBaseLUTState[sd],
|
||||
&lutSize, &isLutModeVss);
|
||||
ctxDma = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_IDENTITY]->surfaceDesc.ctxDmaHandle;
|
||||
lutSize = NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES;
|
||||
isLutModeVss = FALSE;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
// Attempt to load a client-supplied custom ILUT since the client did
|
||||
// not specify an input colorspace.
|
||||
pLutSurfaceEvo = EvoGetLutSurface3(pDevEvo, pChannel, pHwState);
|
||||
|
||||
// Default to IDENTITY ILUT if the client does not specify an input
|
||||
// colorspace or a custom ILUT.
|
||||
if (pLutSurfaceEvo == NULL) {
|
||||
ctxDma = pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_IDENTITY]->surfaceDesc.ctxDmaHandle;
|
||||
lutSize = NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES;
|
||||
isLutModeVss = FALSE;
|
||||
} else {
|
||||
ctxDma = pLutSurfaceEvo->surfaceDesc.ctxDmaHandle;
|
||||
lutSize = NV_LUT_VSS_HEADER_SIZE + NV_NUM_EVO_LUT_ENTRIES;
|
||||
isLutModeVss = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
if (pLutSurfaceEvo) {
|
||||
if (ctxDma != 0) {
|
||||
const NvU32 origin = offsetof(NVEvoLutDataRec, base);
|
||||
|
||||
nvDmaSetStartEvoMethod(pChannel, NVC57E_SET_ILUT_CONTROL, 1);
|
||||
@@ -4515,9 +4757,9 @@ EvoFlipC5Common(NVDevEvoPtr pDevEvo,
|
||||
DRF_DEF(C57E, _SET_ILUT_CONTROL, _MODE, _DIRECT10)) |
|
||||
DRF_NUM(C57E, _SET_ILUT_CONTROL, _SIZE, lutSize));
|
||||
|
||||
SetILUTSurfaceAddress(pChannel, &pLutSurfaceEvo->surfaceDesc, origin);
|
||||
SetILUTSurfaceAddress(pChannel, ctxDma, origin);
|
||||
} else {
|
||||
SetILUTSurfaceAddress(pChannel, NULL /* pSurfaceDesc */, 0 /* offset */);
|
||||
SetILUTSurfaceAddress(pChannel, 0 /* ctxDmaHandle */, 0 /* offset */);
|
||||
}
|
||||
|
||||
ConfigureTmoLut(pDevEvo, pHwState, pChannel);
|
||||
@@ -5125,99 +5367,6 @@ static void EvoSetLUTContextDmaC3(const NVDispEvoRec *pDispEvo,
|
||||
nvPopEvoSubDevMask(pDevEvo);
|
||||
}
|
||||
|
||||
static void EvoSetupPQOetfOutputLutC5(NVEvoLutDataRec *pData,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss)
|
||||
{
|
||||
NvU32 lutDataStartingIndex = NV_LUT_VSS_HEADER_SIZE;
|
||||
NvU32 numOetfPQ512Entries = ARRAY_LEN(OetfPQ512Entries);
|
||||
NvU32 oetfTableIdx;
|
||||
NvU64 vssHead = 0;
|
||||
NvU32 lutEntryCounter = 0, i;
|
||||
|
||||
// Skip LUT data init if already done
|
||||
if (*lutState == NvKmsLUTStatePQ) {
|
||||
goto skipInit;
|
||||
}
|
||||
|
||||
// VSS Header
|
||||
for (lutEntryCounter = 0; lutEntryCounter < NV_LUT_VSS_HEADER_SIZE; lutEntryCounter++) {
|
||||
vssHead = 0;
|
||||
for (i = 0; ((i < 16) && (((lutEntryCounter * 16) + i) < ARRAY_LEN(OetfPQ512SegSizesLog2))); i++) {
|
||||
NvU64 temp = OetfPQ512SegSizesLog2[(lutEntryCounter * 16) + i];
|
||||
temp = temp << (i * 3);
|
||||
vssHead |= temp;
|
||||
}
|
||||
nvkms_memcpy(&(pData->output[lutEntryCounter]), &vssHead, sizeof(NVEvoLutEntryRec));
|
||||
}
|
||||
|
||||
for (oetfTableIdx = 0; oetfTableIdx < numOetfPQ512Entries; oetfTableIdx++) {
|
||||
pData->output[oetfTableIdx + lutDataStartingIndex].Red =
|
||||
pData->output[oetfTableIdx + lutDataStartingIndex].Green =
|
||||
pData->output[oetfTableIdx + lutDataStartingIndex].Blue =
|
||||
OetfPQ512Entries[oetfTableIdx];
|
||||
}
|
||||
|
||||
// Copy the last entry for interpolation
|
||||
pData->output[numOetfPQ512Entries + lutDataStartingIndex].Red =
|
||||
pData->output[numOetfPQ512Entries + lutDataStartingIndex - 1].Red;
|
||||
pData->output[numOetfPQ512Entries + lutDataStartingIndex].Green =
|
||||
pData->output[numOetfPQ512Entries + lutDataStartingIndex - 1].Green;
|
||||
pData->output[numOetfPQ512Entries + lutDataStartingIndex].Blue =
|
||||
pData->output[numOetfPQ512Entries + lutDataStartingIndex - 1].Blue;
|
||||
|
||||
skipInit:
|
||||
*lutState = NvKmsLUTStatePQ;
|
||||
*lutSize = numOetfPQ512Entries + 1;
|
||||
*isLutModeVss = TRUE;
|
||||
}
|
||||
|
||||
static void EvoSetupIdentityOutputLutC5(NVEvoLutDataRec *pData,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss)
|
||||
{
|
||||
NvU32 i;
|
||||
|
||||
// Skip LUT data init if already done
|
||||
if (*lutState == NvKmsLUTStateIdentity) {
|
||||
goto skipInit;
|
||||
}
|
||||
|
||||
ct_assert(NV_NUM_EVO_LUT_ENTRIES == 1025);
|
||||
|
||||
// nvdisplay 3 uses 16-bit fixed-point entries in the OLUT.
|
||||
for (i = 0; i < 1024; i++) {
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + i].Red =
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + i].Green =
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + i].Blue = (i << (16 - 10));
|
||||
}
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + 1024] =
|
||||
pData->output[NV_LUT_VSS_HEADER_SIZE + 1023];
|
||||
|
||||
skipInit:
|
||||
*lutState = NvKmsLUTStateIdentity;
|
||||
*lutSize = 1025;
|
||||
*isLutModeVss = FALSE;
|
||||
}
|
||||
|
||||
static void SetupHDROutputLUT(NVDevEvoPtr pDevEvo,
|
||||
const NVDispHeadStateEvoRec *pHeadState,
|
||||
NvU32 sd,
|
||||
enum NvKmsLUTState *lutState,
|
||||
NvU32 *lutSize,
|
||||
NvBool *isLutModeVss)
|
||||
{
|
||||
NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut;
|
||||
NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd];
|
||||
|
||||
// XXX HDR TODO: Support other transfer functions
|
||||
nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ);
|
||||
|
||||
EvoSetupPQOetfOutputLutC5(pData, lutState, lutSize, isLutModeVss);
|
||||
}
|
||||
|
||||
void nvSetupOutputLUT5(NVDevEvoPtr pDevEvo,
|
||||
const NVDispHeadStateEvoRec *pHeadState,
|
||||
const int head,
|
||||
@@ -5250,15 +5399,17 @@ void nvSetupOutputLUT5(NVDevEvoPtr pDevEvo,
|
||||
*disableOcsc0 = TRUE;
|
||||
} else if (!enableOutputLut) {
|
||||
/* Use the default OLUT if the client didn't provide one */
|
||||
*pSurfaceDesc = &pDevEvo->lut.defaultLut->surfaceDesc;
|
||||
*pSurfaceDesc = &pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_IDENTITY]->surfaceDesc;
|
||||
|
||||
// Setup default OLUT
|
||||
// Choose the appropriate OLUT based on NvKmsOutputColorSpace.
|
||||
for (sd = 0; sd < pDevEvo->numSubDevices; sd++) {
|
||||
if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) {
|
||||
SetupHDROutputLUT(pDevEvo, pHeadState, sd,
|
||||
&pDevEvo->lut.defaultOutputLUTState[sd],
|
||||
lutSize, isLutModeVss);
|
||||
// XXX HDR TODO: Support other transfer functions
|
||||
nvAssert(pHeadState->tf == NVKMS_OUTPUT_TF_PQ);
|
||||
|
||||
*isLutModeVss = TRUE;
|
||||
*lutSize = PQ_OETF_LUT_NUM_ENTRIES;
|
||||
*pSurfaceDesc = &pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_PQ]->surfaceDesc;
|
||||
*disableOcsc0 = TRUE;
|
||||
|
||||
/*
|
||||
@@ -5266,14 +5417,19 @@ void nvSetupOutputLUT5(NVDevEvoPtr pDevEvo,
|
||||
* XXX HDR TODO: Assumes input is in this range, SDR is not.
|
||||
*/
|
||||
*fpNormScale = 0xFFFFFFFF / 125;
|
||||
} else {
|
||||
NVLutSurfaceEvoPtr pLut = pDevEvo->lut.defaultLut;
|
||||
NVEvoLutDataRec *pData = pLut->subDeviceAddress[sd];
|
||||
} else if (pHeadState->outputColorSpace == NVKMS_OUTPUT_COLORSPACE_SRGB) {
|
||||
*isLutModeVss = TRUE;
|
||||
*lutSize = SRGB_OETF_LUT_NUM_ENTRIES;
|
||||
*pSurfaceDesc = &pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_SRGB]->surfaceDesc;
|
||||
|
||||
EvoSetupIdentityOutputLutC5(
|
||||
pData,
|
||||
&pDevEvo->lut.defaultOutputLUTState[sd],
|
||||
lutSize, isLutModeVss);
|
||||
// 0xFFFFFFFF / (100.0 / 80.0) which assumes a standard SDR luminance range.
|
||||
*fpNormScale = 0xcccccccc;
|
||||
} else {
|
||||
// If no output color space specified, or if the specified
|
||||
// color space is NONE, use Identity OLUT.
|
||||
*isLutModeVss = FALSE;
|
||||
*lutSize = NV_NUM_EVO_LUT_ENTRIES;
|
||||
*pSurfaceDesc = &pDevEvo->lut.gammaLUTs[NVKMS_GAMMA_LUT_IDENTITY]->surfaceDesc;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -5316,7 +5472,8 @@ static void EvoSetLUTContextDmaC5(const NVDispEvoRec *pDispEvo,
|
||||
NvU32 fpNormScale = 0xFFFFFFFF;
|
||||
|
||||
// XXX HDR TODO: Enable custom output LUTs with HDR
|
||||
if (pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) {
|
||||
if ((pHeadState->hdr.outputState == NVKMS_HDR_OUTPUT_STATE_HDR) ||
|
||||
(pHeadState->outputColorSpace != NVKMS_OUTPUT_COLORSPACE_NONE)) {
|
||||
enableOutputLut = FALSE;
|
||||
}
|
||||
|
||||
|
||||
@@ -27,6 +27,7 @@
|
||||
#include "nvkms-dma.h"
|
||||
#include "nvkms-utils.h"
|
||||
#include "nvos.h"
|
||||
#include "nvkms-softfloat.h"
|
||||
|
||||
#include <class/cl0040.h> /* NV01_MEMORY_LOCAL_USER */
|
||||
|
||||
@@ -367,7 +368,7 @@ void nvUnrefTmoLutSurfacesEvo(NVDevEvoPtr pDevEvo,
|
||||
NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo)
|
||||
{
|
||||
NVDispEvoPtr pDispEvo;
|
||||
NvU32 apiHead, dispIndex, i, sd;
|
||||
NvU32 apiHead, dispIndex, i;
|
||||
|
||||
for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) {
|
||||
for (i = 0; i < ARRAY_LEN(pDevEvo->lut.apiHead[apiHead].LUT); i++) {
|
||||
@@ -387,22 +388,18 @@ NvBool nvAllocLutSurfacesEvo(NVDevEvoPtr pDevEvo)
|
||||
}
|
||||
}
|
||||
|
||||
if (pDevEvo->hal->caps.needDefaultLutSurface) {
|
||||
pDevEvo->lut.defaultLut = AllocLutSurfaceEvo(pDevEvo);
|
||||
if (pDevEvo->lut.defaultLut == NULL) {
|
||||
// Allocate memory for the predefined LUTs.
|
||||
for (i = 0; i < NVKMS_GAMMA_LUT_LAST; i++) {
|
||||
pDevEvo->lut.gammaLUTs[i] = AllocLutSurfaceEvo(pDevEvo);
|
||||
if (pDevEvo->lut.gammaLUTs[i] == NULL) {
|
||||
nvFreeLutSurfacesEvo(pDevEvo);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
for (sd = 0; sd < NVKMS_MAX_SUBDEVICES; sd++) {
|
||||
pDevEvo->lut.defaultBaseLUTState[sd] =
|
||||
pDevEvo->lut.defaultOutputLUTState[sd] =
|
||||
NvKmsLUTStateUninitialized;
|
||||
}
|
||||
|
||||
pDevEvo->hal->InitDefaultLut(pDevEvo);
|
||||
}
|
||||
|
||||
// Initialize the predefined LUTs.
|
||||
pDevEvo->hal->InitDefaultLut(pDevEvo);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@@ -432,9 +429,12 @@ void nvFreeLutSurfacesEvo(NVDevEvoPtr pDevEvo)
|
||||
}
|
||||
}
|
||||
|
||||
if (pDevEvo->lut.defaultLut != NULL) {
|
||||
FreeLutSurfaceEvo(pDevEvo->lut.defaultLut);
|
||||
pDevEvo->lut.defaultLut = NULL;
|
||||
// Free any previously-allocated predefined gamma LUTs.
|
||||
for (i = 0; i < NVKMS_GAMMA_LUT_LAST; i++) {
|
||||
if (pDevEvo->lut.gammaLUTs[i] != NULL) {
|
||||
FreeLutSurfaceEvo(pDevEvo->lut.gammaLUTs[i]);
|
||||
pDevEvo->lut.gammaLUTs[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
for (apiHead = 0; apiHead < pDevEvo->numApiHeads; apiHead++) {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -443,14 +443,14 @@ static void AdjustHwModeTimingsForVrr(const NVDispEvoRec *pDispEvo,
|
||||
|
||||
/*
|
||||
* Return whether headSurface is allowed. But, only honor the requestor's
|
||||
* setting if they are the modeset owner. Otherwise, inherit the cached value
|
||||
* in pDevEvo.
|
||||
* setting if they have modeset owner permission. Otherwise, inherit the cached
|
||||
* value in pDevEvo.
|
||||
*/
|
||||
NvBool nvGetAllowHeadSurfaceInNvKms(const NVDevEvoRec *pDevEvo,
|
||||
const struct NvKmsPerOpenDev *pOpenDev,
|
||||
const struct NvKmsSetModeRequest *pRequest)
|
||||
{
|
||||
if (pOpenDev == pDevEvo->modesetOwner || pOpenDev == pDevEvo->pNvKmsOpenDev) {
|
||||
if (nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
return pRequest->allowHeadSurfaceInNvKms;
|
||||
}
|
||||
|
||||
@@ -1172,6 +1172,18 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo,
|
||||
pProposedApiHead->lut.input.specified = FALSE;
|
||||
}
|
||||
|
||||
if (pRequestHead->outputColorSpace.specified) {
|
||||
pProposedApiHead->outputColorSpace =
|
||||
pRequestHead->outputColorSpace.val;
|
||||
|
||||
// A specified output color space takes precedence over a
|
||||
// specified custom OLUT. Setting the lut.output as follows
|
||||
// will cause nvEvoSetLut() to set the relevant parameter to
|
||||
// output disabled.
|
||||
pProposedApiHead->lut.output.specified = TRUE;
|
||||
pProposedApiHead->lut.output.enabled = FALSE;
|
||||
}
|
||||
|
||||
if (pRequestHead->flip.viewPortIn.specified) {
|
||||
pProposedApiHead->viewPortPointIn =
|
||||
pRequestHead->flip.viewPortIn.point;
|
||||
@@ -2458,6 +2470,7 @@ ApplyProposedModeSetHwStateOneHeadPreUpdate(
|
||||
nvEvoColorSpaceBpcToPixelDepth(pProposedApiHead->attributes.colorSpace,
|
||||
pProposedApiHead->attributes.colorBpc);
|
||||
pHeadState->audio = pProposedHead->audio;
|
||||
pHeadState->outputColorSpace = pProposedApiHead->outputColorSpace;
|
||||
|
||||
/* Update current LUT to hardware */
|
||||
nvEvoSetLUTContextDma(pDispEvo, head, updateState);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -784,7 +784,8 @@ fail:
|
||||
*/
|
||||
static NvBool ValidateNvKmsPermissions(
|
||||
const NVDevEvoRec *pDevEvo,
|
||||
const struct NvKmsPermissions *pPermissions)
|
||||
const struct NvKmsPermissions *pPermissions,
|
||||
enum NvKmsClientType clientType)
|
||||
{
|
||||
if (pPermissions->type == NV_KMS_PERMISSIONS_TYPE_FLIPPING) {
|
||||
NvU32 d, h;
|
||||
@@ -845,6 +846,13 @@ static NvBool ValidateNvKmsPermissions(
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (pPermissions->type == NV_KMS_PERMISSIONS_TYPE_SUB_OWNER) {
|
||||
|
||||
/* Only kapi uses this permission type, so disallow it from userspace */
|
||||
if (clientType != NVKMS_CLIENT_KERNEL_SPACE) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
} else {
|
||||
return FALSE;
|
||||
}
|
||||
@@ -888,6 +896,16 @@ static void AssignFullNvKmsModesetPermissions(
|
||||
}
|
||||
}
|
||||
|
||||
static void AssignFullNvKmsPermissions(
|
||||
struct NvKmsPerOpenDev *pOpenDev
|
||||
)
|
||||
{
|
||||
NVDevEvoPtr pDevEvo = pOpenDev->pDevEvo;
|
||||
|
||||
AssignFullNvKmsFlipPermissions(pDevEvo, &pOpenDev->flipPermissions);
|
||||
AssignFullNvKmsModesetPermissions(pDevEvo, &pOpenDev->modesetPermissions);
|
||||
}
|
||||
|
||||
/*!
|
||||
* Set the modeset owner to pOpenDev
|
||||
*
|
||||
@@ -917,9 +935,7 @@ static NvBool GrabModesetOwnership(struct NvKmsPerOpenDev *pOpenDev)
|
||||
pDevEvo->modesetOwner = pOpenDev;
|
||||
pDevEvo->modesetOwnerChanged = TRUE;
|
||||
|
||||
AssignFullNvKmsFlipPermissions(pDevEvo, &pOpenDev->flipPermissions);
|
||||
AssignFullNvKmsModesetPermissions(pDevEvo, &pOpenDev->modesetPermissions);
|
||||
|
||||
AssignFullNvKmsPermissions(pOpenDev);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@@ -991,7 +1007,7 @@ static NvBool RemoveModesetPermissions(struct NvKmsModesetPermissions *pModeset,
|
||||
*/
|
||||
static void RevokePermissionsInternal(
|
||||
const NvU32 typeBitmask,
|
||||
const NVDevEvoRec *pDevEvo,
|
||||
NVDevEvoRec *pDevEvo,
|
||||
const struct NvKmsPerOpenDev *pOpenDevExclude)
|
||||
{
|
||||
struct NvKmsPerOpen *pOpen;
|
||||
@@ -1019,6 +1035,19 @@ static void RevokePermissionsInternal(
|
||||
continue;
|
||||
}
|
||||
|
||||
if (pOpenDev == pDevEvo->modesetSubOwner &&
|
||||
(typeBitmask & NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER))) {
|
||||
pDevEvo->modesetSubOwner = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Clients with sub-owner permission (or better) don't get flipping
|
||||
* or modeset permission revoked.
|
||||
*/
|
||||
if (nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (typeBitmask & NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING)) {
|
||||
nvkms_memset(&pOpenDev->flipPermissions, 0,
|
||||
sizeof(pOpenDev->flipPermissions));
|
||||
@@ -1075,7 +1104,8 @@ static NvBool ReleaseModesetOwnership(struct NvKmsPerOpenDev *pOpenDev)
|
||||
|
||||
RestoreConsole(pDevEvo);
|
||||
RevokePermissionsInternal(NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING) |
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET),
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET) |
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER),
|
||||
pDevEvo, NULL /* pOpenDevExclude */);
|
||||
return TRUE;
|
||||
}
|
||||
@@ -1173,10 +1203,7 @@ struct NvKmsPerOpenDev *nvAllocPerOpenDev(struct NvKmsPerOpen *pOpen,
|
||||
|
||||
pOpenDev->isPrivileged = isPrivileged;
|
||||
if (pOpenDev->isPrivileged) {
|
||||
AssignFullNvKmsFlipPermissions(pDevEvo,
|
||||
&pOpenDev->flipPermissions);
|
||||
AssignFullNvKmsModesetPermissions(pOpenDev->pDevEvo,
|
||||
&pOpenDev->modesetPermissions);
|
||||
AssignFullNvKmsPermissions(pOpenDev);
|
||||
}
|
||||
|
||||
if (!nvEvoInitApiHandles(&pOpenDev->deferredRequestFifoHandles, 4)) {
|
||||
@@ -1513,6 +1540,11 @@ static void FreeDeviceReference(struct NvKmsPerOpen *pOpen,
|
||||
ReleaseModesetOwnership(pOpenDev);
|
||||
|
||||
nvAssert(pOpenDev->pDevEvo->modesetOwner != pOpenDev);
|
||||
|
||||
// If this pOpenDev is the modeset sub-owner, implicitly release it.
|
||||
if (pOpenDev->pDevEvo->modesetSubOwner == pOpenDev) {
|
||||
pOpenDev->pDevEvo->modesetSubOwner = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
nvFreePerOpenDev(pOpen, pOpenDev);
|
||||
@@ -1753,6 +1785,36 @@ static NvBool QueryDpyDynamicData(struct NvKmsPerOpen *pOpen,
|
||||
return nvDpyGetDynamicData(pDpyEvo, pParams);
|
||||
}
|
||||
|
||||
/*!
|
||||
* Get the base address and size of the VT framebuffer memory
|
||||
*/
|
||||
static NvBool QueryVtFbData(struct NvKmsPerOpen *pOpen,
|
||||
void *pParamsVoid)
|
||||
{
|
||||
struct NvKmsQueryVtFbDataParams *pParams = pParamsVoid;
|
||||
struct NvKmsPerOpenDev *pOpenDev;
|
||||
NV0080_CTRL_OS_UNIX_VT_GET_FB_INFO_PARAMS *vtFbInfo;
|
||||
|
||||
if (pOpen->clientType != NVKMS_CLIENT_KERNEL_SPACE) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pOpenDev = GetPerOpenDev(pOpen, pParams->request.deviceHandle);
|
||||
|
||||
if (pOpenDev == NULL ||
|
||||
!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
vtFbInfo = &pOpenDev->pDevEvo->vtFbInfo;
|
||||
|
||||
nvkms_memset(&pParams->reply, 0, sizeof(pParams->reply));
|
||||
pParams->reply.baseAddress = vtFbInfo->baseAddress;
|
||||
pParams->reply.size = vtFbInfo->size;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* Store a copy of the user's infoString pointer, so we can copy out to it when
|
||||
* we're done. */
|
||||
struct InfoStringExtraUserStateCommon
|
||||
@@ -2380,9 +2442,9 @@ static NvBool IdleBaseChannel(struct NvKmsPerOpen *pOpen,
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Only the modesetOwner can idle base. */
|
||||
/* Only a modeset owner can idle base. */
|
||||
|
||||
if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) {
|
||||
if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
@@ -3080,14 +3142,15 @@ static NvBool GrantPermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid)
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Only the modesetOwner can grant permissions. */
|
||||
/* Only a modeset owner can grant permissions. */
|
||||
|
||||
if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) {
|
||||
if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (!ValidateNvKmsPermissions(pOpenDev->pDevEvo,
|
||||
&pParams->request.permissions)) {
|
||||
&pParams->request.permissions,
|
||||
pOpen->clientType)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
@@ -3165,6 +3228,16 @@ static NvBool AcquirePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid)
|
||||
|
||||
pParams->reply.permissions.modeset = pOpenDev->modesetPermissions;
|
||||
|
||||
} else if (type == NV_KMS_PERMISSIONS_TYPE_SUB_OWNER) {
|
||||
|
||||
if (pOpenDev->pDevEvo->modesetSubOwner != NULL) {
|
||||
/* There can be only one sub-owner */
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pOpenDev->pDevEvo->modesetSubOwner = pOpenDev;
|
||||
AssignFullNvKmsPermissions(pOpenDev);
|
||||
|
||||
} else {
|
||||
/*
|
||||
* GrantPermissions() should ensure that
|
||||
@@ -3267,23 +3340,45 @@ static NvBool RevokePermissions(struct NvKmsPerOpen *pOpen, void *pParamsVoid)
|
||||
GetPerOpenDev(pOpen, pParams->request.deviceHandle);
|
||||
const NvU32 validBitmask =
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_FLIPPING) |
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET);
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_MODESET) |
|
||||
NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER);
|
||||
|
||||
if (pOpenDev == NULL) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Only the modeset owner can revoke permissions. */
|
||||
if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Reject invalid bitmasks. */
|
||||
|
||||
if ((pParams->request.permissionsTypeBitmask & ~validBitmask) != 0) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if ((pParams->request.permissionsTypeBitmask & NVBIT(NV_KMS_PERMISSIONS_TYPE_SUB_OWNER)) != 0) {
|
||||
if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) {
|
||||
/* Only the modeset owner can revoke sub-owner permissions. */
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/*
|
||||
* When revoking ownership permissions, shut down all heads.
|
||||
*
|
||||
* This is necessary to keep the state of nvidia-drm in sync with NVKMS.
|
||||
* Otherwise, an NVKMS client can leave heads enabled when handing off
|
||||
* control of the device back to nvidia-drm, and nvidia-drm's flip queue
|
||||
* handling will get out of sync because it thinks all heads are
|
||||
* disabled and does not expect flip events on those heads.
|
||||
*/
|
||||
nvShutDownApiHeads(pOpenDev->pDevEvo, NULL /* pTestFunc */);
|
||||
}
|
||||
|
||||
/*
|
||||
* Only a client with sub-owner permissions (or better) can revoke other
|
||||
* kinds of permissions.
|
||||
*/
|
||||
if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (pParams->request.permissionsTypeBitmask > 0) {
|
||||
// Old behavior, revoke all permissions of a type.
|
||||
|
||||
@@ -3410,8 +3505,8 @@ static NvBool QueryDpyCRC32(struct NvKmsPerOpen *pOpen,
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
if (pOpenDev->pDevEvo->modesetOwner != pOpenDev) {
|
||||
// Only the current owner can query CRC32 values.
|
||||
if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(pOpenDev)) {
|
||||
// Only a current owner can query CRC32 values.
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
@@ -3452,15 +3547,13 @@ static NvBool SwitchMux(
|
||||
struct NvKmsSwitchMuxParams *pParams = pParamsVoid;
|
||||
const struct NvKmsSwitchMuxRequest *r = &pParams->request;
|
||||
NVDpyEvoPtr pDpyEvo;
|
||||
NVDevEvoPtr pDevEvo;
|
||||
|
||||
pDpyEvo = GetPerOpenDpy(pOpen, r->deviceHandle, r->dispHandle, r->dpyId);
|
||||
if (pDpyEvo == NULL) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pDevEvo = pDpyEvo->pDispEvo->pDevEvo;
|
||||
if (pDevEvo->modesetOwner != GetPerOpenDev(pOpen, r->deviceHandle)) {
|
||||
if (!nvKmsOpenDevHasSubOwnerPermissionOrBetter(GetPerOpenDev(pOpen, r->deviceHandle))) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
@@ -3956,6 +4049,7 @@ NvBool nvKmsIoctl(
|
||||
ENTRY(NVKMS_IOCTL_QUERY_CONNECTOR_DYNAMIC_DATA, QueryConnectorDynamicData),
|
||||
ENTRY(NVKMS_IOCTL_QUERY_DPY_STATIC_DATA, QueryDpyStaticData),
|
||||
ENTRY(NVKMS_IOCTL_QUERY_DPY_DYNAMIC_DATA, QueryDpyDynamicData),
|
||||
ENTRY(NVKMS_IOCTL_QUERY_VT_FB_DATA, QueryVtFbData),
|
||||
ENTRY_CUSTOM_USER(NVKMS_IOCTL_VALIDATE_MODE_INDEX, ValidateModeIndex),
|
||||
ENTRY_CUSTOM_USER(NVKMS_IOCTL_VALIDATE_MODE, ValidateMode),
|
||||
ENTRY_CUSTOM_USER(NVKMS_IOCTL_SET_MODE, SetMode),
|
||||
@@ -4232,6 +4326,7 @@ static const char *ProcFsPermissionsTypeString(
|
||||
switch (permissionsType) {
|
||||
case NV_KMS_PERMISSIONS_TYPE_FLIPPING: return "flipping";
|
||||
case NV_KMS_PERMISSIONS_TYPE_MODESET: return "modeset";
|
||||
case NV_KMS_PERMISSIONS_TYPE_SUB_OWNER:return "sub-owner";
|
||||
}
|
||||
|
||||
return "unknown";
|
||||
@@ -5532,3 +5627,10 @@ NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness)
|
||||
|
||||
return status == NV_OK;
|
||||
}
|
||||
|
||||
NvBool nvKmsOpenDevHasSubOwnerPermissionOrBetter(const struct NvKmsPerOpenDev *pOpenDev)
|
||||
{
|
||||
return pOpenDev->isPrivileged ||
|
||||
pOpenDev->pDevEvo->modesetOwner == pOpenDev ||
|
||||
pOpenDev->pDevEvo->modesetSubOwner == pOpenDev;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -162,7 +162,7 @@ NvBool NV_API_CALL os_is_vgx_hyper (void);
|
||||
NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32);
|
||||
NvBool NV_API_CALL os_is_grid_supported (void);
|
||||
NvU32 NV_API_CALL os_get_grid_csp_support (void);
|
||||
void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64, NvU64);
|
||||
void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *, NvU64, NvU64);
|
||||
void NV_API_CALL os_bug_check (NvU32, const char *);
|
||||
NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32);
|
||||
NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -4351,12 +4351,10 @@ NvBool rm_get_uefi_console_status(
|
||||
// UEFI console check the fbBaseAddress: if it was set up by the EFI GOP
|
||||
// driver, it will point into BAR1 (FB); if it was set up by the VBIOS,
|
||||
// it will point to BAR2 + 16MB.
|
||||
os_get_screen_info(&fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch,
|
||||
os_get_screen_info(&fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize,
|
||||
nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
|
||||
nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);
|
||||
|
||||
fbSize = (NvU64)fbHeight * (NvU64)fbPitch;
|
||||
|
||||
bConsoleDevice = (fbSize != 0);
|
||||
|
||||
return bConsoleDevice;
|
||||
@@ -4377,12 +4375,10 @@ NvU64 rm_get_uefi_console_size(
|
||||
// UEFI console check the fbBaseAddress: if it was set up by the EFI GOP
|
||||
// driver, it will point into BAR1 (FB); if it was set up by the VBIOS,
|
||||
// it will point to BAR2 + 16MB.
|
||||
os_get_screen_info(pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch,
|
||||
os_get_screen_info(pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize,
|
||||
nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
|
||||
nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);
|
||||
|
||||
fbSize = (NvU64)fbHeight * (NvU64)fbPitch;
|
||||
|
||||
return fbSize;
|
||||
}
|
||||
|
||||
|
||||
@@ -71,7 +71,7 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL
|
||||
|
||||
if (RmDisplayConsoleMemDescPresent(pGpu) && bContinue)
|
||||
{
|
||||
NvU64 baseAddr;
|
||||
NvU64 baseAddr, size;
|
||||
NvU32 width, height, depth, pitch;
|
||||
|
||||
// There should only be one.
|
||||
@@ -80,10 +80,12 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL
|
||||
pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu);
|
||||
|
||||
// Console is either mapped to BAR1 or BAR2 + 16 MB
|
||||
os_get_screen_info(&baseAddr, &width, &height, &depth, &pitch,
|
||||
os_get_screen_info(&baseAddr, &width, &height, &depth, &pitch, &size,
|
||||
nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
|
||||
nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);
|
||||
|
||||
pParams->baseAddress = baseAddr;
|
||||
pParams->size = size;
|
||||
pParams->width = (NvU16)width;
|
||||
pParams->height = (NvU16)height;
|
||||
pParams->depth = (NvU16)depth;
|
||||
|
||||
@@ -334,8 +334,8 @@ void dceclientHandleAsyncRpcCallback
|
||||
NV_STATUS nvStatus = NV_OK;
|
||||
|
||||
// Get the notification list that contains this event.
|
||||
NV_ASSERT(CliGetEventInfo(rpc_params->hClient,
|
||||
rpc_params->hEvent, &pEvent));
|
||||
NV_CHECK_OR_RETURN_VOID(LEVEL_ERROR, CliGetEventInfo(rpc_params->hClient,
|
||||
rpc_params->hEvent, &pEvent));
|
||||
|
||||
if (pEvent->pNotifierShare != NULL)
|
||||
pNotifyList = pEvent->pNotifierShare->pEventList;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
NVIDIA_VERSION = 540.3.2
|
||||
NVIDIA_VERSION = 540.4.0
|
||||
|
||||
# This file.
|
||||
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
||||
|
||||
Reference in New Issue
Block a user