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git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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osi: mgbe: support for get hw features
Bug 200565647 Change-Id: I3599f3606254bf70a8b4d48da0497f0c70c89ead Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
This commit is contained in:
Bhadram Varka
@@ -3111,6 +3111,145 @@ static void mgbe_configure_eee(struct osi_core_priv_data *osi_core,
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}
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}
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static int mgbe_get_hw_features(struct osi_core_priv_data *osi_core,
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struct osi_hw_features *hw_feat)
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{
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unsigned char *base = (unsigned char *)osi_core->base;
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unsigned int mac_hfr0 = 0;
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unsigned int mac_hfr1 = 0;
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unsigned int mac_hfr2 = 0;
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unsigned int mac_hfr3 = 0;
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mac_hfr0 = osi_readl(base + MGBE_MAC_HFR0);
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mac_hfr1 = osi_readl(base + MGBE_MAC_HFR1);
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mac_hfr2 = osi_readl(base + MGBE_MAC_HFR2);
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mac_hfr3 = osi_readl(base + MGBE_MAC_HFR3);
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hw_feat->rgmii_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_RGMIISEL_SHIFT) &
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MGBE_MAC_HFR0_RGMIISEL_MASK);
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hw_feat->gmii_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_GMIISEL_SHIFT) &
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MGBE_MAC_HFR0_GMIISEL_MASK);
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hw_feat->rmii_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_RMIISEL_SHIFT) &
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MGBE_MAC_HFR0_RMIISEL_MASK);
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hw_feat->hd_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_HDSEL_SHIFT) &
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MGBE_MAC_HFR0_HDSEL_MASK);
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hw_feat->vlan_hash_en = ((mac_hfr0 >> MGBE_MAC_HFR0_VLHASH_SHIFT) &
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MGBE_MAC_HFR0_VLHASH_MASK);
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hw_feat->sma_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_SMASEL_SHIFT) &
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MGBE_MAC_HFR0_SMASEL_MASK);
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hw_feat->rwk_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_RWKSEL_SHIFT) &
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MGBE_MAC_HFR0_RWKSEL_MASK);
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hw_feat->mgk_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_MGKSEL_SHIFT) &
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MGBE_MAC_HFR0_MGKSEL_MASK);
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hw_feat->mmc_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_MMCSEL_SHIFT) &
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MGBE_MAC_HFR0_MMCSEL_MASK);
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hw_feat->arp_offld_en = ((mac_hfr0 >> MGBE_MAC_HFR0_ARPOFFLDEN_SHIFT) &
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MGBE_MAC_HFR0_ARPOFFLDEN_MASK);
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hw_feat->rav_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_RAVSEL_SHIFT) &
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MGBE_MAC_HFR0_RAVSEL_MASK);
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hw_feat->av_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_AVSEL_SHIFT) &
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MGBE_MAC_HFR0_AVSEL_MASK);
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hw_feat->ts_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_TSSSEL_SHIFT) &
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MGBE_MAC_HFR0_TSSSEL_MASK);
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hw_feat->eee_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_EEESEL_SHIFT) &
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MGBE_MAC_HFR0_EEESEL_MASK);
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hw_feat->tx_coe_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_TXCOESEL_SHIFT) &
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MGBE_MAC_HFR0_TXCOESEL_MASK);
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hw_feat->rx_coe_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_RXCOESEL_SHIFT) &
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MGBE_MAC_HFR0_RXCOESEL_MASK);
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hw_feat->mac_addr_sel =
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((mac_hfr0 >> MGBE_MAC_HFR0_ADDMACADRSEL_SHIFT) &
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MGBE_MAC_HFR0_ADDMACADRSEL_MASK);
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hw_feat->act_phy_sel = ((mac_hfr0 >> MGBE_MAC_HFR0_PHYSEL_SHIFT) &
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MGBE_MAC_HFR0_PHYSEL_MASK);
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hw_feat->tsstssel = ((mac_hfr0 >> MGBE_MAC_HFR0_TSSTSSEL_SHIFT) &
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MGBE_MAC_HFR0_TSSTSSEL_MASK);
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hw_feat->sa_vlan_ins = ((mac_hfr0 >> MGBE_MAC_HFR0_SAVLANINS_SHIFT) &
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MGBE_MAC_HFR0_SAVLANINS_SHIFT);
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hw_feat->vxn = ((mac_hfr0 >> MGBE_MAC_HFR0_VXN_SHIFT) &
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MGBE_MAC_HFR0_VXN_MASK);
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hw_feat->ediffc = ((mac_hfr0 >> MGBE_MAC_HFR0_EDIFFC_SHIFT) &
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MGBE_MAC_HFR0_EDIFFC_MASK);
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hw_feat->edma = ((mac_hfr0 >> MGBE_MAC_HFR0_EDMA_SHIFT) &
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MGBE_MAC_HFR0_EDMA_MASK);
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hw_feat->rx_fifo_size = ((mac_hfr1 >> MGBE_MAC_HFR1_RXFIFOSIZE_SHIFT) &
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MGBE_MAC_HFR1_RXFIFOSIZE_MASK);
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hw_feat->pfc_en = ((mac_hfr1 >> MGBE_MAC_HFR1_PFCEN_SHIFT) &
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MGBE_MAC_HFR1_PFCEN_MASK);
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hw_feat->tx_fifo_size = ((mac_hfr1 >> MGBE_MAC_HFR1_TXFIFOSIZE_SHIFT) &
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MGBE_MAC_HFR1_TXFIFOSIZE_MASK);
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hw_feat->ost_en = ((mac_hfr1 >> MGBE_MAC_HFR1_OSTEN_SHIFT) &
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MGBE_MAC_HFR1_OSTEN_MASK);
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hw_feat->pto_en = ((mac_hfr1 >> MGBE_MAC_HFR1_PTOEN_SHIFT) &
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MGBE_MAC_HFR1_PTOEN_MASK);
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hw_feat->adv_ts_hword = ((mac_hfr1 >> MGBE_MAC_HFR1_ADVTHWORD_SHIFT) &
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MGBE_MAC_HFR1_ADVTHWORD_MASK);
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hw_feat->addr_64 = ((mac_hfr1 >> MGBE_MAC_HFR1_ADDR64_SHIFT) &
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MGBE_MAC_HFR1_ADDR64_MASK);
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hw_feat->dcb_en = ((mac_hfr1 >> MGBE_MAC_HFR1_DCBEN_SHIFT) &
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MGBE_MAC_HFR1_DCBEN_MASK);
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hw_feat->sph_en = ((mac_hfr1 >> MGBE_MAC_HFR1_SPHEN_SHIFT) &
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MGBE_MAC_HFR1_SPHEN_MASK);
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hw_feat->tso_en = ((mac_hfr1 >> MGBE_MAC_HFR1_TSOEN_SHIFT) &
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MGBE_MAC_HFR1_TSOEN_MASK);
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hw_feat->dma_debug_gen = ((mac_hfr1 >> MGBE_MAC_HFR1_DBGMEMA_SHIFT) &
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MGBE_MAC_HFR1_DBGMEMA_MASK);
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hw_feat->rss_en = ((mac_hfr1 >> MGBE_MAC_HFR1_RSSEN_SHIFT) &
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MGBE_MAC_HFR1_RSSEN_MASK);
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hw_feat->num_tc = ((mac_hfr1 >> MGBE_MAC_HFR1_NUMTC_SHIFT) &
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MGBE_MAC_HFR1_NUMTC_MASK);
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hw_feat->hash_tbl_sz = ((mac_hfr1 >> MGBE_MAC_HFR1_HASHTBLSZ_SHIFT) &
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MGBE_MAC_HFR1_HASHTBLSZ_MASK);
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hw_feat->l3l4_filter_num = ((mac_hfr1 >> MGBE_MAC_HFR1_L3L4FNUM_SHIFT) &
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MGBE_MAC_HFR1_L3L4FNUM_MASK);
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hw_feat->rx_q_cnt = ((mac_hfr2 >> MGBE_MAC_HFR2_RXQCNT_SHIFT) &
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MGBE_MAC_HFR2_RXQCNT_MASK);
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hw_feat->tx_q_cnt = ((mac_hfr2 >> MGBE_MAC_HFR2_TXQCNT_SHIFT) &
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MGBE_MAC_HFR2_TXQCNT_MASK);
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hw_feat->rx_ch_cnt = ((mac_hfr2 >> MGBE_MAC_HFR2_RXCHCNT_SHIFT) &
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MGBE_MAC_HFR2_RXCHCNT_MASK);
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hw_feat->tx_ch_cnt = ((mac_hfr2 >> MGBE_MAC_HFR2_TXCHCNT_SHIFT) &
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MGBE_MAC_HFR2_TXCHCNT_MASK);
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hw_feat->pps_out_num = ((mac_hfr2 >> MGBE_MAC_HFR2_PPSOUTNUM_SHIFT) &
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MGBE_MAC_HFR2_PPSOUTNUM_MASK);
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hw_feat->aux_snap_num = ((mac_hfr2 >> MGBE_MAC_HFR2_AUXSNAPNUM_SHIFT) &
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MGBE_MAC_HFR2_AUXSNAPNUM_MASK);
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hw_feat->num_vlan_filters = ((mac_hfr3 >> MGBE_MAC_HFR3_NRVF_SHIFT) &
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MGBE_MAC_HFR3_NRVF_MASK);
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hw_feat->frp_sel = ((mac_hfr3 >> MGBE_MAC_HFR3_FRPSEL_SHIFT) &
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MGBE_MAC_HFR3_FRPSEL_MASK);
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hw_feat->cbti_sel = ((mac_hfr3 >> MGBE_MAC_HFR3_CBTISEL_SHIFT) &
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MGBE_MAC_HFR3_CBTISEL_MASK);
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hw_feat->num_frp_pipes = ((mac_hfr3 >> MGBE_MAC_HFR3_FRPPIPE_SHIFT) &
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MGBE_MAC_HFR3_FRPPIPE_MASK);
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hw_feat->ost_over_udp = ((mac_hfr3 >> MGBE_MAC_HFR3_POUOST_SHIFT) &
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MGBE_MAC_HFR3_POUOST_MASK);
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hw_feat->max_frp_bytes = ((mac_hfr3 >> MGBE_MAC_HFR3_FRPPB_SHIFT) &
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MGBE_MAC_HFR3_FRPPB_MASK);
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hw_feat->max_frp_entries = ((mac_hfr3 >> MGBE_MAC_HFR3_FRPES_SHIFT) &
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MGBE_MAC_HFR3_FRPES_MASK);
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hw_feat->double_vlan_en = ((mac_hfr3 >> MGBE_MAC_HFR3_DVLAN_SHIFT) &
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MGBE_MAC_HFR3_DVLAN_MASK);
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hw_feat->auto_safety_pkg = ((mac_hfr3 >> MGBE_MAC_HFR3_ASP_SHIFT) &
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MGBE_MAC_HFR3_ASP_MASK);
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hw_feat->tts_fifo_depth = ((mac_hfr3 >> MGBE_MAC_HFR3_TTSFD_SHIFT) &
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MGBE_MAC_HFR3_TTSFD_MASK);
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hw_feat->est_sel = ((mac_hfr3 >> MGBE_MAC_HFR3_ESTSEL_SHIFT) &
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MGBE_MAC_HFR3_ESTSEL_MASK);
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hw_feat->gcl_depth = ((mac_hfr3 >> MGBE_MAC_HFR3_GCLDEP_SHIFT) &
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MGBE_MAC_HFR3_GCLDEP_MASK);
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hw_feat->gcl_width = ((mac_hfr3 >> MGBE_MAC_HFR3_GCLWID_SHIFT) &
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MGBE_MAC_HFR3_GCLWID_MASK);
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hw_feat->fpe_sel = ((mac_hfr3 >> MGBE_MAC_HFR3_FPESEL_SHIFT) &
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MGBE_MAC_HFR3_FPESEL_MASK);
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hw_feat->tbs_sel = ((mac_hfr3 >> MGBE_MAC_HFR3_TBSSEL_SHIFT) &
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MGBE_MAC_HFR3_TBSSEL_MASK);
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hw_feat->num_tbs_ch = ((mac_hfr3 >> MGBE_MAC_HFR3_TBS_CH_SHIFT) &
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MGBE_MAC_HFR3_TBS_CH_MASK);
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return 0;
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}
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/**
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* @brief mgbe_init_core_ops - Initialize MGBE MAC core operations
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*/
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@@ -3163,4 +3302,5 @@ void mgbe_init_core_ops(struct core_ops *ops)
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ops->read_mmc = mgbe_read_mmc;
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ops->reset_mmc = mgbe_reset_mmc;
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ops->configure_eee = mgbe_configure_eee;
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ops->get_hw_features = mgbe_get_hw_features;
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};
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@@ -527,4 +527,203 @@
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#define MGBE_MAX_BAK_IDX ((MGBE_MAC_VLAN_BAK_IDX(0) + \
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MGBE_MAX_VLAN_FILTER + 1U))
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/** @} */
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/**
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* @addtogroup MGBE-MAC MGBE MAC HW feature registers
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*
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* @brief Helps in identifying the features that are set in MAC HW
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* @{
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*/
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#define MGBE_MAC_HFR0 0x11C
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#define MGBE_MAC_HFR1 0x120
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#define MGBE_MAC_HFR2 0x124
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#define MGBE_MAC_HFR3 0x128
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/** @} */
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/**
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* @addtogroup MGBE-MAC-Feature MGBE MAC HW feature registers bit fields
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*
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* @brief HW feature register bit masks and bit shifts.
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* @{
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*/
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#define MGBE_MAC_HFR0_RGMIISEL_MASK 0x1U
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#define MGBE_MAC_HFR0_RGMIISEL_SHIFT 0U
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#define MGBE_MAC_HFR0_GMIISEL_MASK 0x1U
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#define MGBE_MAC_HFR0_GMIISEL_SHIFT 1U
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#define MGBE_MAC_HFR0_RMIISEL_MASK 0x1U
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#define MGBE_MAC_HFR0_RMIISEL_SHIFT 2U
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#define MGBE_MAC_HFR0_HDSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_HDSEL_SHIFT 3U
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#define MGBE_MAC_HFR0_VLHASH_MASK 0x1U
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#define MGBE_MAC_HFR0_VLHASH_SHIFT 4U
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#define MGBE_MAC_HFR0_SMASEL_MASK 0x1U
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#define MGBE_MAC_HFR0_SMASEL_SHIFT 5U
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#define MGBE_MAC_HFR0_RWKSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_RWKSEL_SHIFT 6U
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#define MGBE_MAC_HFR0_MGKSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_MGKSEL_SHIFT 7U
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#define MGBE_MAC_HFR0_MMCSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_MMCSEL_SHIFT 8U
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#define MGBE_MAC_HFR0_ARPOFFLDEN_MASK 0x1U
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#define MGBE_MAC_HFR0_ARPOFFLDEN_SHIFT 9U
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#define MGBE_MAC_HFR0_RAVSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_RAVSEL_SHIFT 10U
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#define MGBE_MAC_HFR0_AVSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_AVSEL_SHIFT 11U
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#define MGBE_MAC_HFR0_TSSSEL_MASK 0x1U
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#define MGBE_MAC_HFR0_TSSSEL_SHIFT 12U
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#define MGBE_MAC_HFR0_EEESEL_MASK 0x1U
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#define MGBE_MAC_HFR0_EEESEL_SHIFT 13U
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#define MGBE_MAC_HFR0_TXCOESEL_MASK 0x1U
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#define MGBE_MAC_HFR0_TXCOESEL_SHIFT 14U
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#define MGBE_MAC_HFR0_RXCOESEL_MASK 0x1U
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#define MGBE_MAC_HFR0_RXCOESEL_SHIFT 16U
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#define MGBE_MAC_HFR0_ADDMACADRSEL_MASK 0x1FU
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#define MGBE_MAC_HFR0_ADDMACADRSEL_SHIFT 18U
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#define MGBE_MAC_HFR0_PHYSEL_MASK 0x3U
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#define MGBE_MAC_HFR0_PHYSEL_SHIFT 23U
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#define MGBE_MAC_HFR0_TSSTSSEL_MASK 0x3U
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#define MGBE_MAC_HFR0_TSSTSSEL_SHIFT 25U
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#define MGBE_MAC_HFR0_SAVLANINS_MASK 0x1U
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#define MGBE_MAC_HFR0_SAVLANINS_SHIFT 27U
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#define MGBE_MAC_HFR0_VXN_MASK 0x1U
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#define MGBE_MAC_HFR0_VXN_SHIFT 29U
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#define MGBE_MAC_HFR0_EDIFFC_MASK 0x1U
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#define MGBE_MAC_HFR0_EDIFFC_SHIFT 30U
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#define MGBE_MAC_HFR0_EDMA_MASK 0x1U
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#define MGBE_MAC_HFR0_EDMA_SHIFT 31U
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#define MGBE_MAC_HFR1_RXFIFOSIZE_MASK 0x1FU
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#define MGBE_MAC_HFR1_RXFIFOSIZE_SHIFT 0U
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#define MGBE_MAC_HFR1_PFCEN_MASK 0x1U
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#define MGBE_MAC_HFR1_PFCEN_SHIFT 5U
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#define MGBE_MAC_HFR1_TXFIFOSIZE_MASK 0x1FU
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#define MGBE_MAC_HFR1_TXFIFOSIZE_SHIFT 6U
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#define MGBE_MAC_HFR1_OSTEN_MASK 0x1U
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#define MGBE_MAC_HFR1_OSTEN_SHIFT 11U
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#define MGBE_MAC_HFR1_PTOEN_MASK 0x1U
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#define MGBE_MAC_HFR1_PTOEN_SHIFT 12U
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#define MGBE_MAC_HFR1_ADVTHWORD_MASK 0x1U
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#define MGBE_MAC_HFR1_ADVTHWORD_SHIFT 13U
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#define MGBE_MAC_HFR1_ADDR64_MASK 0x3U
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#define MGBE_MAC_HFR1_ADDR64_SHIFT 14U
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#define MGBE_MAC_HFR1_DCBEN_MASK 0x1U
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#define MGBE_MAC_HFR1_DCBEN_SHIFT 16U
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#define MGBE_MAC_HFR1_SPHEN_MASK 0x1U
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#define MGBE_MAC_HFR1_SPHEN_SHIFT 17U
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#define MGBE_MAC_HFR1_TSOEN_MASK 0x1U
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#define MGBE_MAC_HFR1_TSOEN_SHIFT 18U
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#define MGBE_MAC_HFR1_DBGMEMA_MASK 0x1U
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#define MGBE_MAC_HFR1_DBGMEMA_SHIFT 19U
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#define MGBE_MAC_HFR1_RSSEN_MASK 0x1U
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#define MGBE_MAC_HFR1_RSSEN_SHIFT 20U
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#define MGBE_MAC_HFR1_NUMTC_MASK 0x7U
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#define MGBE_MAC_HFR1_NUMTC_SHIFT 21U
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#define MGBE_MAC_HFR1_HASHTBLSZ_MASK 0x3U
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#define MGBE_MAC_HFR1_HASHTBLSZ_SHIFT 24U
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#define MGBE_MAC_HFR1_L3L4FNUM_MASK 0xFU
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#define MGBE_MAC_HFR1_L3L4FNUM_SHIFT 27U
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#define MGBE_MAC_HFR2_RXQCNT_MASK 0xFU
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#define MGBE_MAC_HFR2_RXQCNT_SHIFT 0U
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#define MGBE_MAC_HFR2_TXQCNT_MASK 0xFU
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#define MGBE_MAC_HFR2_TXQCNT_SHIFT 6U
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#define MGBE_MAC_HFR2_RXCHCNT_MASK 0xFU
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#define MGBE_MAC_HFR2_RXCHCNT_SHIFT 12U
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#define MGBE_MAC_HFR2_TXCHCNT_MASK 0xFU
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#define MGBE_MAC_HFR2_TXCHCNT_SHIFT 18U
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#define MGBE_MAC_HFR2_PPSOUTNUM_MASK 0x7U
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#define MGBE_MAC_HFR2_PPSOUTNUM_SHIFT 24U
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#define MGBE_MAC_HFR2_AUXSNAPNUM_MASK 0x7U
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#define MGBE_MAC_HFR2_AUXSNAPNUM_SHIFT 28U
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#define MGBE_MAC_HFR3_NRVF_MASK 0x7U
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#define MGBE_MAC_HFR3_NRVF_SHIFT 0U
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#define MGBE_MAC_HFR3_FRPSEL_MASK 0x1U
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#define MGBE_MAC_HFR3_FRPSEL_SHIFT 3U
|
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|
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#define MGBE_MAC_HFR3_CBTISEL_MASK 0x1U
|
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#define MGBE_MAC_HFR3_CBTISEL_SHIFT 4U
|
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|
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#define MGBE_MAC_HFR3_FRPPIPE_MASK 0x7U
|
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#define MGBE_MAC_HFR3_FRPPIPE_SHIFT 5U
|
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|
||||
#define MGBE_MAC_HFR3_POUOST_MASK 0x1U
|
||||
#define MGBE_MAC_HFR3_POUOST_SHIFT 8U
|
||||
|
||||
#define MGBE_MAC_HFR3_FRPPB_MASK 0x3U
|
||||
#define MGBE_MAC_HFR3_FRPPB_SHIFT 9U
|
||||
|
||||
#define MGBE_MAC_HFR3_FRPES_MASK 0x3U
|
||||
#define MGBE_MAC_HFR3_FRPES_SHIFT 11U
|
||||
|
||||
#define MGBE_MAC_HFR3_DVLAN_MASK 0x1U
|
||||
#define MGBE_MAC_HFR3_DVLAN_SHIFT 13U
|
||||
|
||||
#define MGBE_MAC_HFR3_ASP_MASK 0x3U
|
||||
#define MGBE_MAC_HFR3_ASP_SHIFT 14U
|
||||
|
||||
#define MGBE_MAC_HFR3_TTSFD_MASK 0x7U
|
||||
#define MGBE_MAC_HFR3_TTSFD_SHIFT 16U
|
||||
|
||||
#define MGBE_MAC_HFR3_ESTSEL_MASK 0x1U
|
||||
#define MGBE_MAC_HFR3_ESTSEL_SHIFT 19U
|
||||
|
||||
#define MGBE_MAC_HFR3_GCLDEP_MASK 0x7U
|
||||
#define MGBE_MAC_HFR3_GCLDEP_SHIFT 20U
|
||||
|
||||
#define MGBE_MAC_HFR3_GCLWID_MASK 0x3U
|
||||
#define MGBE_MAC_HFR3_GCLWID_SHIFT 23U
|
||||
|
||||
#define MGBE_MAC_HFR3_FPESEL_MASK 0x1U
|
||||
#define MGBE_MAC_HFR3_FPESEL_SHIFT 26U
|
||||
|
||||
#define MGBE_MAC_HFR3_TBSSEL_MASK 0x1U
|
||||
#define MGBE_MAC_HFR3_TBSSEL_SHIFT 27U
|
||||
|
||||
#define MGBE_MAC_HFR3_TBS_CH_MASK 0xFU
|
||||
#define MGBE_MAC_HFR3_TBS_CH_SHIFT 28U
|
||||
/** @} */
|
||||
#endif /* MGBE_CORE_H_ */
|
||||
|
||||
Reference in New Issue
Block a user