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mgbe: pcs: Fix offset for T26X_XPCS_WRAP_INTERRUPT_CONTROL

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Fix the offset for T26X_XPCS_WRAP_INTERRUPT_CONTROL
and removes unused macro.

Bug 4778785

Change-Id: I3f2ac54c8119727f05fc77348d95b12e9ac3f525
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3199177
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Bhadram Varka
2024-08-23 10:10:18 +00:00
committed by mobile promotions
parent a81ae285f2
commit 2e3848b279
2 changed files with 5 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
osi/core/mgbe_core.c
View File

@@ -2011,10 +2011,10 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
nveu32_t value = 0U;
nve32_t ret = 0;
const nveu32_t xpcs_intr_ctrl_reg[OSI_MAX_MAC_IP_TYPES] = {
0,
XPCS_WRAP_INTERRUPT_CONTROL,
T26X_XPCS_WRAP_INTERRUPT_CONTROL
};
0,
XPCS_WRAP_INTERRUPT_CONTROL,
T26X_XPCS_WRAP_INTERRUPT_CONTROL
};
const nveu32_t intr_en[OSI_MAX_MAC_IP_TYPES] = {
0,
MGBE_WRAP_COMMON_INTR_ENABLE,

3
osi/core/xpcs.h
View File

@@ -213,7 +213,7 @@
#ifdef HSI_SUPPORT
#define XPCS_WRAP_INTERRUPT_CONTROL 0x8048
#define T26X_XPCS_WRAP_INTERRUPT_CONTROL 0x8078
#define T26X_XPCS_WRAP_INTERRUPT_CONTROL 0x8084
#define XPCS_CORE_CORRECTABLE_ERR OSI_BIT(10)
#define XPCS_CORE_UNCORRECTABLE_ERR OSI_BIT(9)
#define XPCS_REGISTER_PARITY_ERR OSI_BIT(8)
@@ -224,7 +224,6 @@
#define XPCS_SFTY_1US_MULT_SHIFT 0U
#define XPCS_FSM_TO_SEL_SHIFT 10U
#define XPCS_FSM_TO_SEL_MASK 0xC00U
#define XPCS_FEC_EN OSI_BIT(0)
#endif
/** @} */