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osi: core: Disable HSI causing problem

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1) Disable PCS FEC_EN programming as should be enabled only
   for autonagotiation mode and phy support is also needed.
   Current phy AQR113C does not has FEC capability (Bug 3799112)
2) Enabling MAC_FSM_CONTROL.TMOUTEN cauing uncorrected error
   on boot (Bug 3584387)

Bug 3590939
Change-Id: Ib5491c64c1028e312470d113934848098e2b0fd5
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2777890
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Om Prakash Singh
2022-09-19 09:32:58 +05:30
committed by mobile promotions
parent 36a6a3d487
commit e8fbce237c
2 changed files with 4 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
osi/core/eqos_core.c
View File

@@ -1028,7 +1028,8 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
/* T23X-EQOS_HSIv2-3: Enabling and Initialization of Watchdog */
/* T23X-EQOS_HSIv2-4: Enabling of Consistency Monitor for FSM States */
value = (EQOS_PRTYEN | EQOS_TMOUTEN);
/* TODO enable EQOS_TMOUTEN. Bug 3584387 */
value = EQOS_PRTYEN;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + EQOS_MAC_FSM_CONTROL);

14
osi/core/mgbe_core.c
View File

@@ -2154,12 +2154,6 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
osi_core->hsi.enabled = OSI_ENABLE;
osi_core->hsi.reporter_id = hsi_err_code[osi_core->instance_id][REPORTER_IDX];
/* T23X-MGBE_HSIv2-10 Enable PCS ECC */
value = (EN_ERR_IND | FEC_EN);
ret = xpcs_write_safety(osi_core, XPCS_BASE_PMA_MMD_SR_PMA_KR_FEC_CTRL, value);
if (ret != 0) {
return ret;
}
/* T23X-MGBE_HSIv2-12:Initialization of Transaction Timeout in PCS */
/* T23X-MGBE_HSIv2-11:Initialization of Watchdog Timer */
value = (0xCCU << XPCS_SFTY_1US_MULT_SHIFT) & XPCS_SFTY_1US_MULT_MASK;
@@ -2189,7 +2183,8 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
/* T23X-MGBE_HSIv2-3: Enabling and Initialization of Watchdog Timer */
/* T23X-MGBE_HSIv2-4: Enabling of Consistency Monitor for XGMAC FSM State */
value = (MGBE_PRTYEN | MGBE_TMOUTEN);
/* TODO enable MGBE_TMOUTEN. Bug 3584387 */
value = MGBE_PRTYEN;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL);
@@ -2243,11 +2238,6 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
} else {
osi_core->hsi.enabled = OSI_DISABLE;
/* T23X-MGBE_HSIv2-10 Disable PCS ECC */
ret = xpcs_write_safety(osi_core, XPCS_BASE_PMA_MMD_SR_PMA_KR_FEC_CTRL, 0);
if (ret != 0) {
return ret;
}
/* T23X-MGBE_HSIv2-11:Deinitialization of Watchdog Timer */
ret = xpcs_write_safety(osi_core, XPCS_VR_XS_PCS_SFTY_TMR_CTRL, 0);
if (ret != 0) {