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Author SHA1 Message Date
Gaurav Asati
f1125b7063 osi: update API headers 
Use @usage instead of @note and group all classification and API
group details under @usage.

Bug 3350640

Change-Id: If77cfd76519f17427b95a2300ad722dc6f83f518
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587106
(cherry picked from commit 0002e2d0b2cf85811b09e8c7157dbd777c8fc117)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657079
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:46 -08:00
Gaurav Asati
9a6c5dbc4b osi: Add Async-sync details to API header 
Issue:
Async-sync details to API header is needed.

Fix:
Add Async-sync details to API header and remove duplicate Thread
details.

Bug 3350640

Change-Id: I0838e53951389c9fa408323324cedba0268f4706
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2572939
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
(cherry picked from commit 8acef05c924ed72e256e792a8cd623a221494287)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657054
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:35 -08:00
Sanath Kumar Gampa
65a9cb659e macsec: get next PN and IRQ stats cmd with server 
Some of the commands such as get next PN and irq stats
are not working if thernet server is enabled, fixed the same.
And also moved HKEY generation to OSD, to avoid dependency on
Crypto libs on LK. devmemr/w can read/write to macsec addresses

Bug 3522740

Change-Id: Id3b328cfd83aa976ef5bde8adc057588bb6fed38
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652212
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-27 18:07:30 -08:00
Narayan Reddy
97d5787a79 mgbe: modify AXI clock to 480MHz 
480MHz APP clock needs to be used for 10G speed as per IAS.
Change the clock source to reflect the same.

Bug 200778229

Change-Id: Idf60c4a090ed82b0a1be58d5b45b3a557c59fdfc
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2660870
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-10 14:05:50 -08:00
Bhadram Varka
f2f5cbf648 osi: fix coverity defects 
CID 10060746 Big parameter passed by value
CID 10060747 Big parameter passed by value
CID 10127879 Dereference after null check

Bug 3461002

Change-Id: Ib1d88177ade979e43e9177ff69f7817982b39be0
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2665777
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-09 20:53:58 -08:00
Om Prakash Singh
bc8f866fac osi: fix mmc.h dependency on osi_common.h 
mmc.h uses few definition from osi_common.h

Bug 3500728

Change-Id: I95696ddd63cee4979c0a79cda9a87e65b895dee0
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2663878
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-09 09:47:04 -08:00
Sanath Kumar Gampa
f88c313a87 To fecilitate calling the PTP-TSC capture in ISR 
Change the usleep used to udelay, so that PTP-TSC
fetching can happen in ISR context

Bug 3430408

Change-Id: I2d6f3755e94fafabe80913fd81cbf1a85c83d407
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2639986
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-02 21:41:38 -08:00
Mahesh Patil
393cfedcf7 nvethernetrm: macsec qnx OSI changes 
Macsec qnx driver OSI changes

Bug 3338180

Change-Id: I2ad4f1b8b919893f2823a120973c1805b58bbb88
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2612659
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
 2022-02-02 21:40:44 -08:00
Bhadram Varka
5461678a44 osi: dma: combine global DMA status functions 
Global DMA status register offsets are same for
EQOS and MGBE. Combine EQOS and MGBE function
into single function instead of two functions.

Bug 200770328

Change-Id: Ia5dfebfd4625daa7bfd04e53e13a6df6a111047e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2660067
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-28 04:51:37 -08:00
Gaurav Asati
92592afeed nvethernetrm: add support desc dump on QNX. 
- Enable desc dump on normal builds
 - export API osi_dma_ioctl

Bug 3375445

Change-Id: I66f33f6c370ebcfcfa194e88d598633cd0892a15
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2645253
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-21 09:16:52 -08:00
Sanath Kumar Gampa
fb4dde440b osi: Avoid macsec and fpe coexistance on MGBE 
Issue: Internal FIFO over/underflows if MACSEC and FPE are enabled on MGBE
interafce and pre-emptable and express frames are sent in interleaved
fashion

Fix: Do not allow enabling any of MACSEC and FPE if the other is already
enabled.

Bug 3484034

Change-Id: Ifc80eb9333c836652a86362a1f7788a0ce70dbb7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2647788
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-01-20 15:36:57 -08:00
Mahesh Patil
b106e60bd9 Revert "nvethernetrm: pad calibration" 
This reverts commit 54263d6ea5.

Bug 3494618

Change-Id: I8e609fb2d42be713d255703d79e1b318078f2907
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2651963
Reviewed-by: Hyong Bin Kim <hyongbink@nvidia.com>
Reviewed-by: Kasinadha Dendukuri <kdendukuri@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Kasinadha Dendukuri <kdendukuri@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-01-13 19:34:36 -08:00
Rakesh Goyal
2246e3a2a5 core: add support configure pps out signal 
Issue: Default pps output is 1 pulse (of width
clk_ptp_i) every second.

Fix: option to configure to binary rollover is 2 Hz,
and the digital rollover is 1 Hz.

Bug 3462227

Change-Id: Ic777bfaf51a72ec91c8f165910e824c55cae3057
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2641896
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-11 20:06:08 -08:00
Mahesh Patil
54263d6ea5 nvethernetrm: pad calibration 
Enable update pad caliration code under UPDATED_PAD_CAL
macro and remove old pad calibration code
Bug 2831220

Change-Id: I01daa72ff6e6cfb016de85f22b55404a9d8a54ba
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2562771
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-06 17:17:51 -08:00
Prateek Patel
68e89375a3 nvethernetrm: fix large_shift coverity defect 
Checking vid_idx == 32U implies that vid_idx is 32 on the true branch.
In expression OSI_BIT(vid_idx), left shifting by more than 31 bits has
undefined behavior. The shift amount, vid_idx, is 32. Return with "-1"
error condition to fix the defect.

CID 10060748

Bug 3461002

Change-Id: I7711152fcf93e50f3c85eddf20b3e9721fb4f853
Signed-off-by: Prateek Patel <prpatel@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2642992
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-22 08:35:15 -08:00
Rakesh Goyal
bdf6243c69 core: eqos: fix PTP register offset 
Issue: ETHER_QOS_PTP_CAPTURE_* register offset was wrong.
low and high offset are swapped.

Fix: correct the offset value.

Bug 3471827

Change-Id: Ia7e13209e123f1c58655af9b79186aa6a21ad316
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2642729
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-16 09:11:49 -08:00
Mohan Thadikamalla
c2b4bf8204 mgbe: Fix FRP DMA route issue 
Issue:
FRP MC/BC packets routing to
multiple DMA channels is not happening.

Fix:
Correct the FRP entry DCH programming to
enable multiple DMA channels route.

Bug 3417901

Change-Id: Ib3d5794253b89d7d3a00164fa7fd011e4ac9e50b
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2629966
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-14 02:45:56 -08:00
Sanath Kumar Gampa
f1e4661f1e osi:macsec:Changes to enable AN after key program 
Issue: In longer stress tests we see unint_key_slot
errors if the key programing is done after AN is
enabled.

Fix: Fix is to program the key and then enable AN.
Done some code cleanup as well

Bug 3422356

Change-Id: I7aeb2f9ab681509b54e9f6763464dfedb46cd26e
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2626062
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-14 02:45:34 -08:00
Rakesh Goyal
a5c2423f63 core: enable m2m_sync for primary and secondary interfaces 
Issue: Ask is to enable Mac-to-Mac tsync
on interface for primary and secondary interface.

Fix: update default value.

Bug 200733666

Change-Id: Ie00e3cf96d0deb75d7c623a63bc0d06ed637ca2c
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2628723
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Sheetal Tigadoli <stigadoli@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
jetson_34.1.1 jetson-r34.1_dp 		2021-12-06 04:35:42 -08:00
Sanath Kumar Gampa
d190c203da osi:macsec:Fix to address sc_an_not_valid counter 
Issue: tx_sc_an_not_valid counter is increasing in
stress tests when there is AN roll over happens

Fix: Program the SCI LUT with vaid AN map and then
enable AN in sc_state LUT

Bug 3422356

Change-Id: I17021d435076ff94367a58a4c74b50124c97d68a
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2623649
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-12-02 07:39:53 -08:00
Bibhay Ranjan
97c73020e2 nveqos:fix MISRA_C-2012_Rule_8.13 and 10.4 issues 
MISRA FIXES
===== DIFF ======
Total misra violation count changed by -21
Rule: MISRA_C-2012_Rule_10.4 Diff: -1
Rule: MISRA_C-2012_Rule_8.13 Diff: -20
Rule: Total Diff: -21

CERT FIXES
===== DIFF ======
Total cert violation count changed by 0

Bug 200770325

Change-Id: Ib6cca8c2eaff5ae8cddd718b2f0c309c6888d4fc
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605632
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-17 12:47:39 -08:00
Sanath Kumar Gampa
c52ad89f9d osi:macsec:lowest pn changes to enable sa 
Enhancement to receive lowest_pn from supplicant
as part of receive AN enable

Bug 3371004

Change-Id: If81f8449f7ebda996c95117e2c84722fdc57c5d0
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2619949
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-11 20:39:08 -08:00
Mohan Thadikamalla
ee1da8d41d osi: xpcs: Remove XPCS lane bring up retry 
Issue:
When the ethernet server got enabled the boot time KPI
increased due to the XPCS lane up retry.

Fix:
Remove retry from OSI and add SET_SPEED ioctl
retry from OSD.

Bug 3414276

Change-Id: I617ab51ee6ddd50b449f78ecc9c858b1d9196b3e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2617516
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-10 00:19:36 -08:00
Rakesh Goyal
81e1442693 nvethernetrm: core: MAC to MAC tsync dynamic support 
Add code to support enable/disable M2M sync using
ioctl.

Bug 200733666

Change-Id: Ifedad7981644c816345f3e10a0b0f8289e032200
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614964
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-02 04:07:38 -07:00
Rakesh Goyal
61be2488de nvethernetrm: MAC to MAC time sync 
- Add code to store role of FD
- Function to return osi_core pointer for
  first role match.
- add code to calculate time offset between
  Primary and Secondary PTP controller HW time.
- calculate frequency adjustment calculation.
- call appropriate HAL function for
  secondary interface.

Bug 200733666

Change-Id: I7a141ea691d80d9f69fd18b28ae0964cb1bf2fb3
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614283
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-02 04:07:33 -07:00
Sanath Kumar Gampa
b8e03a8b43 osi:macsec: changes to send next PN to supplicant 
As part of MKA, supplicant requests for Next PN
used by SecY. Added changes to OSI to send to
send the Next PN for a given SCI and AN.

Bug 3371004

Change-Id: Iaf001ba5e6b5480396e2f774a42927831160a2e5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614365
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-28 01:06:06 -07:00
Bhadram Varka
15aec6d712 osi: dma: check TDES3_ES_BITS for EQOS 
Issue: TDES3_ES_BITS not valid for MGBE which results
wrong error stats in ethtool o/p

Fix: Check TDES3_ES_BITS only for EQOS.

Bug 200779501

Change-Id: Idccc8cca54b2fe6f8ac30ed99f2cc69d093acea9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2609473
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-22 02:09:16 -07:00
Mohan Thadikamalla
31058b6774 osi: core: Add MTU IOCTL support 
Issue:
When the ethernet server got enabled,
the MTU changes are not getting
communicated to the ethernet server.

Fix:
Add new OSI IOCTL and implement HAL
and IVC message for ethernet server.

Bug 3402313

Change-Id: I28bab58c2847d275324e54229ac50459d3059d26
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2610189
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-18 21:43:48 -07:00
Sanath Kumar Gampa
6108b6e8a1 nvethernetrm:Disabled DIC as part of mgbe init 
Issue:seeing 0 Throughput after MACSEC is enabled

Fix: Disable DIC to fix 0 Tput issue

Bug 200770840

Change-Id: I8cceee8fd8509ec484bfbb6063ca4dd8be091fa5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2606457
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-14 12:03:15 -07:00
Sanath Kumar Gampa
2a3bdce7c8 nvethernetrm: MTL_EST CTOV config for MACSEC 
Issue: h/w requirement to change the MTL_EST value
depending on MACSEC

Fix: Change the value in MACSEC enable/disable flow

Bug 200630202

Change-Id: Iefdb14e44841941ab3e8f8c116746b0db6c63ba5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604830
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-14 12:02:52 -07:00
Nagaraj Annaiah
5df5eefe5a osi: core & dma : Increase osi and dma instances 
- Increase OSI and DMA instances to 10 to support
  multiple VF's.
- Copy PTP config to ioctl structure.

Bug 2694285

Change-Id: I558b161c64a5467dc9e7260e58801eb6b1735d50
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605781
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-07 22:39:51 -07:00
Mahesh Patil
0b11badd9d nvethernetrm: Fix err for macro MACSEC_KEY_PROGRAM 
Fix compiler err when macro MACSEC_KEY_PROGRAM enabled
Bug 3389496

Change-Id: Ic95dd8c5b63538f3f246122ddb203a649afc6975
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2601538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-07 17:52:02 -07:00
Rakesh Goyal
e6a2dd50b4 osi: core: Set QHLBF bit 
As per HW fix, program QHLBF to 1 to get
HLBF error in 1-2 cycle of GCL.

Bug 200778825
Bug 200649072
case: 01085007

Change-Id: I18cfa6ad4eda56e2684abd86b7dc02c7a143c0ef
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2601421
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-07 17:51:50 -07:00
Bhadram Varka
d58825f314 osi: dma: fix SMMU faults with iova address 0x0 
Issue: Transmit buffer address is pupulated in transmit
descriptor only if buffer address is less than UINT_MAX.
If the buffer address equals to UINT_MAX then descriptor
will have value of zero which is filled during transmit
completions. Because of this HW tries to fetch the address
zero which not valid and results in SMMU fault.

Fix: Fill all tdesc0 using with lower 32 bits and tdesc1
with higher 32 bits

Bug 200779695

Change-Id: I3706234d3f8c561f8291ffd63a1b1d63d046d2f2
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604615
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-06 18:17:03 -07:00
Narayan Reddy
4bfff697fe osi: core: mgbe: pass correct argument 
Issue: base pointer is passed instead of osi_core
for mgbe_l3l4_filter_read and mgbe_l3l4_filter_write
as an first argument.

Fix: Pass osi_core pointer instead of base

Bug 200764768

Change-Id: I29ec030b2cab98d49f164d1011ac0f951496aa1c
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2603073
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-06 18:16:11 -07:00
Narayan Reddy
b9be4579b7 osi: core: Enable Transparent Tx LPI Mode 
In this mode, the transmit LPI state-machine
does not move to TX_QUIET state. On detecting Lower-Power Idle
on XGMII/GMII Tx interface, xpcs goes to the TX_SLEEP state and
remains in this state till MAC stops sending LPI.

Bug 200764486

Change-Id: I376ac481e880472d7a11b60931a90d6f9c7a0067
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2598380
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-24 12:31:56 -07:00
Rakesh Goyal
972305578c core: add CMD_PTP_TSC_CAP to capture time 
issue: Requirement is to have a method by which
       TSC-PTP-CAPTURE can be initiated.

fix: Having osi_core ioctl to trigger and capture
     TSC-PTP timestamp using HW logic.
     Caller need to call osi_handle_ioctl with
     command as OSI_CMD_CAP_TSC_PTP,
     osi_core pointer and osi_core_ptp_tsc_data
     structure.

Bug 200736396

Change-Id: I511dc4f490fdef81655a62c18268764741855fe4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2554284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-22 15:39:49 -07:00
Bhadram Varka
a0c20c02f6 osi: mgbe: add handling of tx errors 
handle Tx buffer underflow
handle Tx jabber timeout
handle Tx IP header error
handle Tx Payload checksum error

Bug 200565898

Change-Id: I2de4cd11580251f0387039c1f8f3c39792c1ab65
Signed-off-by: narayanr <narayanr@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2596092
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-21 13:40:58 -07:00
Bhadram Varka
dbaf1ac0ba osi: xpcs: Fix Tx lane bring-up failure 
Issue:
During Tx lane bring up power up will fail if
the lane is already powered up.

Fix:
Don't bring-up Tx lane if its already powered up.

Bug 200766119
Bug 200764018

Change-Id: Idbdffdca7b9c9cccd8b8876fcfe8ea7448a7ed10
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2597604
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-21 07:51:42 -07:00
Rakesh Goyal
2200f3d921 core: update code for TSN 
- Update CTOV recommended value
- Update PTOV recommended value
- Disable PEC filed on preemption disable
- Disable EEST with message to reprogram
  GCL instead of dropping packet on HLBF/HLBS
- Configure code not to drop any packet silently
  on HLBF and HLBS error
- Q2TC mapping with CBS enable

Bug 200763256
Bug 200765943

Change-Id: I7a2581af488e22a23d32ce1819440c21f4748800
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2593162
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-20 11:10:24 -07:00
Rakesh Goyal
fc9e41ca31 dma: check tx_pkt_cx length field 
Validate tx_pkt_cx before updating
hardware

Bug 200765943
Bug 200763256

Change-Id: I44c4b1ec3adfed2b9f871924b3f03a3dd6e2ab2f
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2592513
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-20 11:10:13 -07:00
Rakesh Goyal
a9b03b83a9 core: mgbe: use lock for time stamping 
Using lock for protect critical section between
common interrupt and ioctl call to read
timestamp

Add mmc counters for lock failure during node
addition and deletion.

Bug 200743666

Change-Id: I12a2e57993e91d6ed50ed0efc84d1b60ef736677
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2590099
Tested-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-20 11:09:19 -07:00
Nagaraj Annaiah
801815742d osi: core: macsec: Add macsec fix 
Issue: macsec doesn't work for virtualization.

Fix:
1.Move virtualization checks before address check.
2. Copy PTP config to ioctl structure.

Bug 2694285

Change-Id: I81f47cf23e37a62a3e5b8ecece8ae905ec1a5df3
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587833
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 19:06:59 -07:00
Bhadram Varka
0372ac4f94 osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID based on MAC instance ID through HV window

Bug 200761024

Change-Id: I1a37455647429e917e7558e812fe7e512d646918
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2592482
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 09:18:17 -07:00
Mohan Thadikamalla
c21e65e2a7 osi: eqos: Fix FRP entry update fail 
Issue:
FRP entry update command is getting
failed due to an invalid RXPI check
on EQOS IP.

Fix:
Fix the RXPI check on the FRP
update as per the databook.

Bug 200766666

Change-Id: I4631623ec06bf815c88c5364f5ae599d0e7702dc
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587257
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 05:00:29 -07:00
Rakesh Goyal
6c53499842 core: eqos: handling onestep ipv4 flags 
Issue: OSI_MAC_TCR_CSC not handled in
eqos code

Fix: update time control register with
CSC bit if passed form upper layer.

Bug 200764256

Change-Id: Ifbfab0de4bb81625c4bd023fad67131ee6a43987
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2593818
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Mohan Thadikamalla <mohant@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-14 11:13:45 -07:00
Mahesh Patil
3af55e0c58 nvethernetrm: change MAC ipg as per macsec req 
Change MAC ipg value as macsec IAS requirement when
macsec is used

Bug 3335658

Change-Id: Ie681bb0a66b256c32ac6093114fe29c65bf20a07
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-10 02:10:19 -07:00
Rakesh Goyal
581b8ad758 dma: mgbe: update RWT and RWUT programming for silicon 
Issue: RWT and RWUT programmed for uFPGA

Fix: Update RWIT programming
     Update minimum rx coalescing timer value

Bug 200767374

Change-Id: I09c21764f0c294021c7546f75351c19c34a0b9db
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2589496
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-09 09:22:28 -07:00
Rakesh Goyal
2e176d13c6 core: eqos: Program OVHD value for EQOS 
As per guidelines form HW team, add
recommended OVHD for eqos

Bug 200765943

Change-Id: Ic885ed9681869fd6f13c65407d208f9e30e19e5e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2589995
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-07 16:11:15 -07:00
Mohan Thadikamalla
7d215e6dcb osi: eqos: Fix 4 to 7 RXQ to DMA mapping 
Issue:
DCS test are getting fail due to invalid
RXQ to DMA mapping.

Fix:
Enable DMA mapping for RXQ 4 to 7

Bug 200765514

Change-Id: Idece787a9aa7d9c9bac52be64f55a9ec962f092f
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587182
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-07 05:34:23 -07:00