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161 Commits

Author SHA1 Message Date
Narayan Reddy
f551f8ab61 nvethernetrm: Update comments with Doxygen style 
replace kernel doc comments with Doxygen style comments

Bug 200512422

Change-Id: I2e8e1f395674ab9e1b66bf40c1f6cc0551608163
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154252
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Srinivas Ramachandran
006059e0a5 nvethernetrm: Implement external safety mechanism 
EQoS MAC version < 5.10 is not safety certified. To ensure
some basic error handling situations, implement external
error handling mechanism in the driver to periodically
read and verify the current register content for certain
critical registers, against the last written value.

Bug 2594911

Change-Id: I1d7c01f89ad838ffe3ab1efd15126640ae9df775
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2136607
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohit Dhingra
d37c177696 nvethernetrm: fix macro name 
ESQC-9844

Change-Id: If0b0311962c2bf0b676aa464aed44183dabc058f
Signed-off-by: Mohit Dhingra <mdhingra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152300
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
f184678da6 nvethernetrm: add support for RIWT 
This support enables the configuration of Receive Interrupt
Watchdog Timer register which indicates the watchdog timeout for
Receive Interrupt (RI) from the DMA.

Bug 200512422
Bug 2624476

Change-Id: I66830a47c34845af06e318ba6069935d51d15af8
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138153
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
5769a9a843 nvethernetrm: add L2/L3/L4 filter based dma routing code 
With this feature filtered Rx packet will be redirect to
corresponding DMA channel based on register configuration.

Function driver code need to pass 2 extra parameters enable/disable
and dma channel number within the valid range to utilize this
functionality.

For L2 filtering, function driver code can also pass address mask
and src_dest for filter index 1-31.

Bug 200525721

Change-Id: Ibf3fb93cdd4c3b7c0384a0e36e7bbe467bb41e04
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133197
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
11b9f541cb nvethernetrm: add HW and SW counters' support 
These stats are read from MAC HW RMON counters as well as from Core
and DMA path.

ethtool -S <interface> is used to get statistics.

There are 3 stats captured currently
1) ether_mmc_counters: EQOS HW RMON counters
2) ether_xtra_stat_counters: SW counters from osi/core
3) ether_xtra_dma_stat_counters: SW counters from osi/dma

Bug 200519211

Change-Id: I5bbeb340cf2ffccb6399687b254f79c67f480179
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114208
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
a50f8221de nvethernetrm: add PTP support 
This takes care of implementing the PTP support
which includes PTP V1/V2 over IPV4,IPV6,Ethernet,gPTP.

Bug 200524751

Change-Id: Ieb680d818be81c1a1a8349ddd9ff02bba1896b08
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127117
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
d73ccb3299 nvethernetrm: replace numeric values with Macros 
As general practice we have replaced numeric value with Macro for
MAC Filter. This will help to make it readable and scalable.

Bug 200512993

Change-Id: I4bbc676eabc85be5f0b8285328a3a91e1a7c61ee
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131537
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
54475f5365 nvethernetrm: enable mac filter 
Code to configure and program register for L2/L3/L4/VLAN Filter

Bug 200512993

Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: I469e25aeb2a31878d2fd7384cbe5f63c63d3b924
Reviewed-on: https://git-master.nvidia.com/r/2111083
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohit Dhingra
f08bdc09b3 nvethernetrm: avoid redefining macro ULONG_MAX 
For QNX, macro ULONG_MAX is already defined in the toolchain.
Define the macro only when not defined earlier.

ESQC-9836

Change-Id: I3afcb5ec0933ec31816e8b6602a5a99260e00e04
Signed-off-by: Mohit Dhingra <mdhingra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124114
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Srinivas Ramachandran
a08e20e2ac nvethernetrm: Add support for HW offloads 
1. ARP offload can be configured private ioctl.
   The IP address to be configured for ARP offload
   needs to be provided by application as unsigned
   char array. Refer to struct ether_ifr_data and
   struct arp_offload_param for details.

2. Tx/Rx checksum offload. Enabled by default (can
   be toggled using ethtool)

3. TCP Segmentation offload. Enabled by default (can
   be toggled using ethtool)

Bug 2571001

Change-Id: Ifcf2982557e80655e3cd7ebf3c70f49c538133b5
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109677
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
3efe5a2afa nvethernetrm: add pause frame support 
Pause frame  is a flow control mechanism for
temporarily stopping the transmission of data on
Ethernet. The goal of this mechanism is to ensure
zero packet loss in case of network congestion.

Bug 200516459

Change-Id: Ideaaecd346bc7f509fbe2fc8e915b9e1fc45c958
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111934
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohit Dhingra
d4547fd86c nvethernetrm: add tmake support 
- Split files into core and dma directories to add
   separate tmake files for creating separate RM and DMA
   channel libraries.

ESQC-7634

Change-Id: Id9a2431bbee73a29b4a3565d8aa2bc0d8e7f0c78
Signed-off-by: Mohit Dhingra <mdhingra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109978
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
835dc93a54 nvethernetrm: Enable Tx packet status reporting 
Added support for configuring the MTL to drop or
forward the Tx packet status to application.

Added API to clear the tx packet error stats

Bug 200515518

Change-Id: I818b4581b8bcbe84d0ca065010c60dd93726a385
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108560
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
b8b3d26534 nvethernetrm: support for jumbo frames 
Bug 200513783

Change-Id: Ie0fccc6a1cbdf2e6417d78f616fcec71ba6f3ebf
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094021
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
2d363b3616 nvethernetrm: MAC loopback support 
When MAC HW loopback is enabled, MAC receives
back all the packets that is being sent by it.
Packets which were sent are looped inside the
MAC and it is not being sent to PHY.

Bug 200512681

Change-Id: Iec42e937824424c46eb15a281fb0c33e92ea2056
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088985
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
adc88f9c88 nvethernetrm: add adress width read support 
Add support for reading the Address Width
from the MAC_HW_Feature1 register

Bug 200458098

Change-Id: I32ae42f536fbac781584425dcccd91155542b579
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099488
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
6639ef53c1 nvethernetrm: osi code for EQOS 
Bug 200507585

Change-Id: I70ce3d013eeb109ebf323e732820fb51c360e313
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
93c142ba2a delete the directories to move the history 
Change-Id: I701c1a8c6c891dc8ee2781d51c2c6ad748ed5bf3
 2024-02-21 16:31:52 +05:30
Bhadram Varka
232ce3ef80 osi: core: support pause frames 
Enable pause frames for Safety builds as well based
on pause_frames if the osi_core->pause_frames is
set to OSI_PAUSE_FRAMES_ENABLE based on DT parameter
nvidia,pause_frames.

Bug 4186472

Change-Id: I8600ae0ce1a9d9a5dd132a949ec14e8d73735319
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2931298
(cherry picked from commit b553b09358e1b4dbce8529c756f013b528f27862)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2931295
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-08-31 16:23:29 -07:00
Mahesh Patil
047a42bef8 osi: core: Update eqos pad calibration 
Updated eqos pad calibration for qnx

Bug 2831220
Bug 3500401

Change-Id: I2301e66ae8bc905b8a61deb37694b0875a20173d
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2846450
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-25 11:07:02 -08:00
Mohan Thadikamalla
43efa1f979 nvethernetrm: Fix Linux safety builds issues 
Issue:
Observed compilation issues
on the nvethernet driver
for DRIVE Linux safety builds.

Fix:
Move out required defines from OSI_STRIPPED_LIB

Bug 3939603

Change-Id: I2418b2b3bd21b5ed4e7e75a3b585f2f542a451c1
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2843094
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-23 15:22:24 -08:00
Narayan Reddy
3fff0cd9ba osi: core: fix Doxygen warnings 
1) Fix Doxygen warnings
2) include debug.h code only when OSI_DEBUG
is defined

JIRA NET-570

Change-Id: I5d002b959925bec3898cc2faafe3f506b3c9bd22
Signed-off-by: Narayan Reddy<narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2847327
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-04 16:49:50 -08:00
Bhadram Varka
32fa453326 nvethernetrm: move pause-frame macros 
Pause frames not programmed in safety builds
so move those macros under non safety builds.

Bug 3932946

Change-Id: Iff89373c4ffd20b35589f3f3852ef191f5f54acf
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2844105
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-19 07:52:33 -08:00
Diptanshu Jamgade
8089f79df8 osi: core: Update OSI_PAUSE_FRAMES_DISABLE 
Issue:
Wrong value of OSI_PAUSE_FRAMES_DISABLE
enabling flow control at probe.

Fix:
Update OSI_PAUSE_FRAMES_DISABLE as per
dt-bindings to disable pause frame support
as a default

Bug 3932946

Change-Id: I0d5227c06b4b5627dc47f5542bbf5d2a0e7ed3bf
Signed-off-by: Diptanshu Jamgade <djamgade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2839839
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-14 18:12:09 -08:00
Rakesh Goyal
379f8ae9a5 osi: core: enable m2m by default 
Mac2Mac sync code enable by default.

Bug 3883951

Change-Id: Iaf09dba80be0d180bf23dff70c65a8e6f34ab9d2
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2814598
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-08 00:05:39 -08:00
Hareesh Kesireddy
3be2a1e7f3 osi: l3l4: support four tuple for l3l4 fitlers 
Following implemented for non safety.
- Moved l3l4 filter index assignment to OSI for better management.
  OSDs need not worry about managing l3l4 filter indexes.
- Restructured code to support four tuple for osi l3 l4 filter.
- Added a wildcard l3l4 filter at highest filter index to allow the
  the packets to receive on default dma channel (from l2 filter) for the
  packets which do not match with any of the configured l3 l4 filters.
- For IPv4, allowed user to configure all SA+DA+SP+DP together at a
  single l3l4 filter index or user can selectively add any
  combination among them (e.g, only SA or SP+DA, etc.).
- For IPV6, only restriction is to add either of the SA or DA only
  but not both at a time at a single l3l4 index.

Bug 3576506
Bug 3825731

Change-Id: I20bd197f5bf793a77f5e723d1875875d442af66e
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2802626
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-30 06:16:47 -08:00
Rakesh Goyal
9597f795e4 nvethernetrm: take arguments field out of union 
ioctl_data as well as arguments required to
support PTP IOCTL in ASIL path

Bug 3868362

Change-Id: Id6d3cf7626b7426a8e44a086335501cf86f50d62
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2807393
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-24 00:39:47 -08:00
Sanath Kumar Gampa
70e0744729 osi: Removal of global variables related to HSI 
Removed Report ID and error codes from global and moved them to local.

Bug 3857897

Change-Id: Ib1a5d70782e8c8e26ca3f04316f7f2bb2b03735f
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2806355
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-17 07:19:11 -08:00
Bhadram Varka
2fb7d1d324 osi: eqos: configure MTL RXFIFO and PFC threshold 
MTL RXFIFO memory available for EQOS - 64KB
Below is the distribution -
1) Q0 - 36KB
2) Q1 to Q6 - 2KB
3) Q8 - 16KB

It also update flow control parameters for
the Rx queues
1) Q0 - FULL_MINUS_16K
2) Q1 to Q7 - FULL_MINUS_1_5K

Bug 3787316

Change-Id: I59031ad03f02d5804fcc65cb24e05559e6358500
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2789263
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-14 20:55:16 -08:00
Narayan Reddy
81242cd874 osi: core: Fix misc optimizations 
1) remove duplicate checks
2) remove unused APIs
3) moved to STRIPPED if not used

Bug 3701869

Change-Id: Id6ba8649ff5135affa949ea8dde947db10003f80
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2784309
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-04 16:17:25 -07:00
Diptanshu Jamgade
4a8382d6fb nvethernetrm: update OSI_PAUSE_FRAMES_ENABLE macro 
Update OSI_PAUSE_FRAMES_ENABLE as per the updated
DT-bindings.

Bug 3529804

Change-Id: Ice290ef85c370956cec2a7b29cc0b6f82ac39093
Signed-off-by: Diptanshu Jamgade <djamgade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2790122
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-10-20 02:13:37 -07:00
Bhadram Varka
5fba408c31 osi: mgbe: configure MTL RXFIFO and flow control 
MTL RXFIFO memory available for MGBE - 192KB
Below is the distribution -
1) Q0 - 160KB
2) Q1 to Q8 - 2KB
3) Q9 - 16KB

It also update flow control parameters for
the Rx queues
1) Q0 - FULL_MINUS_32K
2) Q1 to Q9 - FULL_MINUS_1_5K

Bug 3787316

Change-Id: I3049d742e784aa3273090191856482121a3e1d3e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2779472
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-09-28 12:47:58 -07:00
Rakesh Goyal
80575def01 nvethernetrm: support L2 filter from ioctls 
Move L2 and L3 structure to osi_core as new structure
at OSD level created to user data.
Number of max L2 filter check based on mac version.

Bug 3659048

Change-Id: I9e1e7c015e8c3a0579a363ccd6bcfe9d84e67eea
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2777333
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-24 13:21:25 -07:00
Rakesh Goyal
fdf60cfb28 nvethernetrm: update filename and location 
Update file name to be added in SDK

Bug 3704251

Change-Id: Ibc6b53a6c152973f249d8af94a33cd537b1ea7ec
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2778302
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-21 01:13:51 -07:00
Rakesh Goyal
6b4ddb8043 nvethernetrm: take exported ioctl related header out 
Issue: SW needs to support IOCTL on safety builds and
these header should be exposed to user

Fix: Create new header file which is exposed externally
     Fix Coverity issues
     Enable TSN and FRP for safety build
     Optimize the code between eqos and mgbe

Bug 3704251

Change-Id: I2807f8283a296de1f96d3f902cb4ad5a4781be50
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2759333
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2022-09-12 20:52:00 -07:00
Bhadram Varka
f77e6e4eb6 osi: dma: Fix MISRA issues 
===== DIFF ======
Total misra violation count changed by -162
Rule: MISRA_C-2012_Directive_4.6 Diff: -13
Rule: MISRA_C-2012_Directive_4.9 Diff: 5
Rule: MISRA_C-2012_Rule_10.1 Diff: -2
Rule: MISRA_C-2012_Rule_11.3 Diff: -15
Rule: MISRA_C-2012_Rule_11.5 Diff: 15
Rule: MISRA_C-2012_Rule_12.2 Diff: -2
Rule: MISRA_C-2012_Rule_15.1 Diff: 64
Rule: MISRA_C-2012_Rule_15.4 Diff: 5
Rule: MISRA_C-2012_Rule_15.5 Diff: -76
Rule: MISRA_C-2012_Rule_15.6 Diff: -1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.4 Diff: -1
Rule: MISRA_C-2012_Rule_2.3 Diff: -2
Rule: MISRA_C-2012_Rule_2.4 Diff: -1
Rule: MISRA_C-2012_Rule_2.5 Diff: -106
Rule: MISRA_C-2012_Rule_5.7 Diff: -1
Rule: MISRA_C-2012_Rule_5.9 Diff: -6
Rule: MISRA_C-2012_Rule_8.13 Diff: -18
Rule: MISRA_C-2012_Rule_8.2 Diff: -1
Rule: MISRA_C-2012_Rule_8.3 Diff: -2
Rule: MISRA_C-2012_Rule_8.9 Diff: -2
Rule: Total Diff: -162
*******************CERT report
Analysis summary report:
Defects/Coding rule violations found : 47 Total
	CERT_INT30-C 	 47 - (Deviation Not approved)
	Total 	 47
===== DIFF ======
Total cert violation count changed by -16
Rule: CERT_INT30-C Diff: -16
Rule: Total Diff: -16
*******************CERT ADV report
Analysis summary report:
Defects/Coding rule violations found : 36 Total
	CERT_DCL37-C (Full Deviation) 	 36 - (Deviation Approved)
	Total 	 36
===== DIFF ======
Total cert_adv violation count changed by -76
Rule: CERT_DCL37-C Diff: -62
Rule: CERT_EXP39-C Diff: -14
Rule: Total Diff: -76

JIRA NET-224

Change-Id: I2084da3d98646e6f9fb7933adbee39343e509e8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2744955
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-09 11:15:17 -07:00
Narayan Reddy
28053a560e osi: core: fix misra 2.x rules 
===== DIFF ======
Total misra violation count changed by -591
Rule: MISRA_C-2012_Rule_2.2 Diff: -1
Rule: MISRA_C-2012_Rule_2.3 Diff: -3
Rule: MISRA_C-2012_Rule_2.4 Diff: -2
Rule: MISRA_C-2012_Rule_2.5 Diff: -585
Rule: Total Diff: -591

Bug 3695218

Change-Id: I57e85ba94f434cb3bd729b4f5f75bb4a592fb279
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2768383
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-02 04:58:41 -07:00
Narayan Reddy
f816ebf1e8 osi: core: fix misra 4.6 rule 
===== DIFF ======
Total misra violation count changed by -240
Rule: MISRA_C-2012_Directive_4.6 Diff: -240
Rule: Total Diff: -240

Bug 3695218

Change-Id: Ida2d3a775872637eda3058ea361a00346c86f7f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767895
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-30 00:05:29 -07:00
Narayan Reddy
f971d40513 osi: core: skip out not required code for Safety QNX 
Bug 3701869

Change-Id: Ic1f676708ff6e3faf7dbed09f0e7048448252e57
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739627
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
 2022-08-06 05:04:15 -07:00
Narayan Reddy
21b6f6aeb9 osi: core: Fix MISRA issues 
Fixed straight forward MISRA issues

===== DIFF ======
Total misra violation count changed by -319
Rule: MISRA_C-2012_Directive_4.4 Diff: -3
Rule: MISRA_C-2012_Directive_4.6 Diff: -32
Rule: MISRA_C-2012_Directive_4.9 Diff: 3
Rule: MISRA_C-2012_Rule_10.1 Diff: -4
Rule: MISRA_C-2012_Rule_10.3 Diff: -2
Rule: MISRA_C-2012_Rule_10.4 Diff: -21
Rule: MISRA_C-2012_Rule_11.1 Diff: -20
Rule: MISRA_C-2012_Rule_12.1 Diff: -74
Rule: MISRA_C-2012_Rule_15.5 Diff: 1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -5
Rule: MISRA_C-2012_Rule_2.5 Diff: -157
Rule: MISRA_C-2012_Rule_8.6 Diff: -1
Rule: Total Diff: -319

JIRA NET-96
Bug 3695218

Change-Id: I221f95aaf23e9214fde21632b68425b705552752
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735077
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-06 02:37:19 -07:00
Nagaraj Annaiah
221989d875 osi core: Fix compiler warnings for HVRTOS 
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-21 15:52:01 -07:00
Sanath Kumar Gampa
37ab92517f osi:macsec: Fix osi macsec Misra/coverity issues 
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes

Fix: Fixed the defects by making minor changes without
impacting the functionality

Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write

Bug 3460422

Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-11 13:17:05 -07:00
Rakesh Goyal
288c525a36 nvethenetrm: core: SW WAR implementation for switching of Gates 
Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-28 10:49:29 -08:00
Rakesh Goyal
581b8ad758 dma: mgbe: update RWT and RWUT programming for silicon 
Issue: RWT and RWUT programmed for uFPGA

Fix: Update RWIT programming
     Update minimum rx coalescing timer value

Bug 200767374

Change-Id: I09c21764f0c294021c7546f75351c19c34a0b9db
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2589496
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-09 09:22:28 -07:00
Bhadram Varka
3293a90aba osi: Add core debug for registers/structures 
- Adds core debugging for registers/structures.
- Add change to use single macro for CORE and DMA.

Bug 200737108

Change-Id: If96af2ef0c39e01b6c1dad74ee11fd820df76a8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559319
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-16 16:46:03 -07:00
Bhadram Varka
9cdfd1cefd osi: Update MGBE MAC version 
On uFPGA MGBE MAC version is 0x31 and it got updated
to 0x40 on silicon.

Bug 200751806

Change-Id: Ic9d35b7a36cff158dd17feeddce6267a3ec2a082
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559464
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-15 17:27:56 -07:00
Bhadram Varka
d4e6ad6ec6 osi: use max_chans based on MAC version 
Issue: Maximum number of DMA channels is different for
Xavier/Orin EQOS/MGBE IP's. Using macro of maximum number
of channels will create problem for other IP's.

Fix: Assign maximum number of DMA channels based on MAC version.

Bug 200741194

Change-Id: I321780b6868dfb36700863a5852b76424d3bbf6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556425
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-13 09:22:21 -07:00
Mahesh Patil
d519384bf8 eqos: core: pad calibration 
Issue:
   1. Current pad calibration does not check for RGMII/MDIO
      interfaces idle
Fix:
  1. Make sure RGMII and MDIO interface are idle before
     doing pad calibration as per spec

Bug 2831220

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: I6b3f35017f62444575d16366d9ac31a5c96fecf7
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2321641
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-06 21:57:08 -07:00
Srinivas Ramachandran
3be3b7a90c nvethernetrm: Add support for MACsec controller 
This commit adds support for MACsec controller HW
operations. The MACsec HW ops can be accessed via
osi_core layer.

Currently, MACsec HW is enabled when MAC interface
is brough up, with no LUT entry so that packets
will still be bypassed. MTU check is enabled and
default interrupts are enabled for statistics.

Bug 2913560

Change-Id: I62e8567fac6603db47f4069a40458038f9b4178a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2021-06-21 07:07:10 +05:30