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nv-soc: remove uart and spi definition

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UARTE, SPI1, SPI2 and SPI3 controller definition have moved to
upstream file. These definitions are no longer required.

Bug 4148340
Bug 4130525

Change-Id: Ibef26f9f83ca9509847e348287cfab92d75a1c44
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3019987
(cherry picked from commit ef1ffd96ac)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3020232
Tested-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Gautham Srinivasan
2023-11-21 16:42:03 +00:00
committed by mobile promotions
parent 7b12220c93
commit 1537177f7b
1 changed files with 0 additions and 70 deletions
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70
nv-soc/tegra234-soc-overlay.dtsi
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@@ -209,55 +209,6 @@
status = "disabled";
};
serial@3140000 {
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03140000 0x0 0x10000>;
interrupts = <GIC_SPI TEGRA234_IRQ_UARTE IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_UARTE>;
clock-names = "serial";
resets = <&bpmp TEGRA234_RESET_UARTE>;
reset-names = "serial";
status = "disabled";
};
spi@3210000 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x03210000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_SPI1>;
assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "spi";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
resets = <&bpmp TEGRA234_RESET_SPI1>;
reset-names = "spi";
dmas = <&gpcdma 15>, <&gpcdma 15>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";
};
spi@3230000 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x03230000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_SPI3>;
clock-names = "spi";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_SPI3>;
reset-names = "spi";
dmas = <&gpcdma 17>, <&gpcdma 17>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";
};
tachometer@39c0000 {
compatible = "nvidia,pwm-tegra234-tachometer";
reg = <0x0 0x039c0000 0x0 0x10>;
@@ -822,27 +773,6 @@
};
};
spi@c260000 {
compatible = "nvidia,tegra210-spi";
reg = <0x0 0x0c260000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA234_CLK_SPI2>,
<&bpmp TEGRA234_CLK_PLLAON>,
<&bpmp TEGRA234_CLK_OSC>;
clock-names = "spi";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_SPI2>;
reset-names = "spi";
dmas = <&gpcdma 16>, <&gpcdma 16>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";
};
mttcan@c310000 {
compatible = "nvidia,tegra194-mttcan";
reg = <0x0 0x0c310000 0x0 0x144>,