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t23x: soc: safety: Add FSI multicore support

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Enable FSI multi core support to communicate using CCPLEX fsicom demo
apps. It adds following to enable:
- add top2 hsp mailbox 5 and 4 for core 1 usage
- add FSI_CPU1 stream id for core 1 memory map in AST and SMMU
- new node per FSI core per SMMU instance

Bug 4243457

Change-Id: Id66c060d5daa1ca6458e3cbeee81dafc88904560
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2977860
(cherry picked from commit 4e450ca886 in
dev-main)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2995454
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Dipen Patel
2023-11-14 20:56:16 +00:00
committed by mobile promotions
parent 7dfa45e768
commit 2d0af855ad
2 changed files with 81 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/kernel/dt-bindings/memory/tegra234-mc.h
View File

@@ -171,6 +171,12 @@
#define TEGRA234_SID_HOST1X_CTX6 0x3b #define TEGRA234_SID_HOST1X_CTX6 0x3b
#define TEGRA234_SID_HOST1X_CTX7 0x3c #define TEGRA234_SID_HOST1X_CTX7 0x3c
/*FSI Stream Id*/
#define TEGRA234_SID_NISO1_FSI_CPU0 TEGRA234_SID_FSI
#define TEGRA234_SID_NISO1_FSI_CPU1 0x4BU
#define TEGRA234_SID_NISO1_FSI_CPU2 0x4CU
#define TEGRA234_SID_NISO1_FSI_CPU3 0X4DU
/* /*
* memory client IDs * memory client IDs
*/ */

109
nv-soc/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -3,43 +3,78 @@
#include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
reserved-memory { reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
fsicom_resv: reservation-fsicom { fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>, iommu-addresses = <&fsicom_client 0x0 0x0 0x0 0xf0000000>,
<&fsiccplex_com 0x0 0xf1000000 0xffffffff 0x0effffff>; <&fsicom_client 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
fsicom_resv_inst1: reservation-fsicom_inst1 {
iommu-addresses = <&fsicom_client_inst1 0x0 0x0 0x0 0xf0000000>,
<&fsicom_client_inst1 0x0 0xf1000000 0xffffffff 0x0effffff>;
}; };
}; };
fsiccplex_com:fsicom_client { fsicom_client: fsicom_client {
compatible = "nvidia,tegra234-fsicom-client"; compatible = "nvidia,tegra234-fsicom-client";
#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
mboxes = mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>, <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>; <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>,
mbox-names = "fsi-tx", "fsi-rx"; <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(5)>,
iommus = <&smmu_niso1 TEGRA234_SID_FSI>; <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(4)>;
#else
mboxes =
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(1)>,
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(5)>,
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(4)>;
#endif
mbox-names = "fsi-tx-cpu0", "fsi-rx-cpu0", "fsi-tx-cpu1", "fsi-rx-cpu1";
iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU0>;
memory-region = <&fsicom_resv>; memory-region = <&fsicom_resv>;
dma-coherent; dma-coherent;
#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
enable-deinit-notify;
#endif
smmu_inst = <0>;
max_fsi_core=<1>; /*Value 1 <-> core 0, value 2 <-> core0,1*/
status = "disabled"; status = "disabled";
}; };
safetyservices_epl_client { fsicom_client_inst1: fsicom_client_inst1 {
compatible = "nvidia,tegra234-fsicom-client";
iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU1>;
memory-region = <&fsicom_resv_inst1>;
dma-coherent;
smmu_inst = <1>;
status = "okay";
};
safetyservices_epl_client@110000 {
compatible = "nvidia,tegra234-epl-client"; compatible = "nvidia,tegra234-epl-client";
mboxes = <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>; #if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
#else
mboxes =
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(0)>;
#endif
mbox-names = "epl-tx"; mbox-names = "epl-tx";
reg = <0x0 0x00110000 0x0 0x4>, reg = <0x0 0x00110000 0x0 0x4>,
<0x0 0x00110004 0x0 0x4>, <0x0 0x00110004 0x0 0x4>,
<0x0 0x00120000 0x0 0x4>, <0x0 0x00120000 0x0 0x4>,
<0x0 0x00120004 0x0 0x4>, <0x0 0x00120004 0x0 0x4>,
<0x0 0x00130000 0x0 0x4>, <0x0 0x00130000 0x0 0x4>,
<0x0 0x00130004 0x0 0x4>, <0x0 0x00130004 0x0 0x4>,
<0x0 0x00140000 0x0 0x4>, <0x0 0x00140000 0x0 0x4>,
<0x0 0x00140004 0x0 0x4>, <0x0 0x00140004 0x0 0x4>,
<0x0 0x00150000 0x0 0x4>, <0x0 0x00150000 0x0 0x4>,
<0x0 0x00150004 0x0 0x4>, <0x0 0x00150004 0x0 0x4>,
<0x0 0x024e0038 0x0 0x4>; <0x0 0x024e0038 0x0 0x4>;
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */ /* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
client-misc-sw-generic-err0 = "fsicom_client"; client-misc-sw-generic-err0 = "fsicom_client";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */ /* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
@@ -48,52 +83,56 @@
client-misc-sw-generic-err3 = "gk20d"; client-misc-sw-generic-err3 = "gk20d";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */ /* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
client-misc-sw-generic-err4 = "gk20e"; client-misc-sw-generic-err4 = "gk20e";
#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
enable-deinit-notify;
#endif
status = "disabled"; status = "disabled";
}; };
FsiComIvc { FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels"; compatible = "nvidia,tegra-fsicom-channels";
status = "disabled"; status = "disabled";
nChannel = <7>; nChannel=<7>;
channel_0 { channel_0{
frame-count = <4>; frame-count = <4>;
frame-size = <1024>; frame-size = <1024>;
core-id = <0>;
NvSciCh = "nvfsicom_EPD"; NvSciCh = "nvfsicom_EPD";
}; };
channel_1{
channel_1 {
frame-count = <30>; frame-count = <30>;
frame-size = <64>; frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_CcplexApp"; NvSciCh = "nvfsicom_CcplexApp";
}; };
channel_2{
channel_2 {
frame-count = <4>; frame-count = <4>;
frame-size = <64>; frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_CcplexApp_state_change"; NvSciCh = "nvfsicom_CcplexApp_state_change";
}; };
channel_3{
channel_3 {
frame-count = <4>; frame-count = <4>;
frame-size = <64>; frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_app1"; NvSciCh = "nvfsicom_app1";
}; };
channel_4{
channel_4 {
frame-count = <2>; frame-count = <2>;
frame-size = <512>; frame-size = <64>;
core-id = <1>;
NvSciCh = "nvfsicom_app2"; NvSciCh = "nvfsicom_app2";
}; };
channel_5{
channel_5 {
frame-count = <4>; frame-count = <4>;
frame-size = <64>; frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_appGR"; NvSciCh = "nvfsicom_appGR";
}; };
channel_6{
channel_6 {
frame-count = <4>; frame-count = <4>;
frame-size = <10240>; frame-size = <10240>;
core-id = <0>;
}; };
}; };