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overlay: p3767: enable C4 based on odm data

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Handle alternate ODMDATA configurations related to PCIE EP mode on C4

Bug 4076164
Bug 4052872

Change-Id: Idf8a48f9915d928ed91da9382dd5e793a01cfeb9
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3013330
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Gautham Srinivasan
2023-11-08 20:00:55 +00:00
committed by mobile promotions
parent fb7d1ce43e
commit 4351270491
4 changed files with 59 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
View File

@@ -245,6 +245,18 @@
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
pcie-ep@14160000 {/* C4 - End Point */
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
reset-gpios = <&gpio
TEGRA234_MAIN_GPIO(L, 1)
GPIO_ACTIVE_LOW>;
nvidia,refclk-select-gpios = <&gpio_aon
TEGRA234_AON_GPIO(AA, 4)
GPIO_ACTIVE_HIGH>;
};
/* C8 - Ethernet */
pcie@140a0000 {
status = "okay";

2
overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0003.dts
View File

@@ -39,7 +39,7 @@
max-link-speed = <0x3>;
};
/* C4 End Point */
pcie_ep@14160000 {
pcie-ep@14160000 {
max-link-speed = <0x3>;
};
/* C7 */

2
overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0004.dts
View File

@@ -39,7 +39,7 @@
max-link-speed = <0x3>;
};
/* C4 End Point */
pcie_ep@14160000 {
pcie-ep@14160000 {
max-link-speed = <0x3>;
};
/* C7 */

46
overlay/tegra234-p3767-sku-handling.dtsi
View File

@@ -80,7 +80,7 @@
};
/* C4 End Point */
pcie_ep@14160000 {
pcie-ep@14160000 {
max-link-speed = <0x3>;
};
@@ -129,4 +129,48 @@
};
};
};
/*
* If ODMDATA contains hsio-uphy-config-40, then:
* 1. Disable PCIE C4
* 2. Enable PCIE C4 EP
* 3. Reduce PCIE C1 to Gen2
*/
p3767-sku-handling-fragment@7 {
target-path = "/bus@0";
board_config {
odm-data = "hsio-uphy-config-40";
};
__overlay__ {
pcie@14160000 {
status = "disabled";
};
pcie-ep@14160000 {
status = "okay";
};
pcie@14100000 {
max-link-speed = <2>;
};
};
};
/*
* If ODMDATA contains hsio-uphy-config-41, then:
* 1. Disable PCIE C4
* 2. Enable PCIE C4 EP
*/
p3767-sku-handling-fragment@8 {
target-path = "/bus@0";
board_config {
odm-data = "hsio-uphy-config-41";
};
__overlay__ {
pcie@14160000 {
status = "disabled";
};
pcie-ep@14160000 {
status = "okay";
};
};
};
};