t23x: overlay: remove imx477 4-lane dtbo

Raspberry PI HQ IMX477 only has 2-lanes for camera
cable and connector design, 4-lanes will never work

Bug 5331483

Change-Id: Id8cfe7bc1f4faceec6ceaf2b28aa4b324ca0e599
Signed-off-by: Jerry Chang <jerchang@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3490070
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>

Makefile

@@ -7,6 +7,7 @@ dtbo-y :=
 makefile-path := t23x/nv-public
 
 dtb-y += tegra234-p3737-0000+p3701-0000.dtb
+dtb-y += tegra234-p3737-0000+p3701-0008.dtb
 dtb-y += tegra234-p3740-0002+p3701-0008.dtb
 dtb-y += tegra234-p3768-0000+p3767-0000.dtb
 dtb-y += tegra234-p3768-0000+p3767-0005.dtb

include/platforms/dt-bindings/tegra234-p3737-0000+p3701-0000.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2025, NVIDIA CORPORATION.  All rights reserved.
  *
  * Definitions for Jetson tegra234-p3737-0000-p3701-0000 board.
  */
@@ -43,25 +43,25 @@
 #define HDR40_PIN40	"soc_gpio42_pi0"
 
 /* SoC GPIO definitions for 40-pin header */
-#define HDR40_PIN7_GPIO		TEGRA_MAIN_GPIO(Q, 6)
-#define HDR40_PIN11_GPIO	TEGRA_MAIN_GPIO(R, 4)
-#define HDR40_PIN12_GPIO	TEGRA_MAIN_GPIO(H, 7)
-#define HDR40_PIN13_GPIO	TEGRA_MAIN_GPIO(R, 0)
-#define HDR40_PIN15_GPIO	TEGRA_MAIN_GPIO(N, 1)
-#define HDR40_PIN16_GPIO	TEGRA_AON_GPIO(BB, 0)
-#define HDR40_PIN18_GPIO	TEGRA_MAIN_GPIO(H, 0)
-#define HDR40_PIN19_GPIO	TEGRA_MAIN_GPIO(Z, 5)
-#define HDR40_PIN21_GPIO	TEGRA_MAIN_GPIO(Z, 4)
-#define HDR40_PIN22_GPIO	TEGRA_MAIN_GPIO(P, 4)
-#define HDR40_PIN23_GPIO	TEGRA_MAIN_GPIO(Z, 3)
-#define HDR40_PIN24_GPIO	TEGRA_MAIN_GPIO(Z, 6)
-#define HDR40_PIN26_GPIO	TEGRA_MAIN_GPIO(Z, 7)
-#define HDR40_PIN29_GPIO	TEGRA_AON_GPIO(AA, 1)
-#define HDR40_PIN31_GPIO	TEGRA_AON_GPIO(AA, 0)
-#define HDR40_PIN32_GPIO	TEGRA_AON_GPIO(BB, 1)
-#define HDR40_PIN33_GPIO	TEGRA_AON_GPIO(AA, 2)
-#define HDR40_PIN35_GPIO	TEGRA_MAIN_GPIO(I, 2)
-#define HDR40_PIN36_GPIO	TEGRA_MAIN_GPIO(R, 5)
-#define HDR40_PIN37_GPIO	TEGRA_AON_GPIO(AA, 3)
-#define HDR40_PIN38_GPIO	TEGRA_MAIN_GPIO(I, 1)
-#define HDR40_PIN40_GPIO	TEGRA_MAIN_GPIO(I, 0)
+#define HDR40_PIN7_GPIO		TEGRA234_MAIN_GPIO(Q, 6)
+#define HDR40_PIN11_GPIO	TEGRA234_MAIN_GPIO(R, 4)
+#define HDR40_PIN12_GPIO	TEGRA234_MAIN_GPIO(H, 7)
+#define HDR40_PIN13_GPIO	TEGRA234_MAIN_GPIO(R, 0)
+#define HDR40_PIN15_GPIO	TEGRA234_MAIN_GPIO(N, 1)
+#define HDR40_PIN16_GPIO	TEGRA234_AON_GPIO(BB, 0)
+#define HDR40_PIN18_GPIO	TEGRA234_MAIN_GPIO(H, 0)
+#define HDR40_PIN19_GPIO	TEGRA234_MAIN_GPIO(Z, 5)
+#define HDR40_PIN21_GPIO	TEGRA234_MAIN_GPIO(Z, 4)
+#define HDR40_PIN22_GPIO	TEGRA234_MAIN_GPIO(P, 4)
+#define HDR40_PIN23_GPIO	TEGRA234_MAIN_GPIO(Z, 3)
+#define HDR40_PIN24_GPIO	TEGRA234_MAIN_GPIO(Z, 6)
+#define HDR40_PIN26_GPIO	TEGRA234_MAIN_GPIO(Z, 7)
+#define HDR40_PIN29_GPIO	TEGRA234_AON_GPIO(AA, 1)
+#define HDR40_PIN31_GPIO	TEGRA234_AON_GPIO(AA, 0)
+#define HDR40_PIN32_GPIO	TEGRA234_AON_GPIO(BB, 1)
+#define HDR40_PIN33_GPIO	TEGRA234_AON_GPIO(AA, 2)
+#define HDR40_PIN35_GPIO	TEGRA234_MAIN_GPIO(I, 2)
+#define HDR40_PIN36_GPIO	TEGRA234_MAIN_GPIO(R, 5)
+#define HDR40_PIN37_GPIO	TEGRA234_AON_GPIO(AA, 3)
+#define HDR40_PIN38_GPIO	TEGRA234_MAIN_GPIO(I, 1)
+#define HDR40_PIN40_GPIO	TEGRA234_MAIN_GPIO(I, 0)

include/platforms/dt-bindings/tegra234-p3767-0000-common.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+/* SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
  *
  * Definitions for Jetson tegra234-p3767-0000 board.
  */
@@ -11,7 +10,12 @@
                                         "nvidia,p3768-0000+p3767-0001", \
                                         "nvidia,p3768-0000+p3767-0003", \
                                         "nvidia,p3768-0000+p3767-0004", \
-                                        "nvidia,p3768-0000+p3767-0005"
+                                        "nvidia,p3768-0000+p3767-0005", \
+                                        "nvidia,p3768-0000+p3767-0000-super", \
+                                        "nvidia,p3768-0000+p3767-0001-super", \
+                                        "nvidia,p3768-0000+p3767-0003-super", \
+                                        "nvidia,p3768-0000+p3767-0004-super", \
+                                        "nvidia,p3768-0000+p3767-0005-super"
 
 #define JETSON_COMPATIBLE_P3509		"nvidia,p3509-0000+p3767-0000", \
                                         "nvidia,p3509-0000+p3767-0001", \
@@ -56,25 +60,25 @@
 #define HDR40_PIN40	"soc_gpio42_pi0"
 
 /* SoC GPIO definitions for 40-pin header */
-#define HDR40_PIN7_GPIO		TEGRA_MAIN_GPIO(AC, 6)
-#define HDR40_PIN11_GPIO	TEGRA_MAIN_GPIO(R, 4)
-#define HDR40_PIN12_GPIO	TEGRA_MAIN_GPIO(H, 7)
-#define HDR40_PIN13_GPIO	TEGRA_MAIN_GPIO(Y, 0)
-#define HDR40_PIN15_GPIO	TEGRA_MAIN_GPIO(N, 1)
-#define HDR40_PIN16_GPIO	TEGRA_AON_GPIO(Y, 4)
-#define HDR40_PIN18_GPIO	TEGRA_MAIN_GPIO(Y, 3)
-#define HDR40_PIN19_GPIO	TEGRA_MAIN_GPIO(Z, 5)
-#define HDR40_PIN21_GPIO	TEGRA_MAIN_GPIO(Z, 4)
-#define HDR40_PIN22_GPIO	TEGRA_MAIN_GPIO(Y, 1)
-#define HDR40_PIN23_GPIO	TEGRA_MAIN_GPIO(Z, 3)
-#define HDR40_PIN24_GPIO	TEGRA_MAIN_GPIO(Z, 6)
-#define HDR40_PIN26_GPIO	TEGRA_MAIN_GPIO(Z, 7)
-#define HDR40_PIN29_GPIO	TEGRA_AON_GPIO(Q, 5)
-#define HDR40_PIN31_GPIO	TEGRA_AON_GPIO(Q, 6)
-#define HDR40_PIN32_GPIO	TEGRA_AON_GPIO(G, 6)
-#define HDR40_PIN33_GPIO	TEGRA_AON_GPIO(H, 0)
-#define HDR40_PIN35_GPIO	TEGRA_MAIN_GPIO(I, 2)
-#define HDR40_PIN36_GPIO	TEGRA_MAIN_GPIO(R, 5)
-#define HDR40_PIN37_GPIO	TEGRA_AON_GPIO(Y, 2)
-#define HDR40_PIN38_GPIO	TEGRA_MAIN_GPIO(I, 1)
-#define HDR40_PIN40_GPIO	TEGRA_MAIN_GPIO(I, 0)
+#define HDR40_PIN7_GPIO		TEGRA234_MAIN_GPIO(AC, 6)
+#define HDR40_PIN11_GPIO	TEGRA234_MAIN_GPIO(R, 4)
+#define HDR40_PIN12_GPIO	TEGRA234_MAIN_GPIO(H, 7)
+#define HDR40_PIN13_GPIO	TEGRA234_MAIN_GPIO(Y, 0)
+#define HDR40_PIN15_GPIO	TEGRA234_MAIN_GPIO(N, 1)
+#define HDR40_PIN16_GPIO	TEGRA234_AON_GPIO(Y, 4)
+#define HDR40_PIN18_GPIO	TEGRA234_MAIN_GPIO(Y, 3)
+#define HDR40_PIN19_GPIO	TEGRA234_MAIN_GPIO(Z, 5)
+#define HDR40_PIN21_GPIO	TEGRA234_MAIN_GPIO(Z, 4)
+#define HDR40_PIN22_GPIO	TEGRA234_MAIN_GPIO(Y, 1)
+#define HDR40_PIN23_GPIO	TEGRA234_MAIN_GPIO(Z, 3)
+#define HDR40_PIN24_GPIO	TEGRA234_MAIN_GPIO(Z, 6)
+#define HDR40_PIN26_GPIO	TEGRA234_MAIN_GPIO(Z, 7)
+#define HDR40_PIN29_GPIO	TEGRA234_AON_GPIO(Q, 5)
+#define HDR40_PIN31_GPIO	TEGRA234_AON_GPIO(Q, 6)
+#define HDR40_PIN32_GPIO	TEGRA234_AON_GPIO(G, 6)
+#define HDR40_PIN33_GPIO	TEGRA234_AON_GPIO(H, 0)
+#define HDR40_PIN35_GPIO	TEGRA234_MAIN_GPIO(I, 2)
+#define HDR40_PIN36_GPIO	TEGRA234_MAIN_GPIO(R, 5)
+#define HDR40_PIN37_GPIO	TEGRA234_AON_GPIO(Y, 2)
+#define HDR40_PIN38_GPIO	TEGRA234_MAIN_GPIO(I, 1)
+#define HDR40_PIN40_GPIO	TEGRA234_MAIN_GPIO(I, 0)

nv-platform/Makefile

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
-# SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+# SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 DTC_FLAGS += -@
 
@@ -16,13 +16,18 @@ dtb-y += tegra234-p3737-0000+p3701-0008-nv.dtb
 dtb-y += tegra234-p3740-0002+p3701-0008-nv.dtb
 dtb-y += tegra234-p3740-0002+p3701-0008-nv-safety.dtb
 dtb-y += tegra234-p3768-0000+p3767-0000-nv.dtb
-dtb-y += tegra234-p3768-0000+p3767-0000-nv-px1.dtb
-dtb-y += tegra234-p3768-0000+p3767-0000-nv-taylor-high.dtb
-dtb-y += tegra234-p3768-0000+p3767-0000-nv-taylor-low.dtb
+dtb-y += tegra234-p3768-0000+p3767-0000-nv-super.dtb
 dtb-y += tegra234-p3768-0000+p3767-0001-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0001-nv-super.dtb
 dtb-y += tegra234-p3768-0000+p3767-0003-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0003-nv-super.dtb
 dtb-y += tegra234-p3768-0000+p3767-0004-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0004-nv-super.dtb
 dtb-y += tegra234-p3768-0000+p3767-0005-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0005-nv-super.dtb
+dtb-y += tegra234-p3971-0000+p3701-0000-nv.dtb
+dtb-y += tegra234-p3971-0000+p3701-0008-nv.dtb
+dtb-y += tegra234-p3971-0000+p3701-0008-nv-safety.dtb
 
 ifneq ($(dtb-y),)
 dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))

nv-platform/tegra234-camera-p3785.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include <dt-bindings/clock/tegra234-clock.h>
 
@@ -339,41 +339,6 @@
 
 	tegra-camera-platform {
 		compatible = "nvidia, tegra-camera-platform";
-		/**
-		* Physical settings to calculate max ISO BW
-		*
-		* num_csi_lanes = <>;
-		* Total number of CSI lanes when all cameras are active
-		*
-		* max_lane_speed = <>;
-		* Max lane speed in Kbit/s
-		*
-		* min_bits_per_pixel = <>;
-		* Min bits per pixel
-		*
-		* vi_peak_byte_per_pixel = <>;
-		* Max byte per pixel for the VI ISO case
-		*
-		* vi_bw_margin_pct = <>;
-		* Vi bandwidth margin in percentage
-		*
-		* max_pixel_rate = <>;
-		* Max pixel rate in Kpixel/s for the ISP ISO case
-		*
-		* isp_peak_byte_per_pixel = <>;
-		* Max byte per pixel for the ISP ISO case
-		*
-		* isp_bw_margin_pct = <>;
-		* Isp bandwidth margin in percentage
-		*/
-		num_csi_lanes = <4>;
-		max_lane_speed = <1500000>;
-		min_bits_per_pixel = <10>;
-		vi_peak_byte_per_pixel = <2>;
-		vi_bw_margin_pct = <25>;
-		max_pixel_rate = <750000>;
-		isp_peak_byte_per_pixel = <5>;
-		isp_bw_margin_pct = <25>;
 
 		/**
 		* The general guideline for naming badge_info contains 3 parts, and is as follows,

nv-platform/tegra234-dcb-p3971-0000+p3701-0000.dtsi

@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+/ {
+	display@13800000 {
+		nvidia,dcb-image = [
+			55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49
+			44 45 4f 20 0d 00 00 00 70 01 00 00 00 00 49 42
+			4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65
+			01 00 00 00 10 00 c7 17 31 30 2f 32 36 2f 32 31
+			00 00 00 00 00 00 00 00 21 18 50 00 f1 2a 00 00
+			50 4d 49 44 00 00 00 00 00 00 00 a0 00 b0 00 b8
+			00 c0 00 0e 47 41 31 30 42 20 56 47 41 20 42 49
+			4f 53 0d 0a 00 00 00 00 00 00 00 00 00 00 00 00
+			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+			00 00 00 00 00 56 65 72 73 69 6f 6e 20 39 34 2e
+			30 42 2e 30 30 2e 30 30 2e 32 30 20 0d 0a 00 43
+			6f 70 79 72 69 67 68 74 20 28 43 29 20 31 39 39
+			36 2d 32 30 32 31 20 4e 56 49 44 49 41 20 43 6f
+			72 70 2e 0d 0a 00 00 00 ff ff 00 00 00 00 ff ff
+			47 50 55 20 42 6f 61 72 64 00 00 00 00 00 00 00
+			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+			00 00 00 43 68 69 70 20 52 65 76 20 20 20 00 00
+			00 00 00 00 00 00 00 ba 91 98 96 91 9a 9a 8d 96
+			91 98 df ad 9a 93 9a 9e 8c 9a df d2 df b1 90 8b
+			df b9 90 8d df af 8d 90 9b 8a 9c 8b 96 90 91 df
+			aa 8c 9a f2 f5 ff 00 00 00 00 00 00 00 00 00 00
+			50 43 49 52 de 10 94 22 00 00 18 00 00 00 00 03
+			16 00 01 00 00 80 00 00 2e 8b c0 2e 8b c0 8b c0
+			4e 50 44 45 01 01 14 00 16 00 00 01 00 00 00 00
+			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+			ff b8 42 49 54 00 00 01 0c 06 12 45 32 01 04 00
+			38 02 42 02 25 00 44 02 43 02 2c 00 69 02 44 01
+			04 00 95 02 49 01 24 00 99 02 4d 02 29 00 bd 02
+			4e 00 00 00 00 00 50 02 e8 00 e6 02 53 02 18 00
+			ce 03 54 01 02 00 e6 03 55 01 05 00 ec 03 56 01
+			06 00 f1 03 78 01 08 00 f7 03 64 01 02 00 ff 03
+			70 02 04 00 01 04 75 01 11 00 05 04 69 02 6e 00
+			18 04 45 01 04 00 e8 03 00 00 86 04 86 04 fe 20
+			00 21 f0 2a 00 00 00 00 00 00 00 00 00 00 00 00
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+			00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 00
+			50 b5 00 19 cf 00 28 75 0e 14 89 0e 23 00 01 23
+			23 01 14 ac 0e 28 18 11 00 00 00 00 d4 0e 01 00
+			00 f1 0d c3 0c 00 00 00 00 01 01 00 00 00 00 f4
+			1c 2d 4e 00 00 00 00 00 00 00 00 00 00 00 00 00
+			00 00 92 2d 00 00 00 00 00 00 0b 94 20 00 00 20
+			92 d2 01 58 03 00 00 31 30 2f 32 36 2f 32 31 00
+			00 00 00 00 00 00 00 00 00 00 00 21 01 10 00 00
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+			30 30 30 30 00 00 00 00 00 00 00 00 03 42 00 00
+			b9 78 8f 47 ad 04 4f 3d bf 01 4c 10 55 04 be ee
+			54 33 00 00 00 00 00 00 c5 4c 00 00 00 00 00 00
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+			94 22 00 00 00 00 01 00 44 00 6b 09 00 00 86 04
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+			61 40 00 00 00 10 00 00 00 00 08 23 61 00 80 00
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+			00 00 08 24 61 00 80 00 00 00 80 00 00 00 88 24
+			61 00 80 00 00 00 80 00 00 00 08 25 61 00 80 00
+			00 00 80 00 00 00 88 25 61 00 80 00 00 00 80 00
+			00 00 08 26 61 00 80 00 00 00 80 00 00 00 00 2a
+			13 00 00 00 04 00 00 00 04 00 00 2a 13 00 00 00
+			01 00 00 00 01 00 00 6e 13 00 00 00 04 00 00 00
+			04 00 00 6e 13 00 00 00 01 00 00 00 01 00 4c 00
+			12 00 3f 00 00 00 00 00 00 00 0c 24 02 00 01 00
+			00 00 00 00 00 00 e4 05 02 00 7c 00 00 00 00 00
+			00 00 e4 05 02 00 7c 00 00 00 18 00 00 00 e4 05
+			02 00 7c 00 00 00 0c 00 00 00 e4 05 02 00 7c 00
+			00 00 04 00 00 00 e4 05 02 00 7c 00 00 00 08 00
+			00 00 e4 05 02 00 7c 00 00 00 14 00 00 00 20 0e
+			9a 00 00 00 02 00 00 00 02 00 00 0e 9a 00 00 00
+			02 00 00 00 02 00 00 0e 9a 00 01 00 00 00 01 00
+			00 00 34 c0 61 40 00 00 00 80 00 00 00 00 00 0c
+			82 00 ff ff ff ff 00 00 00 00 00 0c 82 00 01 00
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+			00 00 00 0c 82 00 04 00 00 00 00 00 00 00 00 0c
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+			00 00 00 00 00 00 00 0c 82 00 20 00 00 00 00 00
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+			82 00 ff 00 00 00 00 00 00 00 c0 04 82 00 07 00
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+			00 00 88 80 08 00 00 00 0f 00 00 00 01 00 40 c0
+			08 00 00 00 0c 00 00 00 0c 00 40 c0 08 00 1f 00
+			00 00 00 00 00 00 00 0a 00 00 00 00 f0 1f 00 00
+			00 00 74 09 9a 00 0f 00 00 00 00 00 00 00 e8 73
+			13 00 01 00 00 00 01 00 00 00 0c 06 9a 00 40 00
+			00 00 40 00 00 00 64 00 12 00 40 00 00 00 40 00
+			00 00 04 14 00 00 04 00 00 00 00 00 00 00 04 14
+			00 00 08 00 00 00 08 00 00 00 14 38 82 00 00 00
+			01 00 00 00 01 00 00 0a 00 00 00 00 f0 1f 00 00
+			00 00 0c 14 00 00 01 00 00 00 01 00 00 00 0c 14
+			00 00 02 00 00 00 01 00 00 00 88 54 62 00 00 00
+			01 00 00 00 00 00 88 54 62 00 00 00 02 00 00 00
+			00 00 88 54 62 00 00 00 04 00 00 00 00 00 9c 8b
+			11 00 00 00 00 80 00 00 00 00 14 0c 82 00 01 00
+			00 00 00 00 00 00 14 0c 82 00 02 00 00 00 00 00
+			00 00 14 0c 82 00 04 00 00 00 00 00 00 00 14 0c
+			82 00 08 00 00 00 00 00 00 00 14 0c 82 00 10 00
+			00 00 00 00 00 00 14 0c 82 00 20 00 00 00 00 00
+			00 00 9c 8b 11 00 00 00 00 80 00 00 00 00 10 01
+			82 00 01 00 00 00 00 00 00 00 d4 06 82 00 ff 03
+			00 00 00 00 00 00 14 0c 82 00 3f 00 00 00 01 00
+			00 00 00 14 00 00 02 00 00 00 00 00 00 00 44 c1
+			61 60 01 00 00 00 01 00 00 00 20 87 08 00 04 00
+			00 00 00 00 00 00 40 00 82 00 01 00 00 00 00 00
+			00 00 54 9b 41 00 ff 00 00 00 00 00 00 00 68 9b
+			41 00 03 00 00 00 00 00 00 00 40 80 11 00 02 00
+			00 00 00 00 00 00 04 0c 82 00 01 00 00 00 00 00
+			00 00 04 14 00 00 00 04 00 00 00 00 00 00 34 04
+			82 00 01 00 00 00 00 00 00 00 4c 08 00 01 02 03
+			04 05 06 07 00 01 02 03 04 05 06 07 41 06 24 06
+			00 00 00 07 00 02 bf 00 01 51 00 04 bf 00 02 5e
+			00 01 bf 00 03 52 00 03 bf 00 84 19 00 00 4f 00
+			85 7b 59 98 4f 00 06 ff 00 00 4f 00 07 ff 00 00
+			ef 00 08 ff 00 00 ef 00 09 ff 00 00 ef 00 0a ff
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+			00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 06
+			00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 10
+			08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 08 00 00 00 10 08 00 1e
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 14
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0c
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0a
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 06
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 08 00 00 00 10 08 00 1e
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 14
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0c
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0a
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 06
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 ];
+	};
+};

nv-platform/tegra234-p3701-0000-prod-overlay.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	bus@0 {
@@ -129,54 +129,6 @@
 			};
 		};
 
-		mttcan@c310000 {
-			prod-settings {
-				#prod-cells = <4>;
-				prod_c_can_2m_1m {
-					board {
-						prod = <
-							0 0x00000048 0x00007f00 0x00000000>;            //M_TTCAN_CORE_TDCR_0
-					};
-				};
-				prod_c_can_5m {
-					board {
-						prod = <
-							0 0x00000048 0x00007f00 0x00000600>;            //M_TTCAN_CORE_TDCR_0
-					};
-				};
-				prod_c_can_8m {
-					board {
-						prod = <
-							0 0x00000048 0x00007f00 0x00000400>;            //M_TTCAN_CORE_TDCR_0
-					};
-				};
-			};
-		};
-
-		mttcan@c320000 {
-			prod-settings {
-				#prod-cells = <4>;
-				prod_c_can_2m_1m {
-					board {
-						prod = <
-							0 0x00000048 0x00007f00 0x00000000>;            //M_TTCAN_CORE_TDCR_0
-					};
-				};
-				prod_c_can_5m {
-					board {
-						prod = <
-							0 0x00000048 0x00007f00 0x00000600>;            //M_TTCAN_CORE_TDCR_0
-					};
-				};
-				prod_c_can_8m {
-					board {
-						prod = <
-							0 0x00000048 0x00007f00 0x00000400>;            //M_TTCAN_CORE_TDCR_0
-					};
-				};
-			};
-		};
-
 		spi@3210000 {
 			prod-settings {
 				#prod-cells = <4>;
@@ -207,6 +159,7 @@
 				prod {
 					board {
 						prod = <
+							0 0x00000004 0x00007cff 0x00000004              //QSPI_COMMAND2_0
 							0 0x000001ec 0x01f1f000 0x00a0a000>;            //QSPI_QSPI_COMP_CONTROL_0
 					};
 				};

nv-platform/tegra234-p3701-0000.dtsi

@@ -2,63 +2,12 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "tegra234-p3701-0000-prod-overlay.dtsi"
+#include "nv-soc/tegra234-soc-thermal.dtsi"
+#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
+#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
+#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 
 / {
-	bus@0 {
-		i2c@c240000 {
-			ina3221@40 {
-				compatible = "ti,ina3221";
-				reg = <0x40>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					label = "VDD_GPU_SOC";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "VDD_CPU_CV";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					label = "VIN_SYS_5V0";
-					shunt-resistor-micro-ohms = <2000>;
-					ti,summation-disable;
-				};
-			};
-
-			ina3221@41 {
-				compatible = "ti,ina3221";
-				reg = <0x41>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					status = "disabled";
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "VDDQ_VDD2_1V8AO";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					status = "disabled";
-				};
-			};
-		};
-
-		spi@3270000 {
-			flash@0 {
-				spi-max-frequency = <51000000>;
-				spi-tx-bus-width = <1>;
-				spi-rx-bus-width = <1>;
-			};
-		};
-	};
-
 	bpmp {
 		i2c {
 			vrs@3c {
@@ -73,11 +22,7 @@
 			};
 
 			tegra_tmp451: thermal-sensor@4c {
-				compatible = "ti,tmp451";
-				reg = <0x4c>;
-				vcc-supply = <&vdd_1v8_ao>;
 				#thermal-sensor-cells = <1>;
-				status = "okay";
 			};
 
 			vrs11_1@20 {

nv-platform/tegra234-p3737-0000+p3701-0004-nv.dts

@@ -1,8 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 
-#include "staging/tegra234-p3737-0000+p3701-0004.dts"
+#include "tegra234-p3737-0000+p3701-0000.dts"
 #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
 #include "tegra234-p3701-0000.dtsi"
+
+/ {
+	compatible = "nvidia,p3737-0000+p3701-0004", "nvidia,p3701-0004", "nvidia,tegra234";
+};

nv-platform/tegra234-p3737-0000+p3701-0005-nv.dts

@@ -1,8 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 
-#include "staging/tegra234-p3737-0000+p3701-0005.dts"
+#include "tegra234-p3737-0000+p3701-0000.dts"
 #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
 #include "tegra234-p3701-0005.dtsi"
+
+/ {
+	compatible = "nvidia,p3737-0000+p3701-0005", "nvidia,p3701-0005", "nvidia,tegra234";
+};

nv-platform/tegra234-p3737-0000+p3701-0008-nv.dts

@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 
-#include "staging/tegra234-p3737-0000+p3701-0008.dts"
+#include "tegra234-p3737-0000+p3701-0008.dts"
 #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
 #include "tegra234-p3701-0008.dtsi"

nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi

@@ -2,10 +2,6 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "nv-soc/tegra234-overlay.dtsi"
-#include "nv-soc/tegra234-soc-thermal.dtsi"
-#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
-#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
-#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 #include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
 #include "nv-soc/tegra234-soc-camera.dtsi"
 #include "tegra234-p3737-0000.dtsi"
@@ -36,40 +32,6 @@
 		status = "okay";
 	};
 
-	thermal-zones {
-		cpu-thermal {
-			status = "okay";
-		};
-
-		cv0-thermal {
-			status = "okay";
-		};
-
-		cv1-thermal {
-			status = "okay";
-		};
-
-		cv2-thermal {
-			status = "okay";
-		};
-
-		gpu-thermal {
-			status = "okay";
-		};
-
-		soc0-thermal {
-			status = "okay";
-		};
-
-		soc1-thermal {
-			status = "okay";
-		};
-
-		soc2-thermal {
-			status = "okay";
-		};
-	};
-
 	bus@0 {
 		smmu_test {
 			compatible = "nvidia,smmu_test";
@@ -242,10 +204,6 @@
 				status = "okay";
 			};
 
-			crypto@15810000 {
-				status = "okay";
-			};
-
 			crypto@15820000 {
 				status = "okay";
 			};
@@ -303,6 +261,12 @@
 			};
 		};
 
+		pcie@14100000 {
+			nvidia,pex-wake-gpios = <&gpio
+							TEGRA234_MAIN_GPIO(Z, 2)
+							GPIO_ACTIVE_LOW>;
+		};
+
 		gpu@17000000 {
 			status = "okay";
 		};

nv-platform/tegra234-p3740-0002+p3701-0008-nv-common.dtsi

@@ -2,10 +2,6 @@
 // SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "nv-soc/tegra234-overlay.dtsi"
-#include "nv-soc/tegra234-soc-thermal.dtsi"
-#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
-#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
-#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 #include "nv-soc/tegra234-soc-camera.dtsi"
 #include "tegra234-camera-p3785.dtsi"
 #include "tegra234-p3740-0002.dtsi"
@@ -21,12 +17,6 @@
 		bootargs = "console=ttyTCU0,115200n8";
 	};
 
-	bpmp {
-		thermal {
-			status = "okay";
-		};
-	};
-
 	cpus {
 		idle-states {
 			c7 {
@@ -45,8 +35,6 @@
 
 	thermal-zones {
 		cpu-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -55,8 +43,6 @@
 		};
 
 		cv0-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -65,8 +51,6 @@
 		};
 
 		cv1-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -75,8 +59,6 @@
 		};
 
 		cv2-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -85,8 +67,6 @@
 		};
 
 		gpu-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -95,8 +75,6 @@
 		};
 
 		soc0-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -105,8 +83,6 @@
 		};
 
 		soc1-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -115,18 +91,12 @@
 		};
 
 		soc2-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
 				};
 			};
 		};
-
-		tj-thermal {
-			status = "okay";
-		};
 	};
 
 	bus@0 {
@@ -261,10 +231,6 @@
 				status = "okay";
 			};
 
-			crypto@15810000 {
-				status = "okay";
-			};
-
 			crypto@15820000 {
 				status = "okay";
 			};
@@ -322,18 +288,6 @@
 			};
 		};
 
-		pcie@141a0000 {
-			reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
-			       0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
-			       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
-			       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
-			       0x2e 0x20000000 0x0 0x10000000>; /* ECAM (256MB)               */
-
-			ranges = <0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000      /* downstream I/O (1MB) */
-			          0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000      /* non-prefetchable memory (128MB) */
-			          0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000>;    /* prefetchable memory (25088MB) */
-		};
-
 		gpu@17000000 {
 			status = "okay";
 		};

nv-platform/tegra234-p3740-0002+p3701-0008-nv-safety.dts

@@ -1,6 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0-only
 // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
+//
+// ### WARNING ###
+// DO NOT ENABLE TPM DEVICE IN THE IGX DEVICE TREE
+// IF NEEDED, PLEASE REACH OUT TO THE NVIDIA IGX PRODUCT TEAM
+// IT IS ILLEGAL TO ENABLE TPM FOR DEVICE GETTING SHIPPED TO CHINA
+
 /dts-v1/;
 
 #include "tegra234-p3740-0002+p3701-0008.dts"

nv-platform/tegra234-p3740-0002+p3701-0008-nv.dts

@@ -1,6 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0-only
 // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
+// 
+// ### WARNING ###
+// DO NOT ENABLE TPM DEVICE IN THE IGX DEVICE TREE
+// IF NEEDED, PLEASE REACH OUT TO THE NVIDIA IGX PRODUCT TEAM
+// IT IS ILLEGAL TO ENABLE TPM FOR DEVICE GETTING SHIPPED TO CHINA
+
 /dts-v1/;
 
 #include "tegra234-p3740-0002+p3701-0008.dts"

nv-platform/tegra234-p3740-0002.dtsi

@@ -6,6 +6,10 @@
 / {
 	bus@0 {
 		i2c@31c0000 {
+			audio-codec@1c {
+				#sound-dai-cells = <1>;
+			};
+
 			typec: stusb1600@28 {
 				status = "okay";
 				compatible = "st,stusb1600";
@@ -31,32 +35,7 @@
 		};
 
 		i2c@c250000 {
-			ina3221@41 {
-				compatible = "ti,ina3221";
-				reg = <0x41>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					label = "CVB_ATX_12V";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "CVB_ATX_3V3";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					label = "CVB_ATX_5V";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-			};
-
-			ina219@44 {
-				compatible = "ti,ina219";
-				reg = <0x44>;
-				shunt-resistor = <2000>;
+			power-sensor@44 {
 				label = "CVB_ATX_12V_8P";
 			};
 

nv-platform/tegra234-p3767-0000.dtsi

@@ -1,12 +1,28 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include <dt-bindings/gpio/tegra234-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt/tegra234-irq.h>
+#include "nv-soc/tegra234-soc-thermal.dtsi"
+#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
+#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
+#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 
 / {
 	bus@0 {
+		spi@3270000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					board {
+						prod = <
+							0 0x00000004 0x000000ff 0x00000004>;            //SPI_COMMAND2_0
+					};
+				};
+			};
+		};
+
 		mmc@3400000 {
 			no-sdio;
 			no-mmc;

nv-platform/tegra234-p3768-0000+p3767-0000-nv-px1.dts

@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-/dts-v1/;
-
-#include "tegra234-p3768-0000+p3767-0000-nv.dts"
-
-/ {
-	compatible = "nvidia,p3768-0000+p3767-0000-px1", "nvidia,p3767-0000", "nvidia,tegra234";
-	model = "NVIDIA Orin NX PX1 Developer Kit";
-
-	bus@0 {
-		host1x@13e00000 {
-			nvdla1@158c0000 {
-				status = "disabled";
-			};
-		};
-
-		pcie@140a0000 { /* C8 - Ethernet */
-			status = "disabled";
-		};
-	};
-};

nv-platform/tegra234-p3768-0000+p3767-0000-nv-super.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0000-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0000-super", "nvidia,p3767-0000", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit Super";
+};

nv-platform/tegra234-p3768-0000+p3767-0000-nv-taylor-high.dts

@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "tegra234-p3768-0000+p3767-0000-nv.dts"
-
-/ {
-	compatible = "nvidia,p3768-0000+p3767-0000-taylor-high", "nvidia,p3767-0000", "nvidia,tegra234";
-	model = "NVIDIA Jetson Orin NX Taylor High";
-};

nv-platform/tegra234-p3768-0000+p3767-0000-nv-taylor-low.dts

@@ -1,9 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "tegra234-p3768-0000+p3767-0000-nv.dts"
-
-/ {
-	compatible = "nvidia,p3768-0000+p3767-0000-taylor-low", "nvidia,p3767-0000", "nvidia,tegra234";
-	model = "NVIDIA Jetson Orin NX Taylor Low";
-};

nv-platform/tegra234-p3768-0000+p3767-0001-nv-super.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0001-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0001-super", "nvidia,p3767-0001", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit Super";
+};

nv-platform/tegra234-p3768-0000+p3767-0001-nv.dts

@@ -1,7 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 
-#include "staging/tegra234-p3768-0000+p3767-0001.dts"
+#include "tegra234-p3768-0000+p3767-0000.dts"
 #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0001", "nvidia,p3767-0001", "nvidia,tegra234";
+};

nv-platform/tegra234-p3768-0000+p3767-0003-nv-super.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0003-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0003-super", "nvidia,p3767-0003", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super";
+};
+
+/delete-node/ &{/opp-table-cluster0/opp-1510400000};
+/delete-node/ &{/opp-table-cluster1/opp-1510400000};
+/delete-node/ &{/opp-table-cluster2/opp-1510400000};

nv-platform/tegra234-p3768-0000+p3767-0003-nv.dts

@@ -1,12 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 
-#include "staging/tegra234-p3768-0000+p3767-0003.dts"
+#include "tegra234-p3768-0000+p3767-0005.dts"
 #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
 
 / {
+	compatible = "nvidia,p3768-0000+p3767-0003", "nvidia,p3767-0003", "nvidia,tegra234";
+
 	bus@0 {
 		host1x@13e00000 {
 			nvdla0@15880000 {

nv-platform/tegra234-p3768-0000+p3767-0004-nv-super.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0004-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0004-super", "nvidia,p3767-0004", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super";
+};
+
+/delete-node/ &{/opp-table-cluster0/opp-1510400000};
+/delete-node/ &{/opp-table-cluster1/opp-1510400000};
+/delete-node/ &{/opp-table-cluster2/opp-1510400000};

nv-platform/tegra234-p3768-0000+p3767-0004-nv.dts

@@ -1,12 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 
-#include "staging/tegra234-p3768-0000+p3767-0004.dts"
+#include "tegra234-p3768-0000+p3767-0005.dts"
 #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
 
 / {
+	compatible = "nvidia,p3768-0000+p3767-0004", "nvidia,p3767-0004", "nvidia,tegra234";
+
 	bus@0 {
 		host1x@13e00000 {
 			nvdla0@15880000 {

nv-platform/tegra234-p3768-0000+p3767-0005-nv-super.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0005-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0005-super", "nvidia,p3767-0005", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super";
+};
+
+/delete-node/ &{/opp-table-cluster0/opp-1510400000};
+/delete-node/ &{/opp-table-cluster1/opp-1510400000};
+/delete-node/ &{/opp-table-cluster2/opp-1510400000};

nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi

@@ -2,10 +2,6 @@
 // SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "nv-soc/tegra234-overlay.dtsi"
-#include "nv-soc/tegra234-soc-thermal.dtsi"
-#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
-#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
-#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 #include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
 #include "tegra234-p3768-0000.dtsi"
 #include "tegra234-p3767-0000.dtsi"
@@ -103,18 +99,6 @@
 			};
 		};
 
-		serial@3100000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		serial@3140000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
 		i2c@3180000 {
 			status = "okay";
 		};
@@ -192,27 +176,6 @@
 
 		i2c@c240000 {
 			status = "okay";
-			ina32211_1_40: ina3221@40 {
-				compatible = "ti,ina3221";
-				reg = <0x40>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					label = "VDD_IN";
-					shunt-resistor-micro-ohms = <5000>;
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "VDD_CPU_GPU_CV";
-					shunt-resistor-micro-ohms = <5000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					label = "VDD_SOC";
-					shunt-resistor-micro-ohms = <5000>;
-				};
-			};
 			fusb301@25 {
 				compatible = "onsemi,fusb301";
 				reg = <0x25>;
@@ -231,18 +194,6 @@
 			};
 		};
 
-		pcie-ep@14160000 {/* C4 - End Point */
-			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
-					<&p2u_hsio_7>;
-			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
-			reset-gpios = <&gpio
-					TEGRA234_MAIN_GPIO(L, 1)
-					GPIO_ACTIVE_LOW>;
-			nvidia,refclk-select-gpios = <&gpio_aon
-							TEGRA234_AON_GPIO(AA, 4)
-							GPIO_ACTIVE_HIGH>;
-		};
-
 		/* PWM1, 40pin header, pin 15 */
 		pwm@3280000 {
 			status = "okay";
@@ -303,6 +254,14 @@
 				status = "okay";
 			};
 
+			crypto@15820000 {
+				status = "okay";
+			};
+
+			crypto@15840000 {
+				status = "okay";
+			};
+
 			nvdla0@15880000 {
 				status = "okay";
 			};
@@ -359,6 +318,10 @@
 				status = "okay";
 			};
 		};
+
+		pcie@14100000 {
+			nvidia,pex-wake-gpios = <&gpio TEGRA234_MAIN_GPIO(L, 2) GPIO_ACTIVE_LOW>;
+		};
 	};
 
 	cpus {
@@ -377,40 +340,6 @@
 		status = "okay";
 	};
 
-	thermal-zones {
-		cpu-thermal {
-			status = "okay";
-		};
-
-		gpu-thermal {
-			status = "okay";
-		};
-
-		cv0-thermal {
-			status = "okay";
-		};
-
-		cv1-thermal {
-			status = "okay";
-		};
-
-		cv2-thermal {
-			status = "okay";
-		};
-
-		soc0-thermal {
-			status = "okay";
-		};
-
-		soc1-thermal {
-			status = "okay";
-		};
-
-		soc2-thermal {
-			status = "okay";
-		};
-	};
-
 	dce@d800000 {
 		status = "okay";
 	};

nv-platform/tegra234-p3971-0000+p3701-0000-nv.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+#include "../tegra234-p3701-0000.dtsi"
+#include "tegra234-p3701-0000.dtsi"
+#include "tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi"
+
+/ {
+        model = "NVIDIA p3971-0000+p3701-0000";
+        compatible = "nvidia,p3971-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
+
+};

nv-platform/tegra234-p3971-0000+p3701-0008-nv-safety.dts

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "tegra234-p3971-0000+p3701-0008-nv.dts"
+#include "tegra234-p3740-0002+p3701-0008-safety.dtsi"
+
+/ {
+	compatible = "nvidia,p3971-0000+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
+
+};

nv-platform/tegra234-p3971-0000+p3701-0008-nv.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+#include "../tegra234-p3701-0008.dtsi"
+#include "tegra234-p3701-0008.dtsi"
+#include "tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi"
+
+/ {
+        model = "NVIDIA p3971-0000+p3701-0008";
+        compatible = "nvidia,p3971-0000+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
+
+};

nv-platform/tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi

@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-overlay.dtsi"
+#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
+#include "nv-soc/tegra234-soc-camera.dtsi"
+
+#include "tegra234-p3971-0000.dtsi"
+
+/ {
+	aliases {
+		serial0 = &tcu;
+		serial1 = &uarta;
+	};
+
+	serial {
+		status = "okay";
+	};
+
+	bus@0 {
+		mc-hwpm@2c10000 {
+			status = "okay";
+		};
+
+		serial@3100000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+		};
+
+		i2c@3180000 {
+			status = "okay";
+		};
+
+		i2c@3190000 {
+			status = "okay";
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+
+		};
+
+		i2c@31e0000 {
+			status = "okay";
+		};
+
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-0 {
+							status = "okay";
+						};
+
+						usb2-1 {
+							status = "okay";
+						};
+
+						usb2-2 {
+							status = "okay";
+						};
+
+						usb2-3 {
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							status = "okay";
+						};
+
+						usb3-1 {
+							status = "okay";
+						};
+
+						usb3-2 {
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					mode = "otg";
+					vbus-supply = <&vdd_5v0_sys>;
+					usb-role-switch;
+					role-switch-default-mode = "peripheral";
+					status = "okay";
+				};
+
+				usb2-1 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb2-2 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <0>;
+					status = "okay";
+				};
+
+				usb3-1 {
+					nvidia,usb2-companion = <3>;
+					status = "okay";
+				};
+
+				usb3-2 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3550000 {
+			status = "okay";
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>;
+			phy-names = "usb2-0", "usb3-0";
+		};
+
+		usb@3610000 {
+			status = "okay";
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", "usb3-1", "usb3-2";
+		};
+
+		hardware-timestamp@3aa0000 {
+			status = "okay";
+		};
+
+		hsp@3c00000 {
+			status = "okay";
+		};
+
+		hsp@c150000 {
+			status = "okay";
+		};
+
+		hardware-timestamp@c1e0000 {
+			status = "okay";
+		};
+
+		i2c@c240000 {
+			status = "okay";
+		};
+
+		i2c@c250000 {
+			status = "okay";
+		};
+
+		mttcan@c310000 {
+			status = "okay";
+		};
+
+		mttcan@c320000 {
+			status = "okay";
+		};
+
+		actmon@d230000 {
+			status = "okay";
+		};
+
+		hwpm@f100000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			nvjpg@15380000 {
+				status = "okay";
+			};
+
+			nvdec@15480000 {
+				status = "okay";
+			};
+
+			nvenc@154c0000 {
+				status = "okay";
+			};
+
+			tsec@15500000 {
+				status = "okay";
+			};
+
+			nvjpg@15540000 {
+				status = "okay";
+			};
+
+			se@15810000 {
+				status = "okay";
+			};
+
+			se@15820000 {
+				status = "okay";
+			};
+
+			se@15840000 {
+				status = "okay";
+			};
+
+			nvdla0@15880000 {
+				status = "okay";
+			};
+
+			nvdla1@158c0000 {
+				status = "okay";
+			};
+
+			ofa@15a50000 {
+				status = "okay";
+			};
+
+			pva0@16000000 {
+				status = "okay";
+
+				pva0_niso1_ctx0 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx1 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx2 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx3 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx4 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx5 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx6 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx7 {
+					status = "okay";
+				};
+			};
+		};
+
+		gpu@17000000 {
+			status = "okay";
+		};
+	};
+
+	tegra-hsp@b950000 {
+		status = "okay";
+	};
+
+	dce@d800000 {
+		status = "okay";
+	};
+
+	tegra_mce@e100000 {
+		status = "okay";
+	};
+
+	display@13800000 {
+		status = "okay";
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "okay";
+			};
+		};
+	};
+
+	nvpmodel {
+		status = "okay";
+	};
+
+	soctherm-oc-event {
+		status = "okay";
+	};
+
+	sound {
+		status = "okay";
+		compatible = "nvidia,tegra186-audio-graph-card",
+			   "nvidia,tegra186-ape";
+		clocks = <&bpmp TEGRA234_CLK_PLLA>,
+		       <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+		       <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		clock-names = "pll_a", "plla_out0", "extern1";
+		assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+
+		nvidia-audio-card,name = "NVIDIA IGX500 Orin APE";
+
+		nvidia-audio-card,mclk-fs = <256>;
+
+		nvidia-audio-card,widgets =
+			"Headphone",    "CVB-RT Headphone Jack",
+			"Microphone",   "CVB-RT Mic Jack",
+			"Microphone",   "CVB-RT Int Mic";
+
+		nvidia-audio-card,routing =
+			"CVB-RT Headphone Jack",     "CVB-RT HPOL",
+			"CVB-RT Headphone Jack",     "CVB-RT HPOR",
+			"CVB-RT IN1P",               "CVB-RT Mic Jack",
+			"CVB-RT IN2P",               "CVB-RT Mic Jack",
+			"CVB-RT DMIC1",              "CVB-RT Int Mic",
+			"CVB-RT DMIC2",              "CVB-RT Int Mic";
+
+		/* I2S4 dai node */
+		nvidia-audio-card,dai-link@79 {
+			link-name = "rt5640-playback";
+			codec {
+				sound-dai = <&rt5640 0>;
+				prefix = "CVB-RT";
+			};
+		};
+	};
+};

nv-platform/tegra234-p3971-0000.dtsi

@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include "tegra234-dcb-p3971-0000+p3701-0000.dtsi"
+#include <dt-bindings/sound/rt5640.h>
+
+/ {
+	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901300 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		hda@3510000 {
+			nvidia,model = "NVIDIA IGX500 Orin HDA";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@56 {
+				compatible = "atmel,24c02";
+				reg = <0x56>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_cvb>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			tsec@15500000 {
+				status = "okay";
+			};
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+
+			rt5640: audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+
+				/* Codec IRQ output */
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+
+				#sound-dai-cells = <1>;
+				sound-name-prefix = "CVB-RT";
+
+				status = "okay";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s4_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+		};
+
+		/* SPI1 in 40 pin conn */
+		spi@3210000 {
+			status = "okay";
+			spi@0 { /* chip select 0 */
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+			};
+
+			spi@1 { /* chips select 1 */
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		/* SPI3 is connected to Aurix */
+		spi@3230000 {
+			status = "disabled";
+		};
+
+		pwm@3280000 {
+			status = "okay";
+		};
+
+
+		pwm@32f0000 {
+			status = "okay";
+		};
+
+		/* Enable fan PWM */
+		pwm@32a0000 {
+			status = "okay";
+		};
+
+		/*
+		 * This is on 40-pin header (pin-18)
+		 * On Orin, the pad control configures it as GPIO/SDMMC.
+		 * No pwm support.
+		 */
+		pwm@32c0000 {
+			status = "disabled";
+		};
+
+		tachometer@39c0000 {
+			status = "okay";
+		};
+
+		pcie@14100000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_hsio_3>;
+			phy-names = "p2u-0";
+		};
+
+		pcie@14160000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+			     <&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+		};
+
+		pcie@141a0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+			     <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+			     <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				"p2u-5", "p2u-6", "p2u-7";
+		};
+
+		pcie@141e0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_gbe_0>, <&p2u_gbe_1>, <&p2u_gbe_2>, <&p2u_gbe_3>,
+			     <&p2u_gbe_4>, <&p2u_gbe_5>, <&p2u_gbe_6>, <&p2u_gbe_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				"p2u-5", "p2u-6", "p2u-7";
+		};
+
+		ufshci@2500000 {
+			status = "okay";
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+        display@13800000 {
+                status = "okay";
+        };
+
+	eeprom-manager {
+		data-size = <0x100>;
+		bus@0 {
+			i2c-bus = <&gen1_i2c>;
+			eeprom@1 {
+				slave-address = <0x56>;
+				label = "cvb";
+			};
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm3 0 45334>;
+		#cooling-cells = <2>;
+	};
+
+	/* fan_nvme is no-stuff, same PWM instance is routed to 40-pin header */
+	fan_nvme: pwm-fan-nvme {
+		compatible = "pwm-fan";
+		pwms = <&pwm8 0 45334>;
+		#cooling-cells = <2>;
+		status = "disabled";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-force-recovery {
+			label = "Force Recovery";
+			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <BTN_1>;
+		};
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_POWER>;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+			wakeup-source;
+		};
+	};
+
+	vcc_src_20v_cvb: regulator-vcc-src-fet {
+		compatible = "regulator-fixed";
+		reg = <1>;
+		regulator-name = "VCC_SRC_FET";
+		regulator-min-microvolt = <20000000>;
+		regulator-max-microvolt = <20000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_5v_cvb: vdd_5v_ao_cvb: regulator-vdd-5v-ao {
+		compatible = "regulator-fixed";
+		reg = <2>;
+		regulator-name = "VDD_5V_AO";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_cbv: regulator-vdd-3v3 {
+		compatible = "regulator-fixed";
+		reg = <3>;
+		regulator-name = "VDD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_3v3_ao_cvb: regulator-vdd-3v3-ao {
+		compatible = "regulator-fixed";
+		reg = <4>;
+		regulator-name = "VDD_3V3_AO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_cvb: regulator-vdd-1v8 {
+		compatible = "regulator-fixed";
+		reg = <5>;
+		regulator-name = "VDD_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vdd_12v_cvb: regulator-vdd-12v {
+		compatible = "regulator-fixed";
+		reg = <6>;
+		regulator-name = "VDD_12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_dp_en: regulator-vdd-3v3-dp-en {
+		compatible = "regulator-fixed";
+		reg = <7>;
+		regulator-name = "VDD_3V3_DP_EN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		enable-active-high;
+	};
+
+	sound {
+		status = "okay";
+
+		compatible = "nvidia,tegra186-audio-graph-card";
+
+		dais = /* ADMAIF (FE) Ports */
+		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+		       /* XBAR Ports */
+		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+		       <&xbar_i2s6_port>, <&xbar_dmic3_port>,
+		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+		       <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
+		       <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
+		       <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
+		       <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
+		       <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
+		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
+		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
+		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
+		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
+		       /* HW accelerators */
+		       <&sfc1_out_port>, <&sfc2_out_port>,
+		       <&sfc3_out_port>, <&sfc4_out_port>,
+		       <&mvc1_out_port>, <&mvc2_out_port>,
+		       <&amx1_out_port>, <&amx2_out_port>,
+		       <&amx3_out_port>, <&amx4_out_port>,
+		       <&adx1_out1_port>, <&adx1_out2_port>,
+		       <&adx1_out3_port>, <&adx1_out4_port>,
+		       <&adx2_out1_port>, <&adx2_out2_port>,
+		       <&adx2_out3_port>, <&adx2_out4_port>,
+		       <&adx3_out1_port>, <&adx3_out2_port>,
+		       <&adx3_out3_port>, <&adx3_out4_port>,
+		       <&adx4_out1_port>, <&adx4_out2_port>,
+		       <&adx4_out3_port>, <&adx4_out4_port>,
+		       <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
+		       <&mix_out4_port>, <&mix_out5_port>,
+		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
+		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
+		       /* BE I/O Ports */
+		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
+		       <&dmic3_port>;
+
+		label = "NVIDIA IGX500 Orin APE";
+
+		widgets = "Microphone",	"CVB-RT MIC Jack",
+			  "Microphone",	"CVB-RT MIC",
+			  "Headphone",	"CVB-RT HP Jack",
+			  "Speaker",	"CVB-RT SPK";
+
+		routing = /* I2S4 <-> RT5640 */
+			  "CVB-RT AIF1 Playback",	"I2S4 DAP-Playback",
+			  "I2S4 DAP-Capture",		"CVB-RT AIF1 Capture",
+			  /* RT5640 codec controls */
+			  "CVB-RT HP Jack",		"CVB-RT HPOL",
+			  "CVB-RT HP Jack",		"CVB-RT HPOR",
+			  "CVB-RT IN1P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2N",		"CVB-RT MIC Jack",
+			  "CVB-RT IN3P",		"CVB-RT MIC Jack",
+			  "CVB-RT SPK",			"CVB-RT SPOLP",
+			  "CVB-RT SPK",			"CVB-RT SPORP",
+			  "CVB-RT SPK",			"CVB-RT LOUTL",
+			  "CVB-RT SPK",			"CVB-RT LOUTR",
+			  "CVB-RT DMIC1",		"CVB-RT MIC",
+			  "CVB-RT DMIC2",		"CVB-RT MIC";
+	};
+};

nv-soc/tegra234-base-overlay.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 // This file contains the additional parameters which are missing from DT nodes of T234
 // available in base/tegra234.dtsi
@@ -37,6 +37,26 @@
 	};
 
 	bus@0 {
+		usb@3610000 {
+			/delete-property/ interrupts;
+			interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 76 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 78 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 82 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			   wake0, wake1, wake2 are for USB3.0 ports
+			   wake3, wake4, wake5, wake6 are for USB2.0 ports
+			*/
+			interrupt-names = "xhci", "mbox",
+				  "wake0", "wake1", "wake2", "wake3",
+				  "wake4", "wake5", "wake6";
+		};
+
 		pcie@140a0000 {
 			iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>;
 		};
@@ -420,24 +440,20 @@
 			dma-names = "rx", "tx";
 			dma-coherent;
 			iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
+					  <&bpmp TEGRA234_CLK_QSPI0_PM>;
+			assigned-clock-rates = <199999999 99999999>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
 		};
 
 		hardware-timestamp@3aa0000 {
 			status = "disabled";
 		};
 
-		sce-fabric@b600000 {
-			status = "disabled";
-		};
-
 		hardware-timestamp@c1e0000 {
 			status = "disabled";
 		};
 
-		dce-fabric@de00000 {
-			compatible = "nvidia,tegra234-dce-fabric";
-		};
-
 		i2c@3160000 {
 			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
 			dma-coherent;

nv-soc/tegra234-soc-overlay.dtsi

@@ -637,7 +637,6 @@
 			};
 
 			crypto@15820000 {
-				compatible = "nvidia,tegra234-se2-aes", "nvidia,tegra234-se-aes";
 				clock-names = "se";
 				interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
 						<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
@@ -647,7 +646,6 @@
 			};
 
 			crypto@15840000 {
-				compatible = "nvidia,tegra234-se4-hash", "nvidia,tegra234-se-hash";
 				clock-names = "se";
 				interconnects = <&mc TEGRA234_MEMORY_CLIENT_SESRD &emc>,
 						<&mc TEGRA234_MEMORY_CLIENT_SESWR &emc>;
@@ -857,39 +855,12 @@
 		};
 
 		pcie-ep@14160000 {
-			compatible = "nvidia,tegra234-pcie-ep";
-			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
-			reg = <0x00 0x14160000 0x0 0x00020000     /* appl registers (128K)      */
-				0x00 0x36040000 0x0 0x00040000    /* iATU_DMA reg space (256K)  */
-				0x00 0x36080000 0x0 0x00040000    /* DBI space (256K)           */
-				0x21 0x40000000 0x3 0x00000000>;  /* Address Space (12G)        */
-			reg-names = "appl", "atu_dma", "dbi", "addr_space";
-			num-lanes = <4>;
-			clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
-			clock-names = "core";
-			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
-			       <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
-			reset-names = "apb", "core";
-
 			pinctrl-names = "default";
 			pinctrl-0 = <&pex_rst_c4_in_state>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
-			interrupt-names = "intr";
-			nvidia,bpmp = <&bpmp 4>;
-			nvidia,enable-ext-refclk;
-			nvidia,aspm-cmrt-us = <60>;
-			nvidia,aspm-pwr-on-t-us = <20>;
-			nvidia,aspm-l0s-entrance-latency-us = <3>;
 
 			nvidia,host1x = <&host1x>;
 			num-ib-windows = <2>;
 			num-ob-windows = <8>;
-			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
-				      <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
-			interconnect-names = "dma-mem", "write";
-			iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
-			dma-coherent;
-			status = "disabled";
 		};
 
 		pcie-ep@141a0000 {

nv-soc/tegra234-soc-prod-overlay.dtsi

@@ -438,6 +438,54 @@
 			};
 		};
 
+		mttcan@c310000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_can_2m_1m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000000>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_5m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000600>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_8m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000400>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+			};
+		};
+
+		mttcan@c320000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_can_2m_1m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000000>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_5m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000600>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_8m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000400>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+			};
+		};
+
 		spi@3210000 {
 			prod-settings {
 				#prod-cells = <4>;

nv-soc/tegra234-soc-thermal.dtsi

@@ -6,46 +6,64 @@
 / {
 	thermal-zones {
 		cpu-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		gpu-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		cv0-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		cv1-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		cv2-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		soc0-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		soc1-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		soc2-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		tj-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};

overlay/Makefile

@@ -41,13 +41,14 @@ dtbo-y += tegra234-p3740-0002+p3701-0008-hdr20.dtbo
 dtbo-y += tegra234-p3740-0002+p3701-0008-m2ke.dtbo
 dtbo-y += tegra234-p3740-0002+p3701-0008-m2kb.dtbo
 dtbo-y += tegra234-p3740-0002-p3701-0008-csi.dtbo
+dtbo-y += tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dtbo
+dtbo-y += tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-dual-imx274-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-e3331-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-e3333-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-imx185-overlay.dtbo
 dtbo-y += tegra234-p3767-camera-p3768-imx219-dual.dtbo
 dtbo-y += tegra234-p3767-camera-p3768-imx477-dual.dtbo
-dtbo-y += tegra234-p3767-camera-p3768-imx477-dual-4lane.dtbo
 dtbo-y += tegra234-p3767-camera-p3768-imx477-imx219.dtbo
 dtbo-y += tegra234-p3737-camera-eCAM130A-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-dual-hawk-ar0234-e3653-overlay.dtbo

overlay/tegra234-camera-ar0234-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2018-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2018-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -819,40 +819,7 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <2>;
-				max_lane_speed = <15000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
+
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-camera-e3331-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -210,42 +210,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				* Set this to the highest pix_clk_hz out of all available modes.
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <3>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <800000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-e3333-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2015-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -63,42 +63,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				* Set this to the highest pix_clk_hz out of all available modes.
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <12>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <160000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-imx185-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2016-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2016-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -402,40 +402,6 @@
 		__overlay__ {
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-imx274-dual.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -712,41 +712,7 @@
 		__overlay__ {
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <8>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <750000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
+
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
 				* The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-camera-imx390-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2016-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2016-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -159,7 +159,7 @@
 								* Sensor embedded metadata height in units of rows.
 								* If sensor does not support embedded metadata value should be 0.
 								*/
-								mode0 {/*mode IMX390_MODE_1936X1096_CROP_30FPS*/
+								mode0 {/*mode IMX390_WDR_MODE_1936X1216_CROP_30FPS*/
 									mclk_khz = "24000";
 									num_lanes = "4";
 									tegra_sinterface = "serial_a";
@@ -171,26 +171,26 @@
 									mode_type = "bayer_wdr_pwl";
 									pixel_phase = "rggb";
 									active_w = "1936";
-									active_h = "1096";
+									active_h = "1216";
 									readout_orientation = "0";
-									line_length = "4400";
+									line_length = "3300"; /* HMAX */
 									inherent_gain = "1";
 									mclk_multiplier = "14.58";
-									pix_clk_hz = "148500000";
+									pix_clk_hz = "83250000"; /* 249.75Mbps/Lane * 4Lane / 12bit = 83.25[MPixel] */
 									serdes_pix_clk_hz = "500000000";
 									gain_factor = "10";
-									min_gain_val = "84"; /* dB */
-									max_gain_val = "240"; /* dB */
-									step_gain_val = "1"; /* 0.1 */
-									default_gain = "84";
+									min_gain_val = "1";
+									max_gain_val = "420";
+									step_gain_val = "3";
+									default_gain = "1";
 									framerate_factor = "1000000";
 									min_framerate = "30000000";
 									max_framerate = "30000000";
 									step_framerate = "1";
 									default_framerate = "30000000";
 									exposure_factor = "1000000";
-									min_exp_time = "2000"; /*us, 2 lines*/
-									max_exp_time = "33000";
+									min_exp_time = "134"; /* (ERRWID_BACK/2) + 2 = 5[line] */
+									max_exp_time = "33227"; /* MODE_VMAX - 1 - (ERRWID_BACK/2) = 1250 - 1 - (6/2) = 1246[line] */
 									step_exp_time = "1";
 									default_exp_time = "11000";/* us */
 									embedded_metadata_height = "0";
@@ -198,26 +198,26 @@
 									max_hdr_ratio = "64.0";
 									num_control_point = "9";
 									control_point_x_0 = "0";
+									control_point_x_1 = "469";
+									control_point_x_2 = "1582";
+									control_point_x_3 = "4592";
+									control_point_x_4 = "13446";
+									control_point_x_5 = "39550";
+									control_point_x_6 = "117664";
+									control_point_x_7 = "352265";
+									control_point_x_8 = "1048575";
 									control_point_y_0 = "0";
-									control_point_x_1="479";
-									control_point_y_1="479";
-									control_point_x_2="1438";
-									control_point_y_2="837";
-									control_point_x_3="4315";
-									control_point_y_3="1238";
-									control_point_x_4="12945";
-									control_point_y_4="1688";
-									control_point_x_5="38836";
-									control_point_y_5="2191";
-									control_point_x_6="116508";
-									control_point_y_6="2755";
-									control_point_x_7="349525";
-									control_point_y_7="3387";
-									control_point_x_8="1048575";
-									control_point_y_8="4095";
+									control_point_y_1 = "469";
+									control_point_y_2 = "840";
+									control_point_y_3 = "1270";
+									control_point_y_4 = "1736";
+									control_point_y_5 = "2238";
+									control_point_y_6 = "2792";
+									control_point_y_7 = "3411";
+									control_point_y_8 = "4095";
 								};
 
-								mode1 {/*mode IMX390_MODE_1936X1096_CROP_30FPS*/
+								mode1 {/*mode IMX390_SDR_MODE_1936X1216_CROP_30FPS*/
 									mclk_khz = "24000";
 									num_lanes = "4";
 									tegra_sinterface = "serial_a";
@@ -231,18 +231,18 @@
 									pixel_phase = "rggb";
 
 									active_w = "1936";
-									active_h = "1096";
+									active_h = "1216";
 									readout_orientation = "0";
-									line_length = "2200";
+									line_length = "3300"; /* HMAX */
 									inherent_gain = "1";
-									pix_clk_hz = "74250000";
+									pix_clk_hz = "83250000"; /* 249.75Mbps/Lane * 4Lane / 12bit = 83.25[MPixel] */
 									serdes_pix_clk_hz = "200000000";
 
 									gain_factor = "10";
-									min_gain_val = "0"; /* dB */
-									max_gain_val = "300"; /* dB */
-									step_gain_val = "3"; /* 0.3 */
-									default_gain = "0";
+									min_gain_val = "1";
+									max_gain_val = "420";
+									step_gain_val = "3";
+									default_gain = "1";
 									min_hdr_ratio = "1";
 									max_hdr_ratio = "1";
 									framerate_factor = "1000000";
@@ -251,10 +251,10 @@
 									step_framerate = "1";
 									default_framerate = "30000000";
 									exposure_factor = "1000000";
-									min_exp_time = "59"; /*us, 2 lines*/
-									max_exp_time = "33333";
+									min_exp_time = "134"; /* (ERRWID_BACK/2) + 2 = 5[line] */
+									max_exp_time = "33227"; /* MODE_VMAX - 1 - (ERRWID_BACK/2) = 1250 - 1 - (6/2) = 1246[line] */
 									step_exp_time = "1";
-									default_exp_time = "33333";/* us */
+									default_exp_time = "11000";/* us */
 									embedded_metadata_height = "0";
 								};
 
@@ -278,40 +278,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-p3762-a00.dtsi

@@ -1113,6 +1113,8 @@
 									};
 								};
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								compatible = "nvidia,ar0234_hawk_owl";
 								reg = <0x34>;
@@ -1249,6 +1251,8 @@
 									};
 								};
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								compatible = "nvidia,ar0234_hawk_owl";
 								reg = <0x36>;
@@ -1391,40 +1395,7 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				 * Physical settings to calculate max ISO BW
-				 *
-				 * num_csi_lanes = <>;
-				 * Total number of CSI lanes when all cameras are active
-				 *
-				 * max_lane_speed = <>;
-				 * Max lane speed in Kbit/s
-				 *
-				 * min_bits_per_pixel = <>;
-				 * Min bits per pixel
-				 *
-				 * vi_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the VI ISO case
-				 *
-				 * vi_bw_margin_pct = <>;
-				 * Vi bandwidth margin in percentage
-				 *
-				 * max_pixel_rate = <>;
-				 * Max pixel rate in Kpixel/s for the ISP ISO case
-				 *
-				 * isp_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the ISP ISO case
-				 *
-				 * isp_bw_margin_pct = <>;
-				 * Isp bandwidth margin in percentage
-				 */
-				num_csi_lanes = <12>;
-				max_lane_speed = <15000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
+
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD
@@ -1533,7 +1504,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_e@34";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@2/ar0234_e@34";
 							status = "okay";
 						};
 					};
@@ -1544,7 +1515,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_f@35";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@2/ar0234_f@35";
 							status = "okay";
 						};
 					};
@@ -1555,7 +1526,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_g@36";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@3/ar0234_g@36";
 							status = "okay";
 						};
 					};
@@ -1566,7 +1537,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_h@37";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@3/ar0234_h@37";
 							status = "okay";
 						};
 					};

overlay/tegra234-camera-p3783-a00.dtsi

@@ -24,89 +24,89 @@
 						reg = <0>;
 						status = "okay";
 						ar0234_vi_in0: endpoint {
-						       vc-id = <0>;
-						       port-index = <0>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out0>;
+							vc-id = <0>;
+							port-index = <0>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out0>;
 							status = "okay";
-					       };
+						};
 					};
 					port@1 {
 						reg = <1>;
 						status = "okay";
 						ar0234_vi_in1: endpoint {
-						       vc-id = <1>;
-						       port-index = <0>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out1>;
+							vc-id = <1>;
+							port-index = <0>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out1>;
 							status = "okay";
-	       					};
+						};
 					};
 					port@2 {
 						reg = <2>;
 						status = "okay";
 						ar0234_vi_in2: endpoint {
-						       vc-id = <0>;
-						       port-index = <1>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out2>;
+							vc-id = <0>;
+							port-index = <1>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out2>;
 							status = "okay";
-					       };
+						};
 					};
 					port@3 {
 						reg = <3>;
 						status = "okay";
 						ar0234_vi_in3: endpoint {
-						       vc-id = <1>;
-						       port-index = <1>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out3>;
+							vc-id = <1>;
+							port-index = <1>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out3>;
 							status = "okay";
-					       };
+						};
 					};
 					port@4 {
 						reg = <4>;
 						status = "okay";
 						ar0234_vi_in4: endpoint {
-						       vc-id = <0>;
-						       port-index = <2>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out4>;
+							vc-id = <0>;
+							port-index = <2>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out4>;
 							status = "okay";
-					       };
+						};
 					};
 					port@5 {
 						reg = <5>;
 						status = "okay";
 						ar0234_vi_in5: endpoint {
-						       vc-id = <1>;
-						       port-index = <2>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out5>;
+							vc-id = <1>;
+							port-index = <2>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out5>;
 							status = "okay";
-					       };
+						};
 					};
 					port@6 {
 						reg = <6>;
 						status = "okay";
 						ar0234_vi_in6: endpoint {
-						       vc-id = <0>;
-						       port-index = <3>;
-						       bus-width = <2>;
-						       remote-endpoint = <&ar0234_csi_out6>;
+							vc-id = <0>;
+							port-index = <3>;
+							bus-width = <2>;
+							remote-endpoint = <&ar0234_csi_out6>;
 							status = "okay";
-	       					};
+						};
 					};
 					port@7 {
 						reg = <7>;
 						status = "okay";
 						ar0234_vi_in7: endpoint {
-							vc-id = <1>;
+						vc-id = <1>;
 							port-index = <3>;
 							bus-width = <2>;
 							remote-endpoint = <&ar0234_csi_out7>;
 							status = "okay";
-	       					};
+						};
 					};
 					port@8 {
 						reg = <8>;
@@ -180,9 +180,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out0: endpoint@1 {
-										 remote-endpoint = <&ar0234_vi_in0>;
+										remote-endpoint = <&ar0234_vi_in0>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -206,9 +206,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out1: endpoint@3 {
-										 remote-endpoint = <&ar0234_vi_in1>;
+										remote-endpoint = <&ar0234_vi_in1>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -232,9 +232,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out2: endpoint@5 {
-										 remote-endpoint = <&ar0234_vi_in2>;
+										remote-endpoint = <&ar0234_vi_in2>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -258,9 +258,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out3: endpoint@7 {
-										 remote-endpoint = <&ar0234_vi_in3>;
+										remote-endpoint = <&ar0234_vi_in3>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -284,9 +284,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out4: endpoint@9 {
-										 remote-endpoint = <&ar0234_vi_in4>;
+										remote-endpoint = <&ar0234_vi_in4>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -310,9 +310,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out5: endpoint@11 {
-										 remote-endpoint = <&ar0234_vi_in5>;
+										remote-endpoint = <&ar0234_vi_in5>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -336,9 +336,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out6: endpoint@13 {
-									 	remote-endpoint = <&ar0234_vi_in6>;
+										remote-endpoint = <&ar0234_vi_in6>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -362,9 +362,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out7: endpoint@15 {
-										 remote-endpoint = <&ar0234_vi_in7>;
+										remote-endpoint = <&ar0234_vi_in7>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -388,9 +388,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out8: endpoint@17 {
-										 remote-endpoint = <&ar0234_vi_in8>;
+										remote-endpoint = <&ar0234_vi_in8>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -414,9 +414,9 @@
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out9: endpoint@19 {
-										 remote-endpoint = <&ar0234_vi_in9>;
+										remote-endpoint = <&ar0234_vi_in9>;
 										status = "okay";
-									 };
+									};
 								};
 							};
 						};
@@ -430,19 +430,19 @@
 									reg = <0>;
 									status = "okay";
 									ar0234_csi_in10: endpoint@20 {
-										 port-index = <4>;
-										 bus-width = <2>;
-										 remote-endpoint = <&ar0234_ar0234_out10>;
+										port-index = <4>;
+										bus-width = <2>;
+										remote-endpoint = <&ar0234_ar0234_out10>;
 										status = "okay";
-									 };
+									};
 								};
 								port@1 {
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out10: endpoint@21 {
-										  remote-endpoint = <&ar0234_vi_in10>;
+										remote-endpoint = <&ar0234_vi_in10>;
 										status = "okay";
-									  };
+									};
 								};
 							};
 						};
@@ -456,19 +456,19 @@
 									reg = <0>;
 									status = "okay";
 									ar0234_csi_in11: endpoint@22 {
-										 port-index = <4>;
-										 bus-width = <2>;
-										 remote-endpoint = <&ar0234_ar0234_out11>;
+										port-index = <4>;
+										bus-width = <2>;
+										remote-endpoint = <&ar0234_ar0234_out11>;
 										status = "okay";
-									 };
+									};
 								};
 								port@1 {
 									reg = <1>;
 									status = "okay";
 									ar0234_csi_out11: endpoint@23 {
-										  remote-endpoint = <&ar0234_vi_in11>;
+										remote-endpoint = <&ar0234_vi_in11>;
 										status = "okay";
-									  };
+									};
 								};
 							};
 						};
@@ -535,10 +535,10 @@
 							port@0 {
 								reg = <0>;
 								ar0234_ar0234_out8: endpoint {
-									    vc-id = <0>;
-									    port-index = <4>;
-									    bus-width = <2>;
-									    remote-endpoint = <&ar0234_csi_in8>;
+									vc-id = <0>;
+									port-index = <4>;
+									bus-width = <2>;
+									remote-endpoint = <&ar0234_csi_in8>;
 								};
 							};
 						};
@@ -603,10 +603,10 @@
 							port@0 {
 								reg = <0>;
 								ar0234_ar0234_out9: endpoint {
-									    vc-id = <1>;
-									    port-index = <4>;
-									    bus-width = <2>;
-									    remote-endpoint = <&ar0234_csi_in9>;
+									vc-id = <1>;
+									port-index = <4>;
+									bus-width = <2>;
+									remote-endpoint = <&ar0234_csi_in9>;
 								};
 							};
 						};
@@ -671,10 +671,10 @@
 							port@0 {
 								reg = <0>;
 								ar0234_ar0234_out10: endpoint {
-									    vc-id = <2>;
-									    port-index = <4>;
-									    bus-width = <2>;
-									    remote-endpoint = <&ar0234_csi_in10>;
+									vc-id = <2>;
+									port-index = <4>;
+									bus-width = <2>;
+									remote-endpoint = <&ar0234_csi_in10>;
 								};
 							};
 						};
@@ -739,10 +739,10 @@
 							port@0 {
 								reg = <0>;
 								ar0234_ar0234_out11: endpoint {
-									    vc-id = <3>;
-									    port-index = <4>;
-									    bus-width = <2>;
-									    remote-endpoint = <&ar0234_csi_in11>;
+									vc-id = <3>;
+									port-index = <4>;
+									bus-width = <2>;
+									remote-endpoint = <&ar0234_csi_in11>;
 								};
 							};
 						};
@@ -899,10 +899,10 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out0: endpoint {
-											    vc-id = <0>;
-											    port-index = <0>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in0>;
+											vc-id = <0>;
+											port-index = <0>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in0>;
 										};
 									};
 								};
@@ -967,10 +967,10 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out1: endpoint {
-											    vc-id = <1>;
-											    port-index = <0>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in1>;
+											vc-id = <1>;
+											port-index = <0>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in1>;
 										};
 									};
 								};
@@ -1037,10 +1037,10 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out2: endpoint {
-											    vc-id = <0>;
-											    port-index = <1>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in2>;
+											vc-id = <0>;
+											port-index = <1>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in2>;
 										};
 									};
 								};
@@ -1105,14 +1105,16 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out3: endpoint {
-											    vc-id = <1>;
-											    port-index = <1>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in3>;
+											vc-id = <1>;
+											port-index = <1>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in3>;
 										};
 									};
 								};
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								compatible = "nvidia,ar0234_hawk_owl";
 								reg = <0x34>;
@@ -1173,10 +1175,10 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out4: endpoint {
-											    vc-id = <0>;
-											    port-index = <2>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in4>;
+											vc-id = <0>;
+											port-index = <2>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in4>;
 										};
 									};
 								};
@@ -1241,14 +1243,16 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out5: endpoint {
-											    vc-id = <1>;
-											    port-index = <2>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in5>;
+											vc-id = <1>;
+											port-index = <2>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in5>;
 										};
 									};
 								};
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								compatible = "nvidia,ar0234_hawk_owl";
 								reg = <0x36>;
@@ -1309,10 +1313,10 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out6: endpoint {
-											    vc-id = <0>;
-											    port-index = <3>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in6>;
+											vc-id = <0>;
+											port-index = <3>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in6>;
 										};
 									};
 								};
@@ -1377,10 +1381,10 @@
 									port@0 {
 										reg = <0>;
 										ar0234_ar0234_out7: endpoint {
-											    vc-id = <1>;
-											    port-index = <3>;
-											    bus-width = <2>;
-											    remote-endpoint = <&ar0234_csi_in7>;
+											vc-id = <1>;
+											port-index = <3>;
+											bus-width = <2>;
+											remote-endpoint = <&ar0234_csi_in7>;
 										};
 									};
 								};
@@ -1391,40 +1395,7 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				 * Physical settings to calculate max ISO BW
-				 *
-				 * num_csi_lanes = <>;
-				 * Total number of CSI lanes when all cameras are active
-				 *
-				 * max_lane_speed = <>;
-				 * Max lane speed in Kbit/s
-				 *
-				 * min_bits_per_pixel = <>;
-				 * Min bits per pixel
-				 *
-				 * vi_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the VI ISO case
-				 *
-				 * vi_bw_margin_pct = <>;
-				 * Vi bandwidth margin in percentage
-				 *
-				 * max_pixel_rate = <>;
-				 * Max pixel rate in Kpixel/s for the ISP ISO case
-				 *
-				 * isp_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the ISP ISO case
-				 *
-				 * isp_bw_margin_pct = <>;
-				 * Isp bandwidth margin in percentage
-				 */
-				num_csi_lanes = <12>;
-				max_lane_speed = <15000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
+
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD
@@ -1442,6 +1413,7 @@
 						drivernode0 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_sensor";
+							/* Declare the device-tree hierarchy to driver instance */
 							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/ar0234_i@30";
 							status = "okay";
 						};
@@ -1454,6 +1426,7 @@
 						drivernode0 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_sensor";
+							/* Declare the device-tree hierarchy to driver instance */
 							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/ar0234_j@32";
 							status = "okay";
 						};
@@ -1531,7 +1504,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_e@34";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@2/ar0234_e@34";
 							status = "okay";
 						};
 					};
@@ -1542,7 +1515,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_f@35";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@2/ar0234_f@35";
 							status = "okay";
 						};
 					};
@@ -1553,7 +1526,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_g@36";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@3/ar0234_g@36";
 							status = "okay";
 						};
 					};
@@ -1564,7 +1537,7 @@
 						status = "okay";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@1/ar0234_h@37";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@31e0000/virtual_i2c_mux@50/i2c@3/ar0234_h@37";
 							status = "okay";
 						};
 					};

overlay/tegra234-camera-rbpcv2-imx219.dtsi

@@ -684,41 +684,7 @@
 
 			tcp: tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <240000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
+
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3737-0000+p3701-0000-hdr40.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 /*
  * Device-tree overlay for tegra234-p3737-0000-p3701-0000 40-pin
  * Expansion Header.
@@ -30,9 +30,15 @@
 				};
 				hdr40-pin8 {
 					nvidia,pins = "uart1_tx_pr2";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 				};
 				hdr40-pin10 {
 					nvidia,pins = "uart1_rx_pr3";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin11 {
 					nvidia,pins = "uart1_rts_pr4";
@@ -145,10 +151,16 @@
 				hdr40-pin3 {
 					nvidia,pins = "gen8_i2c_scl_pdd1";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin5 {
 					nvidia,pins = "gen8_i2c_sda_pdd2";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin16a {
 					nvidia,pins = "can1_en_pbb1";
@@ -166,9 +178,15 @@
 				};
 				hdr40-pin27 {
 					nvidia,pins = "gen2_i2c_sda_pdd0";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin28 {
 					nvidia,pins = "gen2_i2c_scl_pcc7";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin29 {
 					nvidia,pins = "can0_din_paa1";

overlay/tegra234-p3737-camera-dual-imx274-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 /*
  * Jetson Device-tree overlay for Camera Dual-IMX274 on t23x platforms
  *
@@ -316,15 +316,6 @@
 			ids = "LPRD-dual-imx274-002";
 			sw-modules = "kernel";
 		};
-		__overlay__ {
-			num_csi_lanes = <8>;
-			max_lane_speed = <1500000>;
-			min_bits_per_pixel = <10>;
-			vi_peak_byte_per_pixel = <2>;
-			vi_bw_margin_pct = <25>;
-			isp_peak_byte_per_pixel = <5>;
-			isp_bw_margin_pct = <25>;
-		};
 	};
 	/* pca9646 i2c mux */
 	fragment@27 {

overlay/tegra234-p3737-camera-e3331-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 
 /dts-v1/;
 /plugin/;
@@ -41,14 +41,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				num_csi_lanes = <3>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <800000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				modules {
 					status = "okay";

overlay/tegra234-p3737-camera-eCAM130A-overlay.dts

@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
+/* SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
 
 /dts-v1/;
 /plugin/;
@@ -1194,11 +1194,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				num_csi_lanes = <12>;
-				max_lane_speed = <2500000>;
-				min_bits_per_pixel = <16>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <67>;
 
 				modules {
 					cam_module0: module0 {

overlay/tegra234-p3737-camera-imx185-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 /*
  * Jetson Device-tree overlay for Camera IMX185 on t23x platforms
  *
@@ -178,15 +178,6 @@
 			ids = "LPRD-002001", "LPRD-002", "LPRD-001";
 			sw-modules = "kernel";
 		};
-		__overlay__ {
-			num_csi_lanes = <4>;
-			max_lane_speed = <1500000>;
-			min_bits_per_pixel = <10>;
-			vi_peak_byte_per_pixel = <2>;
-			vi_bw_margin_pct = <25>;
-			isp_peak_byte_per_pixel = <5>;
-			isp_bw_margin_pct = <25>;
-		};
 	};
 	/* pca9646 i2c mux */
 	fragment@30 {

overlay/tegra234-p3737-camera-p3762-a00-1Hawk-overlay.dts

@@ -154,12 +154,16 @@
 							ar0234_d@33 {
 								status = "disabled";
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								status = "disabled";
 							};
 							ar0234_f@35 {
 								status = "disabled";
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								status = "disabled";
 							};

overlay/tegra234-p3737-camera-p3762-a00-2Hawk-overlay.dts

@@ -154,12 +154,16 @@
 							ar0234_d@33 {
 								status = "okay";
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								status = "disabled";
 							};
 							ar0234_f@35 {
 								status = "disabled";
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								status = "disabled";
 							};

overlay/tegra234-p3737-camera-p3762-a00-3Hawk-3Owl-overlay.dts

@@ -155,12 +155,16 @@
 							ar0234_d@33 {
 								status = "okay";
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								status = "okay";
 							};
 							ar0234_f@35 {
 								status = "okay";
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								status = "disabled";
 							};

overlay/tegra234-p3737-camera-p3762-a00-4Hawk-overlay.dts

@@ -154,12 +154,16 @@
 							ar0234_d@33 {
 								status = "okay";
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								status = "okay";
 							};
 							ar0234_f@35 {
 								status = "okay";
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								status = "okay";
 							};

overlay/tegra234-p3737-camera-p3762-a00-4Owl-overlay.dts

@@ -155,12 +155,16 @@
 							ar0234_d@33 {
 								status = "disabled";
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								status = "disabled";
 							};
 							ar0234_f@35 {
 								status = "disabled";
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								status = "disabled";
 							};

overlay/tegra234-p3737-camera-p3762-a00-overlay.dts

@@ -68,12 +68,16 @@
 							ar0234_d@33 {
 								status = "okay";
 							};
+						};
+						i2c@2 {
 							ar0234_e@34 {
 								status = "okay";
 							};
 							ar0234_f@35 {
 								status = "okay";
 							};
+						};
+						i2c@3 {
 							ar0234_g@36 {
 								status = "okay";
 							};

overlay/tegra234-p3737-camera-p3762-a00.dtsi

@@ -215,6 +215,12 @@
 								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
 								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
 							};
+						};
+						i2c@2 {
+							reg = <2>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
 							ar0234_e@34 {
 								status = "disabled";
 								def-addr = <0x10>;
@@ -247,6 +253,12 @@
 								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
 								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
 							};
+						};
+						i2c@3 {
+							reg = <3>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
 							ar0234_g@36 {
 								status = "disabled";
 								def-addr = <0x10>;

overlay/tegra234-p3740-camera-p3783-a00-overlay.dts

@@ -221,6 +221,12 @@
 								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
 								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
 							};
+						};
+						i2c@2 {
+							reg = <2>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
 							ar0234_e@34 {
 								status = "okay";
 								def-addr = <0x10>;
@@ -253,6 +259,12 @@
 								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
 								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
 							};
+						};
+						i2c@3 {
+							reg = <3>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
 							ar0234_g@36 {
 								status = "okay";
 								def-addr = <0x10>;

overlay/tegra234-p3767-0000+p3768-0000-csi.dts

@@ -11,7 +11,7 @@
 #include <dt-bindings/tegra234-p3767-0000-common.h>
 
 / {
-	overlay-name = "Jetson 24pin CSI Connector";
+	overlay-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 
 	p3767-0000_p3768-0000-csi@0 {

overlay/tegra234-p3767-0000-common-hdr40.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 /*
  * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
  *
@@ -36,9 +36,15 @@
 				};
 				hdr40-pin8 {
 					nvidia,pins = "uart1_tx_pr2";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 				};
 				hdr40-pin10 {
 					nvidia,pins = "uart1_rx_pr3";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin11 {
 					nvidia,pins = "uart1_rts_pr4";
@@ -206,16 +212,28 @@
 				hdr40-pin3 {
 					nvidia,pins = "gen8_i2c_sda_pdd2";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin5 {
 					nvidia,pins = "gen8_i2c_scl_pdd1";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin27 {
 					nvidia,pins = "gen2_i2c_sda_pdd0";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin28 {
 					nvidia,pins = "gen2_i2c_scl_pcc7";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 			};
 		};

overlay/tegra234-p3767-camera-p3768-imx219-A.dts

@@ -13,7 +13,7 @@
 
 / {
 	overlay-name = "Camera IMX219-A";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 
 	/* IMX219 sensor module on CSI PORT A / cam1 */
@@ -37,41 +37,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx219-C.dts

@@ -13,7 +13,7 @@
 
 / {
 	overlay-name = "Camera IMX219-C";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 
 	/* IMX219 sensor module on CSI PORT B / cam0 */
@@ -37,41 +37,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx219-dual.dts

@@ -14,7 +14,7 @@
 
 / {
 	overlay-name = "Camera IMX219 Dual";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 
 	fragment-camera-imx219@0 {

overlay/tegra234-p3767-camera-p3768-imx219-imx477.dts

@@ -13,7 +13,7 @@
 
 / {
 	overlay-name = "Camera IMX219-A and IMX477-C";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 	/* IMX477 connected on cam0 and IMX219 connected on cam1 port */
 
@@ -46,41 +46,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-A.dts

@@ -12,7 +12,7 @@
 
 / {
 	overlay-name = "Camera IMX477-A";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 	/* IMX477 connected to cam1 port */
 
@@ -36,41 +36,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-C.dts

@@ -12,7 +12,7 @@
 
 / {
 	overlay-name = "Camera IMX477-C";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 	/*IMX477 connected on cam0 port */
 
@@ -36,41 +36,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-dual-4lane.dts

@@ -1,491 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
-
-/dts-v1/;
-/plugin/;
-
-#define CAM0_PWDN	TEGRA234_MAIN_GPIO(H, 6)
-#define CAM1_PWDN	TEGRA234_MAIN_GPIO(AC, 0)
-#define CAM_I2C_MUX 	TEGRA234_AON_GPIO(CC, 3)
-
-#include <dt-bindings/tegra234-p3767-0000-common.h>
-
-/ {
-	overlay-name = "Camera IMX477 Dual 4 lane";
-	jetson-header-name = "Jetson 24pin CSI Connector";
-	compatible = JETSON_COMPATIBLE_P3768;
-
-	fragment@0 {
-		target-path = "/";
-		__overlay__ {
-			tegra-capture-vi  {
-				num-channels = <2>;
-				ports {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					port@0 {
-						reg = <0>;
-						rbpcv3_imx477_vi_in0: endpoint {
-							port-index = <1>;
-							bus-width = <4>;
-							remote-endpoint = <&rbpcv3_imx477_csi_out0>;
-						};
-					};
-					port@1 {
-						reg = <1>;
-						rbpcv3_imx477_vi_in1: endpoint {
-							port-index = <2>;
-							bus-width = <2>;
-							remote-endpoint = <&rbpcv3_imx477_csi_out1>;
-						};
-					};
-				};
-			};
-			tegra-camera-platform {
-				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
-				/**
-				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
-				 * The first part is the camera_board_id for the module; if the module is in a FFD
-				 * platform, then use the platform name for this part.
-				 * The second part contains the position of the module, ex. "rear" or "front".
-				 * The third part contains the last 6 characters of a part number which is found
-				 * in the module's specsheet from the vendor.
-				 */
-				modules {
-					module0 {
-						badge = "jakku_front_RBPCV3";
-						position = "front";
-						orientation = "1";
-						drivernode0 {
-							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@0/rbpcv3_imx477_a@1a";
-						};
-					};
-					module1 {
-						badge = "jakku_rear_RBPCV3";
-						position = "rear";
-						orientation = "1";
-						drivernode0 {
-							pcl_id = "v4l2_sensor";
-							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@1/rbpcv3_imx477_c@1a";
-						};
-					};
-				};
-			};
-			bus@0 {
-				host1x@13e00000 {
-					nvcsi@15a00000 {
-						num-channels = <2>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						channel@0 {
-							reg = <0>;
-							ports {
-								#address-cells = <1>;
-								#size-cells = <0>;
-								port@0 {
-									reg = <0>;
-									rbpcv3_imx477_csi_in0: endpoint@0 {
-										port-index = <1>;
-										bus-width = <4>;
-										remote-endpoint = <&rbpcv3_imx477_out0>;
-									};
-								};
-								port@1 {
-									reg = <1>;
-									rbpcv3_imx477_csi_out0: endpoint@1 {
-										remote-endpoint = <&rbpcv3_imx477_vi_in0>;
-									};
-								};
-							};
-						};
-						channel@1 {
-							reg = <1>;
-							ports {
-								#address-cells = <1>;
-								#size-cells = <0>;
-								port@0 {
-									reg = <0>;
-									rbpcv3_imx477_csi_in1: endpoint@2 {
-										port-index = <2>;
-										bus-width = <2>;
-										remote-endpoint = <&rbpcv3_imx477_out1>;
-									};
-								};
-								port@1 {
-									reg = <1>;
-									rbpcv3_imx477_csi_out1: endpoint@3 {
-										remote-endpoint = <&rbpcv3_imx477_vi_in1>;
-									};
-								};
-							};
-						};
-					};
-				};
-				cam_i2cmux {
-					status = "okay";
-					compatible = "i2c-mux-gpio";
-					#address-cells = <1>;
-					#size-cells = <0>;
-					mux-gpios = <&gpio_aon CAM_I2C_MUX GPIO_ACTIVE_HIGH>;
-					i2c-parent = <&cam_i2c>;
-					i2c@0 {
-						status = "okay";
-						reg = <0>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						rbpcv2_imx219_a@10 {
-							status = "disabled";
-						};
-						rbpcv3_imx477_a@1a {
-							reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
-							compatible = "ridgerun,imx477";
-							/* I2C device address */
-							reg = <0x1a>;
-							/* V4L2 device node location */
-							devnode = "video0";
-							/* Physical dimensions of sensor */
-							physical_w = "3.680";
-							physical_h = "2.760";
-							sensor_model = "imx477";
-							use_sensor_mode_id = "true";
-							/**
-							* ==== Modes ====
-							* A modeX node is required to support v4l2 driver
-							* implementation with NVIDIA camera software stack
-							*
-							* == Signal properties ==
-							*
-							* phy_mode = "";
-							* PHY mode used by the MIPI lanes for this device
-							*
-							* tegra_sinterface = "";
-							* CSI Serial interface connected to tegra
-							* Incase of virtual HW devices, use virtual
-							* For SW emulated devices, use host
-							*
-							* pix_clk_hz = "";
-							* Sensor pixel clock used for calculations like exposure and framerate
-							*
-							* readout_orientation = "0";
-							* Based on camera module orientation.
-							* Only change readout_orientation if you specifically
-							* Program a different readout order for this mode
-							*
-							* lane_polarity
-							* Based on the camera connector pin.
-							* CSIx_D0 | CSIx_D1 | CSI(X+1)_D0 | CSI(X+1)CSIx_D1
-							*    LSB  |   BIT1  |     BIT2    |      MSB
-							* if there is a polarity swap on any lane, the bit corrsponding
-							* to the lane should be set
-							* e.g. polarity swap on CSIx_D0 only -> lane_polarity = "1"; 0001
-							* e.g. polarity swap on CSIx_D1 and CSI(X+1)_D0 -> lane_polarity = "6"; 0110
-							*
-							* == Image format Properties ==
-							*
-							* active_w = "";
-							* Pixel active region width
-							*
-							* active_h = "";
-							* Pixel active region height
-							*
-							* pixel_t = "";
-							* The sensor readout pixel pattern
-							*
-							* line_length = "";
-							* Pixel line length (width) for sensor mode.
-							*
-							* == Source Control Settings ==
-							*
-							* Gain factor used to convert fixed point integer to float
-							* Gain range [min_gain/gain_factor, max_gain/gain_factor]
-							* Gain step [step_gain/gain_factor is the smallest step that can be configured]
-							* Default gain [Default gain to be initialized for the control.
-							*     use min_gain_val as default for optimal results]
-							* Framerate factor used to convert fixed point integer to float
-							* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
-							* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
-							* Default Framerate [Default framerate to be initialized for the control.
-							*     use max_framerate to get required performance]
-							* Exposure factor used to convert fixed point integer to float
-							* For convenience use 1 sec = 1000000us as conversion factor
-							* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
-							* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
-							* Default Exposure Time [Default exposure to be initialized for the control.
-							*     Set default exposure based on the default_framerate for optimal exposure settings]
-							*
-							* gain_factor = ""; (integer factor used for floating to fixed point conversion)
-							* min_gain_val = ""; (ceil to integer)
-							* max_gain_val = ""; (ceil to integer)
-							* step_gain_val = ""; (ceil to integer)
-							* default_gain = ""; (ceil to integer)
-							* Gain limits for mode
-							*
-							* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
-							* min_exp_time = ""; (ceil to integer)
-							* max_exp_time = ""; (ceil to integer)
-							* step_exp_time = ""; (ceil to integer)
-							* default_exp_time = ""; (ceil to integer)
-							* Exposure Time limits for mode (sec)
-							*
-							* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
-							* min_framerate = ""; (ceil to integer)
-							* max_framerate = ""; (ceil to integer)
-							* step_framerate = ""; (ceil to integer)
-							* default_framerate = ""; (ceil to integer)
-							* Framerate limits for mode (fps)
-							*
-							* embedded_metadata_height = "";
-							* Sensor embedded metadata height in units of rows.
-							* If sensor does not support embedded metadata value should be 0.
-							*/
-							mode0 { /* IMX477_MODE_3840x2160 */
-								mclk_khz = "24000";
-								num_lanes = "4";
-								tegra_sinterface = "serial_b";
-								phy_mode = "DPHY";
-								discontinuous_clk = "no";
-								dpcm_enable = "false";
-								cil_settletime = "0";
-								lane_polarity = "6";
-								active_w = "3840";
-								active_h = "2160";
-								mode_type = "bayer";
-								pixel_phase = "rggb";
-								csi_pixel_bit_depth = "10";
-								readout_orientation = "90";
-								line_length = "5832";
-								inherent_gain = "1";
-								mclk_multiplier = "80";
-								pix_clk_hz = "600000000";
-								gain_factor = "16";
-								framerate_factor = "1000000";
-								exposure_factor = "1000000";
-								min_gain_val = "16"; /* 1.00x */
-								max_gain_val = "356"; /* 22x */
-								step_gain_val = "1";
-								default_gain = "16"; /* 1.00x */
-								min_hdr_ratio = "1";
-								max_hdr_ratio = "1";
-								min_framerate = "2000000"; /* 2.0 fps */
-								max_framerate = "30000000"; /* 30.0 fps */
-								step_framerate = "1";
-								default_framerate = "30000000"; /* 30.0 fps */
-								min_exp_time = "13"; /* us */
-								max_exp_time = "683709"; /* us */
-								step_exp_time = "1";
-								default_exp_time = "2495"; /* us */
-								embedded_metadata_height = "2";
-							};
-							mode1 { /* IMX477_MODE_1920X1080 */
-								mclk_khz = "24000";
-								num_lanes = "4";
-								tegra_sinterface = "serial_b";
-								phy_mode = "DPHY";
-								discontinuous_clk = "no";
-								dpcm_enable = "false";
-								cil_settletime = "0";
-								lane_polarity = "6";
-								active_w = "1920";
-								active_h = "1080";
-								mode_type = "bayer";
-								pixel_phase = "rggb";
-								csi_pixel_bit_depth = "10";
-								readout_orientation = "90";
-								line_length = "3076";
-								inherent_gain = "1";
-								mclk_multiplier = "80";
-								pix_clk_hz = "600000000";
-								gain_factor = "16";
-								framerate_factor = "1000000";
-								exposure_factor = "1000000";
-								min_gain_val = "16"; /* 1.00x */
-								max_gain_val = "356"; /* 22x */
-								step_gain_val = "1";
-								default_gain = "16"; /* 1.00x */
-								min_hdr_ratio = "1";
-								max_hdr_ratio = "1";
-								min_framerate = "2000000"; /* 2.0 fps */
-								max_framerate = "60000000"; /* 60.0 fps */
-								step_framerate = "1";
-								default_framerate = "60000000"; /* 60.0 fps */
-								min_exp_time = "13"; /* us */
-								max_exp_time = "683709"; /* us */
-								step_exp_time = "1";
-								default_exp_time = "2495"; /* us */
-								embedded_metadata_height = "2";
-							};
-							ports {
-								#address-cells = <1>;
-								#size-cells = <0>;
-								port@0 {
-									reg = <0>;
-									rbpcv3_imx477_out0: endpoint {
-										port-index = <1>;
-										bus-width = <4>;
-										remote-endpoint = <&rbpcv3_imx477_csi_in0>;
-									};
-								};
-							};
-						};
-					};
-					i2c@1 {
-						status = "okay";
-						reg = <1>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						rbpcv2_imx219_c@10 {
-							status = "disabled";
-						};
-						rbpcv3_imx477_c@1a {
-							reset-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
-							compatible = "ridgerun,imx477";
-							/* I2C device address */
-							reg = <0x1a>;
-							/* V4L2 device node location */
-							devnode = "video1";
-							/* Physical dimensions of sensor */
-							physical_w = "3.680";
-							physical_h = "2.760";
-							sensor_model = "imx477";
-							use_sensor_mode_id = "true";
-							mode0 { /* IMX477_MODE_3840x2160 */
-								mclk_khz = "24000";
-								num_lanes = "2";
-								tegra_sinterface = "serial_c";
-								phy_mode = "DPHY";
-								discontinuous_clk = "no";
-								dpcm_enable = "false";
-								cil_settletime = "0";
-								lane_polarity = "0";
-								active_w = "3840";
-								active_h = "2160";
-								mode_type = "bayer";
-								pixel_phase = "rggb";
-								csi_pixel_bit_depth = "10";
-								readout_orientation = "90";
-								line_length = "11200";
-								inherent_gain = "1";
-								mclk_multiplier = "80";
-								pix_clk_hz = "300000000";
-								gain_factor = "16";
-								framerate_factor = "1000000";
-								exposure_factor = "1000000";
-								min_gain_val = "16"; /* 1.00x */
-								max_gain_val = "356"; /* 22x */
-								step_gain_val = "1";
-								default_gain = "16"; /* 1.00x */
-								min_hdr_ratio = "1";
-								max_hdr_ratio = "1";
-								min_framerate = "2000000"; /* 2.0 fps */
-								max_framerate = "30000000"; /* 30.0 fps */
-								step_framerate = "1";
-								default_framerate = "30000000"; /* 30.0 fps */
-								min_exp_time = "13"; /* us */
-								max_exp_time = "683709"; /* us */
-								step_exp_time = "1";
-								default_exp_time = "2495"; /* us */
-								embedded_metadata_height = "2";
-							};
-							mode1 { /* IMX477_MODE_1920X1080 */
-								mclk_khz = "24000";
-								num_lanes = "2";
-								tegra_sinterface = "serial_c";
-								phy_mode = "DPHY";
-								discontinuous_clk = "no";
-								dpcm_enable = "false";
-								cil_settletime = "0";
-								lane_polarity = "0";
-								active_w = "1920";
-								active_h = "1080";
-								mode_type = "bayer";
-								pixel_phase = "rggb";
-								csi_pixel_bit_depth = "10";
-								readout_orientation = "90";
-								line_length = "7000";
-								inherent_gain = "1";
-								mclk_multiplier = "80";
-								pix_clk_hz = "300000000";
-								gain_factor = "16";
-								framerate_factor = "1000000";
-								exposure_factor = "1000000";
-								min_gain_val = "16"; /* 1.00x */
-								max_gain_val = "356"; /* 22x */
-								step_gain_val = "1";
-								default_gain = "16"; /* 1.00x */
-								min_hdr_ratio = "1";
-								max_hdr_ratio = "1";
-								min_framerate = "2000000"; /* 2.0 fps */
-								max_framerate = "60000000"; /* 60.0 fps */
-								step_framerate = "1";
-								default_framerate = "60000000"; /* 60.0 fps */
-								min_exp_time = "13"; /* us */
-								max_exp_time = "683709"; /* us */
-								step_exp_time = "1";
-								default_exp_time = "2495"; /* us */
-								embedded_metadata_height = "2";
-							};
-							ports {
-								#address-cells = <1>;
-								#size-cells = <0>;
-								port@0 {
-									reg = <0>;
-									rbpcv3_imx477_out1: endpoint {
-										status = "okay";
-										port-index = <2>;
-										bus-width = <2>;
-										remote-endpoint = <&rbpcv3_imx477_csi_in1>;
-									};
-								};
-							};
-						};
-					};
-				};
-
-				gpio@6000d000 {
-					camera-control-output-low {
-						gpio-hog;
-						output-low;
-						gpios = < CAM1_PWDN 0  CAM0_PWDN 0>;
-						label = "cam1-pwdn", "cam0-pwdn";
-					};
-				};
-			};
-		};
-	};
-};

overlay/tegra234-p3767-camera-p3768-imx477-dual.dts

@@ -12,7 +12,7 @@
 
 / {
 	overlay-name = "Camera IMX477 Dual";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 
 	fragment@0 {
@@ -43,41 +43,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-imx219.dts

@@ -18,7 +18,7 @@
 
 / {
 	overlay-name = "Camera IMX477-A and IMX219-C";
-	jetson-header-name = "Jetson 24pin CSI Connector";
+	jetson-header-name = "Jetson 22pin CSI Connector";
 	compatible = JETSON_COMPATIBLE_P3768;
 
 	/* IMX477 sensor module on CSI PORT A and IMX219 sensor module on CSI PORT B  */
@@ -50,41 +50,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3768-0000+p3767-0000-dynamic.dts

@@ -4,8 +4,6 @@
 /dts-v1/;
 /plugin/;
 
-#include "tegra234-p3768-camera-rbpcv2-imx219.dtsi"
-
 / {
 	overlay-name = "Tegra234 p3768-0000+p3767-xxxx Dynamic Overlay";
 };

overlay/tegra234-p3768-camera-rbpcv2-imx219.dtsi

@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
-
-#define CAM0_RST        TEGRA234_MAIN_GPIO(H, 3)
-#define CAM0_PWDN	TEGRA234_MAIN_GPIO(H, 6)
-#define CAM1_PWDN	TEGRA234_MAIN_GPIO(AC, 0)
-#define CAM_I2C_MUX 	TEGRA234_AON_GPIO(CC, 3)
-
-#include <dt-bindings/tegra234-p3767-0000-common.h>
-#include "tegra234-camera-rbpcv2-imx219.dtsi"
-
-/ {
-	fragment-camera-imx219@0 {
-		target-path = "/";
-		__overlay__ {
-			bus@0 {
-				cam_i2cmux{
-					status = "okay";
-					compatible = "i2c-mux-gpio";
-					#address-cells = <1>;
-					#size-cells = <0>;
-					i2c-parent = <&cam_i2c>;
-					mux-gpios = <&gpio_aon CAM_I2C_MUX GPIO_ACTIVE_HIGH>;
-					i2c@0 {
-						status = "okay";
-						reg = <0>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						rbpcv2_imx219_a@10 {
-							reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
-						};
-					};
-					i2c@1 {
-						status = "okay";
-						reg = <1>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						rbpcv2_imx219_c@10 {
-							reset-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
-						};
-					};
-				};
-				gpio@2200000 {
-					camera-control-output-low {
-						gpio-hog;
-						output-low;
-						gpios = <CAM0_RST 0>;
-						label = "cam0-rst";
-					};
-				};
-			};
-		};
-	};
-};

overlay/tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dts

@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+/*
+ * Jetson Device-tree overlay for Camera Dual-IMX274 on t23x + p3971 platforms
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "dt-bindings/gpio/tegra234-gpio.h"
+#include "dt-bindings/clock/tegra234-clock.h"
+#include "tegra234-p3971-0000-camera-imx274-dual.dtsi"
+
+
+/ {
+	overlay-name = "Jetson Camera Dual-IMX274";
+	jetson-header-name = "Jetson AGX CSI Connector";
+	compatible = "nvidia,p3971-0000+p3701-0008";
+
+	fragment@0 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@1 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a/ports/port@0/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_csi_in0>;
+		};
+	};
+	fragment@2 {
+		target-path = "/tegra-camera-platform/modules/module0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			badge = "imx274_bottom_A6V26";
+			position = "bottom";
+			orientation = "0";
+		};
+	};
+	fragment@3 {
+		target-path = "/tegra-camera-platform/modules/module0/drivernode0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_sensor";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a";
+		};
+	};
+	fragment@4 {
+		target-path = "/tegra-camera-platform/modules/module0/drivernode1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_lens";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx274@A6V26/";
+		};
+	};
+	fragment@5 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@6 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a/ports/port@0/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_csi_in1>;
+		};
+	};
+	fragment@7 {
+		target-path = "/tegra-camera-platform/modules/module1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			badge = "imx274_top_A6V26";
+			position = "top";
+			orientation = "0";
+		};
+	};
+	fragment@8 {
+		target-path = "/tegra-camera-platform/modules/module1/drivernode0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_sensor";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a";
+		};
+	};
+	fragment@9 {
+		target-path = "/tegra-camera-platform/modules/module1/drivernode1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_lens";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx274@A6V26/";
+		};
+	};
+	/* Enable VI ports - capture_vi_base, */
+	fragment@10 {
+		target-path = "/tegra-capture-vi";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			num-channels=<2>;
+		};
+	};
+	fragment@11 {
+		target-path = "/tegra-capture-vi/ports/port@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@12 {
+		target-path = "/tegra-capture-vi/ports/port@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@13 {
+		target-path = "/tegra-capture-vi/ports/port@0/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <0>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_csi_out0>;
+
+		};
+	};
+	fragment@14 {
+		target-path = "/tegra-capture-vi/ports/port@1/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <2>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_csi_out1>;
+		};
+	};
+	/* Enable CSI ports */
+	fragment@15 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			num-channels=<2>;
+		};
+	};
+	fragment@16 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@17 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@18 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@0/endpoint@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <0>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_imx274_out0>;
+		};
+	};
+	fragment@19 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@20 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@1/endpoint@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_vi_in0>;
+		};
+	};
+	fragment@21 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@22 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@23 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@0/endpoint@2";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <2>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_imx274_out1>;
+		};
+	};
+	fragment@24 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@25 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@1/endpoint@3";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_vi_in1>;
+		};
+	};
+	/* tegra-camera-platform settings */
+	fragment@26 {
+		target-path = "/tegra-camera-platform";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			num_csi_lanes = <8>;
+			max_lane_speed = <1500000>;
+			min_bits_per_pixel = <10>;
+			vi_peak_byte_per_pixel = <2>;
+			vi_bw_margin_pct = <25>;
+			isp_peak_byte_per_pixel = <5>;
+			isp_bw_margin_pct = <25>;
+		};
+	};
+	/* pca9646 i2c mux */
+	fragment@27 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+};

overlay/tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dts

@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+/dts-v1/;
+/plugin/;
+
+#include "dt-bindings/gpio/tegra234-gpio.h"
+#include "dt-bindings/clock/tegra234-clock.h"
+#include "tegra234-camera-p3762-a00.dtsi"
+
+/* camera control gpio definitions */
+#define CAM0_RST_L      TEGRA234_MAIN_GPIO(H, 3)
+#define CAM0_PWDN       TEGRA234_MAIN_GPIO(E, 6)
+#define CAM1_RST_L      TEGRA234_MAIN_GPIO(AC, 1)
+#define CAM1_PWDN       TEGRA234_MAIN_GPIO(AC, 0)
+#define PWR_EN      	TEGRA234_MAIN_GPIO(AC, 7)
+#define GYRO1_IRQ_GPIO  TEGRA234_AON_GPIO(CC, 1)
+#define ACCE1_IRQ_GPIO  TEGRA234_AON_GPIO(CC, 0)
+
+/ {
+	overlay-name = "Jetson Camera Hawk-Owl p3762 module";
+	jetson-header-name = "Jetson AGX CSI Connector";
+	compatible = "nvidia,p3971-0000+p3701-0008";
+
+	fragment-camera-hawk-owl@0 {
+		target-path = "/";
+		__overlay__ {
+			bus@0 {
+				/* set camera gpio direction to output */
+				gpio@2200000 {
+					camera-control-output-low {
+						gpio-hog;
+						output-low;
+						gpios = <CAM0_RST_L 0 CAM0_PWDN 0
+								CAM1_RST_L 0 CAM1_PWDN 0>;
+						label = "cam0-rst", "cam0-pwdn",
+								"cam1-rst", "cam1-pwdn";
+					};
+				};
+				i2c@3180000 {
+					max96712_b@62 {
+						compatible = "nvidia,max96712";
+						reg = <0x62>;
+						channel = "b";
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						status = "okay";
+					};
+					ar0234_i@30 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x38>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+					ar0234_j@32 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x3a>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+					ar0234_k@34 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x3c>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+					ar0234_l@36 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x3e>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+				};
+				i2c@31e0000 {
+					max96712_a@62 {
+						compatible = "nvidia,max96712";
+						reg = <0x62>;
+						channel = "a";
+						pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+						status = "okay";
+					};
+					virtual_i2c_mux@50 {
+						reg = <0x50>;
+						compatible = "nvidia,virtual-i2c-mux";
+						#address-cells = <1>;
+						#size-cells = <0>;
+						i2c-parent = <&dp_aux_ch3_i2c>;
+						status = "okay";
+
+						i2c@0 {
+							reg = <0>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							bmi088_a@69 {
+								compatible = "bmi,bmi088";
+								reg = <0x69>;
+								accel_i2c_addr = <0x19>;
+								/* Old BMI088 driver uses *_gpio property and the latest
+								 * BMI088 driver uses *-gpios property. Have both versions
+								 * to maintain backward compatibility.
+								 */
+								accel_irq_gpio = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								gyro_irq_gpio = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								accel_irq-gpios = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								gyro_irq-gpios = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								accel_matrix = [01 00 00 00 01 00 00 00 01];
+								gyro_matrix = [01 00 00 00 01 00 00 00 01];
+								gyro_reg_0x18 = <0x81>;
+								timestamps = <&hte_aon ACCE1_IRQ_GPIO>, <&hte_aon GYRO1_IRQ_GPIO>;
+								timestamp-names = "accelerometer", "gyroscope";
+								status = "okay";
+							};
+							ar0234_a@30 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x40>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_b@31 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x40>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+						};
+						i2c@1 {
+							reg = <1>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							ar0234_c@32 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x15>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_d@33 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x15>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_e@34 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x44>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_f@35 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x44>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_g@36 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x46>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_h@37 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x46>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+						};
+					};
+				};
+			};
+		};
+	};
+	fragment-cam-cdi-tsc@0 {
+		target-path = "/";
+		__overlay__ {
+			tsc_sig_gen@c6a0000 {
+				status = "okay";
+				generator@380 {
+					status = "okay";
+				};
+			};
+		};
+	};
+};

overlay/tegra234-p3971-0000-camera-imx274-dual.dtsi

@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+#include <dt-bindings/clock/tegra234-clock.h>
+#include <dt-bindings/gpio/tegra234-gpio.h>
+#include "tegra234-camera-imx274-dual.dtsi"
+
+#define CAM0_RST_L	TEGRA234_MAIN_GPIO(H, 3)
+#define CAM0_PWDN	TEGRA234_MAIN_GPIO(E, 6)
+
+/* camera control gpio definitions */
+/ {
+	fragment-camera-dual-imx274@0 {
+		target-path = "/bus@0";
+		__overlay__ {
+			gpio@2200000 {
+				camera-control-output-low {
+					gpio-hog;
+					output-low;
+					gpios = <CAM0_RST_L GPIO_ACTIVE_HIGH CAM0_PWDN GPIO_ACTIVE_HIGH>;
+					label = "cam0-rst", "cam0-pwdn";
+				};
+			};
+			i2c@3180000 {
+				tca9546@70 {
+					compatible = "nxp,pca9546";
+					reg = <0x70>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					skip_mux_detect = "yes";
+					vcc-supply = <&vdd_1v8_ls>;
+					i2c@0 {
+						reg = <0>;
+						i2c-mux,deselect-on-exit;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						imx274_a@1a {
+							/* Define any required hw resources needed by driver */
+							/* ie. clocks, io pins, power sources */
+							clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+									<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+							clock-names = "extperiph1", "pllp_grtba";
+							mclk = "extperiph1";
+							reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+						};
+					};
+					i2c@1 {
+						reg = <1>;
+						i2c-mux,deselect-on-exit;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						imx274_c@1a {
+							/* Define any required hw resources needed by driver */
+							/* ie. clocks, io pins, power sources */
+							clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+									<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+							clock-names = "extperiph1", "pllp_grtba";
+							mclk = "extperiph1";
+							reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+						};
+					};
+				};
+			};
+		};
+	};
+};

staging/Makefile

@@ -1,27 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-# Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-DTC_FLAGS += -@
-
-old-dtb := $(dtb-y)
-old-dtbo := $(dtbo-y)
-dtb-y :=
-dtbo-y :=
-makefile-path := t23x/nv-public/staging
-
-dtb-y += tegra234-p3737-0000+p3701-0004.dtb
-dtb-y += tegra234-p3737-0000+p3701-0005.dtb
-dtb-y += tegra234-p3737-0000+p3701-0008.dtb
-dtb-y += tegra234-p3768-0000+p3767-0001.dtb
-dtb-y += tegra234-p3768-0000+p3767-0003.dtb
-dtb-y += tegra234-p3768-0000+p3767-0004.dtb
-
-ifneq ($(dtb-y),)
-dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))
-endif
-ifneq ($(dtbo-y),)
-dtbo-y := $(addprefix $(makefile-path)/,$(dtbo-y))
-endif
-
-dtb-y += $(old-dtb)
-dtbo-y += $(old-dtbo)

staging/tegra234-p3737-0000+p3701-0004.dts

@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2023 NVIDIA CORPORATION. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "tegra234-p3737-0000+p3701-0000.dts"
-
-/ {
-	model = "NVIDIA Jetson AGX Orin Developer Kit";
-	compatible = "nvidia,p3737-0000+p3701-0004", "nvidia,p3701-0004", "nvidia,tegra234";
-};

staging/tegra234-p3737-0000+p3701-0005.dts

@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2023 NVIDIA CORPORATION. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "tegra234-p3737-0000+p3701-0000.dts"
-
-/ {
-	model = "NVIDIA Jetson AGX Orin Developer Kit";
-	compatible = "nvidia,p3737-0000+p3701-0005", "nvidia,p3701-0005", "nvidia,tegra234";
-};

staging/tegra234-p3737-0000+p3701-0008.dts

@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2023 NVIDIA CORPORATION. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "tegra234-p3737-0000+p3701-0000.dts"
-
-/ {
-	model = "NVIDIA Jetson AGX Orin Developer Kit";
-	compatible = "nvidia,p3737-0000+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
-};

staging/tegra234-p3768-0000+p3767-0001.dts

@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2023 NVIDIA CORPORATION. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "tegra234-p3768-0000+p3767-0000.dts"
-
-/ {
-	compatible = "nvidia,p3768-0000+p3767-0001", "nvidia,p3767-0001", "nvidia,tegra234";
-	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit";
-};

staging/tegra234-p3768-0000+p3767-0003.dts

@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2023 NVIDIA CORPORATION. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "tegra234-p3768-0000+p3767-0000.dts"
-
-/ {
-	compatible = "nvidia,p3768-0000+p3767-0003", "nvidia,p3767-0003", "nvidia,tegra234";
-	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit";
-};

staging/tegra234-p3768-0000+p3767-0004.dts

@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2023 NVIDIA CORPORATION. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "tegra234-p3768-0000+p3767-0000.dts"
-
-/ {
-	compatible = "nvidia,p3768-0000+p3767-0004", "nvidia,p3767-0004", "nvidia,tegra234";
-	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit";
-};

tegra234-p3701-0000.dtsi

@@ -1,146 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 
-#include "tegra234.dtsi"
 #include "tegra234-p3701.dtsi"
 
 / {
 	model = "NVIDIA Jetson AGX Orin";
 	compatible = "nvidia,p3701-0000", "nvidia,tegra234";
 
-	bus@0 {
-		i2c@3160000 {
-			status = "okay";
-
-			eeprom@50 {
-				compatible = "atmel,24c02";
-				reg = <0x50>;
-
-				label = "module";
-				vcc-supply = <&vdd_1v8_hs>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
-			};
-		};
-
-		spi@3270000 {
-			status = "okay";
-
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <102000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-			};
-		};
-
-		mmc@3400000 {
-			status = "okay";
-			bus-width = <4>;
-			cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
-			disable-wp;
-		};
-
-		mmc@3460000 {
-			status = "okay";
-			bus-width = <8>;
-			non-removable;
-		};
-
-		padctl@3520000 {
-			vclamp-usb-supply = <&vdd_1v8_ao>;
-			avdd-usb-supply = <&vdd_3v3_ao>;
-
-			ports {
-				usb2-0 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-1 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-2 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-3 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-			};
-		};
-
-		rtc@c2a0000 {
-			status = "okay";
-		};
-
-		pmc@c360000 {
-			nvidia,invert-interrupt;
-		};
-	};
-
-	vdd_5v0_sys: regulator-vdd-5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "VIN_SYS_5V0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_1v8_ls: regulator-vdd-1v8-ls {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_LS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_hs: regulator-vdd-1v8-hs {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_HS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_ao: regulator-vdd-1v8-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_AO";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_3v3_ao: regulator-vdd-3v3-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_3V3_AO";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_3V3_PCIE";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
-		regulator-boot-on;
-		enable-active-high;
-	};
-
-	vdd_12v_pcie: regulator-vdd-12v-pcie {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_12V_PCIE";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
-		regulator-boot-on;
-	};
-
 	thermal-zones {
 		tj-thermal {
 			polling-delay = <1000>;

tegra234-p3701-0008.dtsi

@@ -1,112 +1,29 @@
 // SPDX-License-Identifier: GPL-2.0
 
-#include "tegra234.dtsi"
 #include "tegra234-p3701.dtsi"
 
 / {
 	compatible = "nvidia,p3701-0008", "nvidia,tegra234";
 
-	bus@0 {
-		i2c@3160000 {
+	thermal-zones {
+		tj-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <1000>;
 			status = "okay";
 
-			eeprom@50 {
-				compatible = "atmel,24c02";
-				reg = <0x50>;
-				label = "module";
-				vcc-supply = <&vdd_1v8_hs>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
+			trips {
+				tj_trip_active0: active-0 {
+					temperature = <85000>;
+					hysteresis = <4000>;
+					type = "active";
+				};
+
+				tj_trip_active1: active-1 {
+					temperature = <105000>;
+					hysteresis = <4000>;
+					type = "active";
+				};
 			};
 		};
-
-		spi@3270000 {
-			status = "okay";
-
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <102000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-			};
-		};
-
-		mmc@3460000 {
-			status = "okay";
-			bus-width = <8>;
-			non-removable;
-		};
-
-		i2c@c240000 {
-			status = "okay";
-		};
-
-		rtc@c2a0000 {
-			status = "okay";
-		};
-
-		pmc@c360000 {
-			nvidia,invert-interrupt;
-		};
-	};
-
-	bpmp {
-		i2c {
-			status = "okay";
-
-			thermal-sensor@4c {
-				status = "okay";
-				reg = <0x4c>;
-				vcc-supply = <&vdd_1v8_ao>;
-			};
-		};
-
-		thermal {
-			status = "okay";
-		};
-	};
-
-	vdd_1v8_ao: regulator-vdd-1v8-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_AO";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_hs: regulator-vdd-1v8-hs {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_HS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_ls: regulator-vdd-1v8-ls {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_LS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_3v3_ao: regulator-vdd-3v3-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd-AO-3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	vdd_5v0_sys: regulator-vdd-5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "VIN_SYS_5V0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
 	};
 };

tegra234-p3701.dtsi

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 
+#include "tegra234.dtsi"
+
 / {
 	compatible = "nvidia,p3701", "nvidia,tegra234";
 
@@ -44,5 +46,181 @@
 				status = "okay";
 			};
 		};
+
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+
+				label = "module";
+				vcc-supply = <&vdd_1v8_hs>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
+		spi@3270000 {
+			status = "okay";
+
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <102000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+		};
+
+		mmc@3460000 {
+			status = "okay";
+			bus-width = <8>;
+			non-removable;
+		};
+
+		padctl@3520000 {
+			vclamp-usb-supply = <&vdd_1v8_ao>;
+			avdd-usb-supply = <&vdd_3v3_ao>;
+
+			ports {
+				usb2-0 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-1 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-2 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-3 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+			};
+		};
+
+		i2c@c240000 {
+			status = "okay";
+
+			power-sensor@40 {
+				compatible = "ti,ina3221";
+				reg = <0x40>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					label = "VDD_GPU_SOC";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "VDD_CPU_CV";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					label = "VIN_SYS_5V0";
+					shunt-resistor-micro-ohms = <2000>;
+					ti,summation-disable;
+				};
+			};
+
+			power-sensor@41 {
+				compatible = "ti,ina3221";
+				reg = <0x41>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					status = "disabled";
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "VDDQ_VDD2_1V8AO";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					status = "disabled";
+				};
+			};
+		};
+
+		rtc@c2a0000 {
+			status = "okay";
+		};
+
+		pmc@c360000 {
+			nvidia,invert-interrupt;
+		};
+	};
+
+	bpmp {
+		i2c {
+			status = "okay";
+
+			thermal-sensor@4c {
+				compatible = "ti,tmp451";
+				status = "okay";
+				reg = <0x4c>;
+				vcc-supply = <&vdd_1v8_ao>;
+			};
+		};
+
+		thermal {
+			status = "okay";
+		};
+	};
+
+	vdd_1v8_ao: regulator-vdd-1v8-ao {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_AO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_hs: regulator-vdd-1v8-hs {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_HS";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_ls: regulator-vdd-1v8-ls {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_LS";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_ao: regulator-vdd-3v3-ao {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_AO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdd_5v0_sys: regulator-vdd-5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "VIN_SYS_5V0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
 	};
 };

tegra234-p3737-0000+p3701-0000.dts

@@ -1,439 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/input/gpio-keys.h>
-
+// Module files must be included first
 #include "tegra234-p3701-0000.dtsi"
-#include "tegra234-p3737-0000.dtsi"
+#include "tegra234-p3737-0000+p3701.dtsi"
 
 / {
 	model = "NVIDIA Jetson AGX Orin Developer Kit";
 	compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
-
-	aliases {
-		serial0 = &tcu;
-		serial1 = &uarta;
-	};
-
-	chosen {
-		bootargs = "console=ttyTCU0,115200n8";
-		stdout-path = "serial0:115200n8";
-	};
-
-	bus@0 {
-		serial@3100000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		serial@31d0000 {
-			current-speed = <115200>;
-			status = "okay";
-		};
-
-		pwm@32a0000 {
-			assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
-			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
-			status = "okay";
-		};
-
-		hda@3510000 {
-			nvidia,model = "NVIDIA Jetson AGX Orin HDA";
-			status = "okay";
-		};
-
-		padctl@3520000 {
-			status = "okay";
-
-			pads {
-				usb2 {
-					lanes {
-						usb2-0 {
-							status = "okay";
-						};
-
-						usb2-1 {
-							status = "okay";
-						};
-
-						usb2-2 {
-							status = "okay";
-						};
-
-						usb2-3 {
-							status = "okay";
-						};
-					};
-				};
-
-				usb3 {
-					lanes {
-						usb3-0 {
-							status = "okay";
-						};
-
-						usb3-1 {
-							status = "okay";
-						};
-
-						usb3-2 {
-							status = "okay";
-						};
-					};
-				};
-			};
-
-			ports {
-				usb2-0 {
-					mode = "otg";
-					usb-role-switch;
-					status = "okay";
-					port {
-						hs_typec_p1: endpoint {
-							remote-endpoint = <&hs_ucsi_ccg_p1>;
-						};
-					};
-				};
-
-				usb2-1 {
-					mode = "host";
-					status = "okay";
-					port {
-						hs_typec_p0: endpoint {
-							remote-endpoint = <&hs_ucsi_ccg_p0>;
-						};
-					};
-				};
-
-				usb2-2 {
-					mode = "host";
-					status = "okay";
-				};
-
-				usb2-3 {
-					mode = "host";
-					status = "okay";
-				};
-
-				usb3-0 {
-					nvidia,usb2-companion = <1>;
-					status = "okay";
-					port {
-						ss_typec_p0: endpoint {
-							remote-endpoint = <&ss_ucsi_ccg_p0>;
-						};
-					};
-				};
-
-				usb3-1 {
-					nvidia,usb2-companion = <0>;
-					status = "okay";
-					port {
-						ss_typec_p1: endpoint {
-							remote-endpoint = <&ss_ucsi_ccg_p1>;
-						};
-					};
-				};
-
-				usb3-2 {
-					nvidia,usb2-companion = <3>;
-					status = "okay";
-				};
-			};
-		};
-
-		usb@3550000 {
-			status = "okay";
-
-			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
-			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
-			phy-names = "usb2-0", "usb3-0";
-		};
-
-		usb@3610000 {
-			status = "okay";
-
-			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
-			       <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
-			       <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
-			       <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
-			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
-			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
-			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
-			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
-				    "usb3-0", "usb3-1", "usb3-2";
-		};
-
-		ethernet@6800000 {
-			status = "okay";
-
-			phy-handle = <&mgbe0_phy>;
-			phy-mode = "10gbase-r";
-
-			mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				mgbe0_phy: phy@0 {
-					compatible = "ethernet-phy-ieee802.3-c45";
-					reg = <0x0>;
-
-					#phy-cells = <0>;
-				};
-			};
-		};
-
-		i2c@c240000 {
-			status = "okay";
-
-			typec@8 {
-				compatible = "cypress,cypd4226";
-				reg = <0x08>;
-				interrupt-parent = <&gpio>;
-				interrupts = <TEGRA234_MAIN_GPIO(Y, 4) IRQ_TYPE_LEVEL_LOW>;
-				firmware-name = "nvidia,jetson-agx-xavier";
-				status = "okay";
-
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				ccg_typec_con0: connector@0 {
-					compatible = "usb-c-connector";
-					reg = <0>;
-					label = "USB-C";
-					data-role = "host";
-
-					ports {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						port@0 {
-							reg = <0>;
-							hs_ucsi_ccg_p0: endpoint {
-								remote-endpoint = <&hs_typec_p0>;
-							};
-						};
-
-						port@1 {
-							reg = <1>;
-							ss_ucsi_ccg_p0: endpoint {
-								remote-endpoint = <&ss_typec_p0>;
-							};
-						};
-					};
-				};
-
-				ccg_typec_con1: connector@1 {
-					compatible = "usb-c-connector";
-					reg = <1>;
-					label = "USB-C";
-					data-role = "dual";
-
-					ports {
-						#address-cells = <1>;
-						#size-cells = <0>;
-
-						port@0 {
-							reg = <0>;
-							hs_ucsi_ccg_p1: endpoint {
-								remote-endpoint = <&hs_typec_p1>;
-							};
-						};
-
-						port@1 {
-							reg = <1>;
-							ss_ucsi_ccg_p1: endpoint {
-								remote-endpoint = <&ss_typec_p1>;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		pcie@14100000 {
-			status = "okay";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
-			phys = <&p2u_hsio_3>;
-			phy-names = "p2u-0";
-		};
-
-		pcie@14160000 {
-			status = "okay";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
-			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
-			       <&p2u_hsio_7>;
-			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
-		};
-
-		pcie@141a0000 {
-			status = "okay";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ls>;
-			vpcie3v3-supply = <&vdd_3v3_pcie>;
-			vpcie12v-supply = <&vdd_12v_pcie>;
-
-			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
-			       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
-			       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
-			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
-				    "p2u-5", "p2u-6", "p2u-7";
-		};
-
-		pcie-ep@141a0000 {
-			status = "disabled";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ls>;
-
-			reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
-
-			nvidia,refclk-select-gpios = <&gpio_aon
-						      TEGRA234_AON_GPIO(AA, 4)
-						      GPIO_ACTIVE_HIGH>;
-
-			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
-			       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
-			       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
-			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
-				    "p2u-5", "p2u-6", "p2u-7";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		status = "okay";
-
-		key-force-recovery {
-			label = "Force Recovery";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <BTN_1>;
-		};
-
-		key-power {
-			label = "Power";
-			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_POWER>;
-			wakeup-event-action = <EV_ACT_ASSERTED>;
-			wakeup-source;
-		};
-
-		key-suspend {
-			label = "Suspend";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_SLEEP>;
-		};
-	};
-
-	pwm-fan {
-		cooling-levels = <66 215 255>;
-	};
-
-	serial {
-		status = "okay";
-	};
-
-	sound {
-		compatible = "nvidia,tegra186-audio-graph-card";
-		status = "okay";
-
-		dais = /* ADMAIF (FE) Ports */
-		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
-		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
-		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
-		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
-		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
-		       /* XBAR Ports */
-		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
-		       <&xbar_i2s6_port>, <&xbar_dmic3_port>,
-		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
-		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
-		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
-		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
-		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
-		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
-		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
-		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
-		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
-		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
-		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
-		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
-		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
-		       <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
-		       <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
-		       <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
-		       <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
-		       <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
-		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
-		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
-		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
-		       <&xbar_asrc_in7_port>,
-		       <&xbar_ope1_in_port>,
-		       /* HW accelerators */
-		       <&sfc1_out_port>, <&sfc2_out_port>,
-		       <&sfc3_out_port>, <&sfc4_out_port>,
-		       <&mvc1_out_port>, <&mvc2_out_port>,
-		       <&amx1_out_port>, <&amx2_out_port>,
-		       <&amx3_out_port>, <&amx4_out_port>,
-		       <&adx1_out1_port>, <&adx1_out2_port>,
-		       <&adx1_out3_port>, <&adx1_out4_port>,
-		       <&adx2_out1_port>, <&adx2_out2_port>,
-		       <&adx2_out3_port>, <&adx2_out4_port>,
-		       <&adx3_out1_port>, <&adx3_out2_port>,
-		       <&adx3_out3_port>, <&adx3_out4_port>,
-		       <&adx4_out1_port>, <&adx4_out2_port>,
-		       <&adx4_out3_port>, <&adx4_out4_port>,
-		       <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
-		       <&mix_out4_port>, <&mix_out5_port>,
-		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
-		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
-		       <&ope1_out_port>,
-		       /* BE I/O Ports */
-		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
-		       <&dmic3_port>;
-
-		label = "NVIDIA Jetson AGX Orin APE";
-
-		widgets = "Microphone",	"CVB-RT MIC Jack",
-			  "Microphone",	"CVB-RT MIC",
-			  "Headphone",	"CVB-RT HP Jack",
-			  "Speaker",	"CVB-RT SPK";
-
-		routing = /* I2S1 <-> RT5640 */
-			  "CVB-RT AIF1 Playback",	"I2S1 DAP-Playback",
-			  "I2S1 DAP-Capture",		"CVB-RT AIF1 Capture",
-			  /* RT5640 codec controls */
-			  "CVB-RT HP Jack",		"CVB-RT HPOL",
-			  "CVB-RT HP Jack",		"CVB-RT HPOR",
-			  "CVB-RT IN1P",		"CVB-RT MIC Jack",
-			  "CVB-RT IN2P",		"CVB-RT MIC Jack",
-			  "CVB-RT SPK",			"CVB-RT SPOLP",
-			  "CVB-RT SPK",			"CVB-RT SPORP",
-			  "CVB-RT DMIC1",		"CVB-RT MIC",
-			  "CVB-RT DMIC2",		"CVB-RT MIC";
-	};
-
-	thermal-zones {
-		tj-thermal {
-			cooling-maps {
-				map-active-0 {
-					cooling-device = <&fan 0 1>;
-					trip = <&tj_trip_active0>;
-				};
-
-				map-active-1 {
-					cooling-device = <&fan 1 2>;
-					trip = <&tj_trip_active1>;
-				};
-			};
-		};
-	};
 };

tegra234-p3737-0000+p3701-0008.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+// Module files must be included first
+#include "tegra234-p3701-0008.dtsi"
+#include "tegra234-p3737-0000+p3701.dtsi"
+
+/ {
+	model = "NVIDIA Jetson AGX Orin Developer Kit";
+	compatible = "nvidia,p3737-0000+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
+};

tegra234-p3737-0000+p3701.dtsi

@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/clock/tegra234-clock.h>
+#include <dt-bindings/gpio/tegra234-gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/sound/rt5640.h>
+
+/ {
+	aliases {
+		serial0 = &tcu;
+		serial1 = &uarta;
+	};
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901000 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		serial@3100000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@56 {
+				compatible = "atmel,24c02";
+				reg = <0x56>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_sys>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
+		serial@31d0000 {
+			current-speed = <115200>;
+			status = "okay";
+		};
+
+		i2c@31e0000 {
+			status = "okay";
+
+			audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+				sound-name-prefix = "CVB-RT";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s1_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+		};
+
+		pwm@3280000 {
+			status = "okay";
+		};
+
+		pwm@32a0000 {
+			assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			status = "okay";
+		};
+
+		pwm@32c0000 {
+			status = "okay";
+		};
+
+		pwm@32f0000 {
+			status = "okay";
+		};
+
+		mmc@3400000 {
+			status = "okay";
+			bus-width = <4>;
+			cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
+			disable-wp;
+		};
+
+		hda@3510000 {
+			nvidia,model = "NVIDIA Jetson AGX Orin HDA";
+			status = "okay";
+		};
+
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-0 {
+							status = "okay";
+						};
+
+						usb2-1 {
+							status = "okay";
+						};
+
+						usb2-2 {
+							status = "okay";
+						};
+
+						usb2-3 {
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							status = "okay";
+						};
+
+						usb3-1 {
+							status = "okay";
+						};
+
+						usb3-2 {
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					mode = "otg";
+					usb-role-switch;
+					status = "okay";
+
+					port {
+						hs_typec_p1: endpoint {
+							remote-endpoint = <&hs_ucsi_ccg_p1>;
+						};
+					};
+				};
+
+				usb2-1 {
+					mode = "host";
+					status = "okay";
+
+					port {
+						hs_typec_p0: endpoint {
+							remote-endpoint = <&hs_ucsi_ccg_p0>;
+						};
+					};
+				};
+
+				usb2-2 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+
+					port {
+						ss_typec_p0: endpoint {
+							remote-endpoint = <&ss_ucsi_ccg_p0>;
+						};
+					};
+				};
+
+				usb3-1 {
+					nvidia,usb2-companion = <0>;
+					status = "okay";
+
+					port {
+						ss_typec_p1: endpoint {
+							remote-endpoint = <&ss_ucsi_ccg_p1>;
+						};
+					};
+				};
+
+				usb3-2 {
+					nvidia,usb2-companion = <3>;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3550000 {
+			status = "okay";
+
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
+			phy-names = "usb2-0", "usb3-0";
+		};
+
+		usb@3610000 {
+			status = "okay";
+
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			       <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+			       <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+			       <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
+			       <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
+				    "usb3-0", "usb3-1", "usb3-2";
+		};
+
+		ethernet@6800000 {
+			status = "okay";
+
+			phy-handle = <&mgbe0_phy>;
+			phy-mode = "10gbase-r";
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mgbe0_phy: phy@0 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x0>;
+
+					#phy-cells = <0>;
+				};
+			};
+		};
+
+		i2c@c240000 {
+			status = "okay";
+
+			typec@8 {
+				compatible = "cypress,cypd4226";
+				reg = <0x08>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(Y, 4) IRQ_TYPE_LEVEL_LOW>;
+				firmware-name = "nvidia,jetson-agx-xavier";
+				status = "okay";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ccg_typec_con0: connector@0 {
+					compatible = "usb-c-connector";
+					reg = <0>;
+					label = "USB-C";
+					data-role = "host";
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0>;
+
+							hs_ucsi_ccg_p0: endpoint {
+								remote-endpoint = <&hs_typec_p0>;
+							};
+						};
+
+						port@1 {
+							reg = <1>;
+
+							ss_ucsi_ccg_p0: endpoint {
+								remote-endpoint = <&ss_typec_p0>;
+							};
+						};
+					};
+				};
+
+				ccg_typec_con1: connector@1 {
+					compatible = "usb-c-connector";
+					reg = <1>;
+					label = "USB-C";
+					data-role = "dual";
+
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						port@0 {
+							reg = <0>;
+
+							hs_ucsi_ccg_p1: endpoint {
+								remote-endpoint = <&hs_typec_p1>;
+							};
+						};
+
+						port@1 {
+							reg = <1>;
+
+							ss_ucsi_ccg_p1: endpoint {
+								remote-endpoint = <&ss_typec_p1>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		pcie@14100000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+			phys = <&p2u_hsio_3>;
+			phy-names = "p2u-0";
+		};
+
+		pcie@14160000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+			       <&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+		};
+
+		pcie@141a0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_1v8_ls>;
+			vpcie3v3-supply = <&vdd_3v3_pcie>;
+			vpcie12v-supply = <&vdd_12v_pcie>;
+
+			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+			       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+			       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				    "p2u-5", "p2u-6", "p2u-7";
+		};
+
+		pcie-ep@141a0000 {
+			status = "disabled";
+
+			vddio-pex-ctl-supply = <&vdd_1v8_ls>;
+
+			reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
+
+			nvidia,refclk-select-gpios = <&gpio_aon
+						      TEGRA234_AON_GPIO(AA, 4)
+						      GPIO_ACTIVE_HIGH>;
+
+			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+			       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+			       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				    "p2u-5", "p2u-6", "p2u-7";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		status = "okay";
+
+		key-force-recovery {
+			label = "Force Recovery";
+			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <BTN_1>;
+		};
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_POWER>;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+			wakeup-source;
+		};
+
+		key-suspend {
+			label = "Suspend";
+			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_SLEEP>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <66 215 255>;
+		pwms = <&pwm3 0 45334>;
+		#cooling-cells = <2>;
+	};
+
+	serial {
+		status = "okay";
+	};
+
+	sound {
+		compatible = "nvidia,tegra186-audio-graph-card";
+		status = "okay";
+
+		dais = /* ADMAIF (FE) Ports */
+		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+		       /* XBAR Ports */
+		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+		       <&xbar_i2s6_port>, <&xbar_dmic3_port>,
+		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+		       <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
+		       <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
+		       <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
+		       <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
+		       <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
+		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
+		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
+		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
+		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
+		       /* HW accelerators */
+		       <&sfc1_out_port>, <&sfc2_out_port>,
+		       <&sfc3_out_port>, <&sfc4_out_port>,
+		       <&mvc1_out_port>, <&mvc2_out_port>,
+		       <&amx1_out_port>, <&amx2_out_port>,
+		       <&amx3_out_port>, <&amx4_out_port>,
+		       <&adx1_out1_port>, <&adx1_out2_port>,
+		       <&adx1_out3_port>, <&adx1_out4_port>,
+		       <&adx2_out1_port>, <&adx2_out2_port>,
+		       <&adx2_out3_port>, <&adx2_out4_port>,
+		       <&adx3_out1_port>, <&adx3_out2_port>,
+		       <&adx3_out3_port>, <&adx3_out4_port>,
+		       <&adx4_out1_port>, <&adx4_out2_port>,
+		       <&adx4_out3_port>, <&adx4_out4_port>,
+		       <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
+		       <&mix_out4_port>, <&mix_out5_port>,
+		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
+		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
+		       /* BE I/O Ports */
+		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
+		       <&dmic3_port>;
+
+		label = "NVIDIA Jetson AGX Orin APE";
+
+		widgets = "Microphone",	"CVB-RT MIC Jack",
+			  "Microphone",	"CVB-RT MIC",
+			  "Headphone",	"CVB-RT HP Jack",
+			  "Speaker",	"CVB-RT SPK";
+
+		routing = /* I2S1 <-> RT5640 */
+			  "CVB-RT AIF1 Playback",	"I2S1 DAP-Playback",
+			  "I2S1 DAP-Capture",		"CVB-RT AIF1 Capture",
+			  /* RT5640 codec controls */
+			  "CVB-RT HP Jack",		"CVB-RT HPOL",
+			  "CVB-RT HP Jack",		"CVB-RT HPOR",
+			  "CVB-RT IN1P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2P",		"CVB-RT MIC Jack",
+			  "CVB-RT SPK",			"CVB-RT SPOLP",
+			  "CVB-RT SPK",			"CVB-RT SPORP",
+			  "CVB-RT DMIC1",		"CVB-RT MIC",
+			  "CVB-RT DMIC2",		"CVB-RT MIC";
+	};
+
+	thermal-zones {
+		tj-thermal {
+			cooling-maps {
+				map-active-0 {
+					cooling-device = <&fan 0 1>;
+					trip = <&tj_trip_active0>;
+				};
+
+				map-active-1 {
+					cooling-device = <&fan 1 2>;
+					trip = <&tj_trip_active1>;
+				};
+			};
+		};
+	};
+
+	vdd_1v8_sys: regulator-vdd-1v8-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_SYS";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_PCIE";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	vdd_12v_pcie: regulator-vdd-12v-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_12V_PCIE";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+		regulator-boot-on;
+	};
+};

tegra234-p3737-0000.dtsi

@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/sound/rt5640.h>
-
-/ {
-	compatible = "nvidia,p3737-0000";
-
-	bus@0 {
-		aconnect@2900000 {
-			ahub@2900800 {
-				i2s@2901000 {
-					ports {
-						port@1 {
-							endpoint {
-								dai-format = "i2s";
-								remote-endpoint = <&rt5640_ep>;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		i2c@3160000 {
-			status = "okay";
-
-			eeprom@56 {
-				compatible = "atmel,24c02";
-				reg = <0x56>;
-
-				label = "system";
-				vcc-supply = <&vdd_1v8_sys>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
-			};
-		};
-
-		i2c@31e0000 {
-			status = "okay";
-
-			audio-codec@1c {
-				compatible = "realtek,rt5640";
-				reg = <0x1c>;
-				interrupt-parent = <&gpio>;
-				interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
-				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
-				clock-names = "mclk";
-				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
-				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
-				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
-				sound-name-prefix = "CVB-RT";
-
-				port {
-					rt5640_ep: endpoint {
-						remote-endpoint = <&i2s1_dap>;
-						mclk-fs = <256>;
-					};
-				};
-			};
-		};
-
-		pwm@3280000 {
-			status = "okay";
-		};
-
-		pwm@32c0000 {
-			status = "okay";
-		};
-
-		pwm@32f0000 {
-			status = "okay";
-		};
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		pwms = <&pwm3 0 45334>;
-		#cooling-cells = <2>;
-	};
-
-	vdd_1v8_sys: regulator-vdd-1v8-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_SYS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-};

tegra234-p3740-0002+p3701-0008.dts

@@ -3,8 +3,8 @@
 
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/sound/rt5640.h>
 #include "tegra234-p3701-0008.dtsi"
-#include "tegra234-p3740-0002.dtsi"
 
 / {
 	model = "NVIDIA IGX Orin Development Kit";
@@ -20,6 +20,32 @@
 	};
 
 	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901300 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+
+				i2s@2901500 {
+					ports {
+						port@1 {
+							endpoint {
+								bitclock-master;
+								frame-master;
+							};
+						};
+					};
+				};
+			};
+		};
+
 		serial@3100000 {
 			compatible = "nvidia,tegra194-hsuart";
 			reset-names = "serial";
@@ -45,6 +71,40 @@
 		i2c@31c0000 {
 			status = "okay";
 
+			rt5640: audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+
+				sound-name-prefix = "CVB-RT";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s4_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+
+			/* carrier board ID EEPROM */
+			eeprom@55 {
+				compatible = "atmel,24c02";
+				reg = <0x55>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_ls>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
 		};
 
 		i2c@31e0000 {
@@ -60,6 +120,115 @@
 			status = "okay";
 		};
 
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-0 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb2-1 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb2-2 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb2-3 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb3-1 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb3-2 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					mode = "otg";
+					usb-role-switch;
+					status = "okay";
+				};
+
+				usb2-1 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb2-2 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <2>;
+					status = "okay";
+				};
+
+				usb3-1 {
+					nvidia,usb2-companion = <0>;
+					status = "okay";
+				};
+
+				usb3-2 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3550000 {
+			status = "okay";
+
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
+			phy-names = "usb2-0", "usb3-0";
+		};
+
+		usb@3610000 {
+			status = "okay";
+
+			phys =	<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
+				"usb3-0", "usb3-1", "usb3-2";
+		};
+
 		fuse@3810000 {
 			status = "okay";
 		};
@@ -70,6 +239,37 @@
 
 		i2c@c250000 {
 			status = "okay";
+
+			power-sensor@41 {
+				compatible = "ti,ina3221";
+				reg = <0x41>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					label = "CVB_ATX_12V";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "CVB_ATX_3V3";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					label = "CVB_ATX_5V";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+			};
+
+			power-sensor@44 {
+				compatible = "ti,ina219";
+				reg = <0x44>;
+				shunt-resistor = <2000>;
+			};
 		};
 
 		host1x@13e00000 {
@@ -102,6 +302,16 @@
 		};
 
 		pcie@141a0000 {
+			reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
+			       0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
+			       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
+			       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
+			       0x2e 0x20000000 0x0 0x10000000>; /* ECAM (256MB)               */
+
+			ranges = <0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000      /* downstream I/O (1MB) */
+				  0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000      /* non-prefetchable memory (128MB) */
+				  0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000>;    /* prefetchable memory (25088MB) */
+
 			status = "okay";
 			vddio-pex-ctl-supply = <&vdd_1v8_ls>;
 			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
@@ -235,4 +445,32 @@
 			  "CVB-RT DMIC1",		"CVB-RT MIC",
 			  "CVB-RT DMIC2",		"CVB-RT MIC";
 	};
+
+	vdd_3v3_dp: regulator-vdd-3v3-dp {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_DP";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_3v3_sys>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	vdd_3v3_sys: regulator-vdd-3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_SYS";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_3v3_wifi: regulator-vdd-3v3-wifi {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_WIFI";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+	};
 };

tegra234-p3740-0002.dtsi

@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/sound/rt5640.h>
-
-/ {
-	compatible = "nvidia,p3740-0002";
-
-	bus@0 {
-		aconnect@2900000 {
-			ahub@2900800 {
-				i2s@2901300 {
-					ports {
-						port@1 {
-							endpoint {
-								dai-format = "i2s";
-								remote-endpoint = <&rt5640_ep>;
-							};
-						};
-					};
-				};
-
-				i2s@2901500 {
-					ports {
-						port@1 {
-							endpoint {
-								bitclock-master;
-								frame-master;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		i2c@31c0000 {
-			rt5640: audio-codec@1c {
-				compatible = "realtek,rt5640";
-				reg = <0x1c>;
-
-				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
-				clock-names = "mclk";
-
-				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
-				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
-				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
-
-				/* Codec IRQ output */
-				interrupt-parent = <&gpio>;
-				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
-
-				#sound-dai-cells = <1>;
-				sound-name-prefix = "CVB-RT";
-
-				status = "okay";
-
-				port {
-					rt5640_ep: endpoint {
-						remote-endpoint = <&i2s4_dap>;
-						mclk-fs = <256>;
-					};
-				};
-			};
-
-			/* carrier board ID EEPROM */
-			eeprom@55 {
-				compatible = "atmel,24c02";
-				reg = <0x55>;
-
-				label = "system";
-				vcc-supply = <&vdd_1v8_ls>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
-			};
-		};
-
-		padctl@3520000 {
-			vclamp-usb-supply = <&vdd_1v8_ao>;
-			avdd-usb-supply = <&vdd_3v3_ao>;
-			status = "okay";
-
-			pads {
-				usb2 {
-					lanes {
-						usb2-0 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb2-1 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb2-2 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb2-3 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-					};
-				};
-
-				usb3 {
-					lanes {
-						usb3-0 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb3-1 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb3-2 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-					};
-				};
-			};
-
-			ports {
-				usb2-0 {
-					mode = "otg";
-					usb-role-switch;
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-1 {
-					mode = "host";
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-2 {
-					mode = "host";
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-3 {
-					mode = "host";
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb3-0 {
-					nvidia,usb2-companion = <2>;
-					status = "okay";
-				};
-
-				usb3-1 {
-					nvidia,usb2-companion = <0>;
-					status = "okay";
-				};
-
-				usb3-2 {
-					nvidia,usb2-companion = <1>;
-					status = "okay";
-				};
-			};
-		};
-
-		usb@3550000 {
-			status = "okay";
-
-			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
-			phy-names = "usb2-0", "usb3-0";
-		};
-
-		usb@3610000 {
-			status = "okay";
-
-			phys =	<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
-				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
-				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
-				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
-			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
-				"usb3-0", "usb3-1", "usb3-2";
-		};
-	};
-
-	vdd_3v3_dp: regulator-vdd-3v3-dp {
-				compatible = "regulator-fixed";
-				regulator-name = "VDD_3V3_DP";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				vin-supply = <&vdd_3v3_sys>;
-				gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>;
-				enable-active-high;
-				regulator-always-on;
-	};
-
-	vdd_3v3_sys: regulator-vdd-3v3-sys {
-				compatible = "regulator-fixed";
-				regulator-name = "VDD_3V3_SYS";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-	};
-
-	vdd_3v3_wifi: regulator-vdd-3v3-wifi {
-				compatible = "regulator-fixed";
-				regulator-name = "VDD_3V3_WIFI";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
-				regulator-boot-on;
-				enable-active-high;
-	};
-};

tegra234-p3767.dtsi

@@ -83,6 +83,35 @@
 			avdd-usb-supply = <&vdd_3v3_ao>;
 		};
 
+		i2c@c240000 {
+			status = "okay";
+
+			power-sensor@40 {
+				compatible = "ti,ina3221";
+				reg = <0x40>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					label = "VDD_IN";
+					shunt-resistor-micro-ohms = <5000>;
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "VDD_CPU_GPU_CV";
+					shunt-resistor-micro-ohms = <5000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					label = "VDD_SOC";
+					shunt-resistor-micro-ohms = <5000>;
+				};
+			};
+		};
+
 		rtc@c2a0000 {
 			status = "okay";
 		};

tegra234-p3768-0000+p3767-0000.dts

@@ -1,111 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/input/gpio-keys.h>
-
-#include "tegra234-p3767.dtsi"
-#include "tegra234-p3768-0000.dtsi"
+#include "tegra234-p3768-0000+p3767.dtsi"
 
 / {
 	compatible = "nvidia,p3768-0000+p3767-0000", "nvidia,p3767-0000", "nvidia,tegra234";
 	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit";
 
-	aliases {
-		serial1 = &uarta;
-		serial2 = &uarte;
-	};
-
 	bus@0 {
-		serial@3100000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		serial@3140000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		pwm@32a0000 {
-			assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
-			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
-			status = "okay";
-		};
-
 		hda@3510000 {
 			nvidia,model = "NVIDIA Jetson Orin NX HDA";
 		};
-
-		padctl@3520000 {
-			status = "okay";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		key-force-recovery {
-			label = "Force Recovery";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <BTN_1>;
-		};
-
-		key-power {
-			label = "Power";
-			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_POWER>;
-			wakeup-event-action = <EV_ACT_ASSERTED>;
-			wakeup-source;
-		};
-
-		key-suspend {
-			label = "Suspend";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_SLEEP>;
-		};
-	};
-
-	pwm-fan {
-		cooling-levels = <0 88 187 255>;
-	};
-
-	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_3V3_PCIE";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
-		enable-active-high;
 	};
 
 	sound {
 		label = "NVIDIA Jetson Orin NX APE";
 	};
-
-	thermal-zones {
-		tj-thermal {
-			cooling-maps {
-				map-active-0 {
-					cooling-device = <&fan 0 1>;
-					trip = <&tj_trip_active0>;
-				};
-
-				map-active-1 {
-					cooling-device = <&fan 1 2>;
-					trip = <&tj_trip_active1>;
-				};
-
-				map-active-2 {
-					cooling-device = <&fan 2 3>;
-					trip = <&tj_trip_active2>;
-				};
-			};
-		};
-	};
 };

tegra234-p3768-0000+p3767-0005.dts

@@ -1,11 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/input/gpio-keys.h>
-
-#include "tegra234-p3767.dtsi"
-#include "tegra234-p3768-0000.dtsi"
+#include "tegra234-p3768-0000+p3767.dtsi"
 
 / {
 	compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234";
@@ -17,32 +13,7 @@
 		};
 	};
 
-	pwm-fan {
-		cooling-levels = <0 88 187 255>;
-	};
-
 	sound {
 		label = "NVIDIA Jetson Orin Nano APE";
 	};
-
-	thermal-zones {
-		tj-thermal {
-			cooling-maps {
-				map-active-0 {
-					cooling-device = <&fan 0 1>;
-					trip = <&tj_trip_active0>;
-				};
-
-				map-active-1 {
-					cooling-device = <&fan 1 2>;
-					trip = <&tj_trip_active1>;
-				};
-
-				map-active-2 {
-					cooling-device = <&fan 2 3>;
-					trip = <&tj_trip_active2>;
-				};
-			};
-		};
-	};
 };

tegra234-p3768-0000+p3767.dtsi

@@ -1,10 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0
 
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+#include "tegra234-p3767.dtsi"
+
 / {
-	compatible = "nvidia,p3768-0000";
 
 	aliases {
 		serial0 = &tcu;
+		serial1 = &uarta;
+		serial2 = &uarte;
 	};
 
 	chosen {
@@ -12,6 +18,18 @@
 	};
 
 	bus@0 {
+		serial@3100000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		serial@3140000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
 		i2c@3160000 {
 			status = "okay";
 
@@ -168,6 +186,18 @@
 			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
 		};
 
+		pcie-ep@14160000 {/* C4 - End Point */
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+					<&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+			reset-gpios = <&gpio
+					TEGRA234_MAIN_GPIO(L, 1)
+					GPIO_ACTIVE_LOW>;
+			nvidia,refclk-select-gpios = <&gpio_aon
+							TEGRA234_AON_GPIO(AA, 4)
+							GPIO_ACTIVE_HIGH>;
+		};
+
 		/* C7 - M.2 Key-M */
 		pcie@141e0000 {
 			status = "okay";
@@ -197,19 +227,13 @@
 			wakeup-event-action = <EV_ACT_ASSERTED>;
 			wakeup-source;
 		};
-
-		key-suspend {
-			label = "Suspend";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_SLEEP>;
-		};
 	};
 
 	fan: pwm-fan {
 		compatible = "pwm-fan";
 		pwms = <&pwm3 0 45334>;
 		#cooling-cells = <2>;
+		cooling-levels = <0 88 187 255>;
 	};
 
 	vdd_1v8_sys: regulator-vdd-1v8-sys {
@@ -241,4 +265,25 @@
 	serial {
 		status = "okay";
 	};
+
+	thermal-zones {
+		tj-thermal {
+			cooling-maps {
+				map-active-0 {
+					cooling-device = <&fan 0 1>;
+					trip = <&tj_trip_active0>;
+				};
+
+				map-active-1 {
+					cooling-device = <&fan 1 2>;
+					trip = <&tj_trip_active1>;
+				};
+
+				map-active-2 {
+					cooling-device = <&fan 2 3>;
+					trip = <&tj_trip_active2>;
+				};
+			};
+		};
+	};
 };

tegra234.dtsi

@@ -2763,6 +2763,8 @@
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bpmp TEGRA234_CLK_UARTA>;
 			resets = <&bpmp TEGRA234_RESET_UARTA>;
+			dmas = <&gpcdma 8>, <&gpcdma 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -3252,23 +3254,8 @@
 			      <0x0 0x03650000 0x0 0x10000>;
 			reg-names = "hcd", "fpci", "bar2";
 
-			interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-				     <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 76 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 77 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 78 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 82 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-                   wake0, wake1, wake2 are for USB3.0 ports
-                   wake3, wake4, wake5, wake6 are for USB2.0 ports
-			*/
-			interrupt-names = "xhci", "mbox",
-				  "wake0", "wake1", "wake2", "wake3",
-				  "wake4", "wake5", "wake6";
-
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 
 			clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
 				 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
@@ -3828,7 +3815,7 @@
 			compatible = "nvidia,tegra234-sce-fabric";
 			reg = <0x0 0xb600000 0x0 0x40000>;
 			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			status = "okay";
+			status = "disabled";
 		};
 
 		rce-fabric@be00000 {
@@ -3913,7 +3900,7 @@
 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 			resets = <&bpmp TEGRA234_RESET_SPI2>;
 			reset-names = "spi";
-			dmas = <&gpcdma 19>, <&gpcdma 19>;
+			dmas = <&gpcdma 16>, <&gpcdma 16>;
 			dma-names = "rx", "tx";
 			dma-coherent;
 			status = "disabled";
@@ -4008,7 +3995,7 @@
 		};
 
 		dce-fabric@de00000 {
-			compatible = "nvidia,tegra234-sce-fabric";
+			compatible = "nvidia,tegra234-dce-fabric";
 			reg = <0x0 0xde00000 0x0 0x40000>;
 			interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
 			status = "okay";
@@ -4031,6 +4018,8 @@
 			#redistributor-regions = <1>;
 			#interrupt-cells = <3>;
 			interrupt-controller;
+
+			#address-cells = <0>;
 		};
 
 		smmu_iso: iommu@10000000 {
@@ -4855,6 +4844,37 @@
 			status = "disabled";
 		};
 
+		pcie-ep@14160000 {
+			compatible = "nvidia,tegra234-pcie-ep";
+			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
+			reg = <0x00 0x14160000 0x0 0x00020000     /* appl registers (128K)      */
+				0x00 0x36040000 0x0 0x00040000    /* iATU_DMA reg space (256K)  */
+				0x00 0x36080000 0x0 0x00040000    /* DBI space (256K)           */
+				0x21 0x40000000 0x3 0x00000000>;  /* Address Space (12G)        */
+			reg-names = "appl", "atu_dma", "dbi", "addr_space";
+			num-lanes = <4>;
+			clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
+			clock-names = "core";
+			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
+			       <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
+			reset-names = "apb", "core";
+
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
+			interrupt-names = "intr";
+			nvidia,bpmp = <&bpmp 4>;
+			nvidia,enable-ext-refclk;
+			nvidia,aspm-cmrt-us = <60>;
+			nvidia,aspm-pwr-on-t-us = <20>;
+			nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
+				      <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		pcie@14180000 {
 			compatible = "nvidia,tegra234-pcie";
 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;