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t23x: overlay: fsicom: add new hsp mailbox and stream id inst

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- add top2 hsp mailbox 5 and 4 for core 1 usage
- add FSI_CPU1 stream id for core 1 memory map
- newnode created for each SMMU inst

Bug 4243457

Change-Id: Id66c060d5daa1ca6458e3cbeee81dafc88904560
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2977860
Reviewed-by: Prashant Kumar Shaw <pshaw@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Tested-by: Lovie Wang <loview@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3168934
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Lovie Wang
2023-09-11 12:48:39 +08:00
committed by mobile promotions
parent 3073391461
commit 8fdbcfc7ff
1 changed files with 6 additions and 1 deletions
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7
include/kernel/dt-bindings/memory/tegra234-mc.h
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@@ -114,7 +114,7 @@
#define TEGRA234_SID_XUSB_HOST 0x0e
#define TEGRA234_SID_XUSB_DEV 0x0f
#define TEGRA234_SID_BPMP 0x10
#define TEGRA234_SID_FSI 0x11
#define TEGRA234_SID_NISO1_FSI_CPU0 0x11
#define TEGRA234_SID_PVA0_VM0 0x12
#define TEGRA234_SID_PVA0_VM1 0x13
#define TEGRA234_SID_PVA0_VM2 0x14
@@ -171,6 +171,11 @@
#define TEGRA234_SID_HOST1X_CTX6 0x3b
#define TEGRA234_SID_HOST1X_CTX7 0x3c
/*FSI Stream Id*/
#define TEGRA234_SID_NISO1_FSI_CPU1 0x4BU
#define TEGRA234_SID_NISO1_FSI_CPU2 0x4CU
#define TEGRA234_SID_NISO1_FSI_CPU3 0X4DU
/*
* memory client IDs
*/