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ASoC: tegra-alt: remove nvidia,mclk-rate property

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Currently MCLK rate depends on following DT properties,
 * 'mclk-fs' : This is a scaling factor depending on which MCLK rate
   is calculated at runtime [rate = scale * sample_rate]. Different
   codecs might expect different scale factors and hence DT property
   is useful here.
 * 'nvidia,mclk-rate' : This is used to provided fixed rate for MCLK.
   This overrides scale property, when specified.

Since the requirement is either to have fixed or dynamic rate for MCLK,
this can be managed with single property like below.
 * Use 'assigned-clocks' and 'assigned-clock-parents' to specify parent
   clock for MCLK.
 * Use preferred rate during initialization with 'assigned-clock-rates'
   DT binding. This can be the required fixed rate as well.
 * If dynamic scaling is required, then use 'mclk-fs' property.
   Otherwise system uses fixed rate.

Since rt565x audio codecs expect scaling factor of 256, all platforms
which use such codecs must be populated with "mclk-fs" property. This
is taken care in other patches in the series.

Bug 200542485
Bug 200516191
Bug 200503387

Change-Id: I1fc31626929bab9d4707d2a1b74c8f1749412ea4
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2173560
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sameer Pujar
2019-08-09 19:35:24 +05:30
parent c051f5fb23
commit a4107ebd5d
3 changed files with 1 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
sound/soc/tegra-alt/include/tegra_asoc_utils_alt.h
View File

@@ -62,8 +62,6 @@ struct tegra_asoc_audio_clock_info {
u32 set_pll_out_rate;
u32 set_aud_mclk_rate;
u32 mclk_scale;
/* fixed MCLK rate from DT */
u32 mclk_rate;
/* FIXME: below would be removed going ahead */
u32 clk_rates[MAX_NUM_RATES];

9
sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c
View File

@@ -793,16 +793,9 @@ static int tegra_machine_driver_probe(struct platform_device *pdev)
return ret;
memset(&machine->audio_clock, 0, sizeof(machine->audio_clock));
if (of_property_read_u32(np, "nvidia,mclk-rate",
&machine->audio_clock.mclk_rate) < 0)
dev_dbg(&pdev->dev, "Missing property nvidia,mclk-rate\n");
if (of_property_read_u32(np, "mclk-fs",
&machine->audio_clock.mclk_scale) < 0) {
/* TODO: fix clock in DT and remove usage of default scale */
machine->audio_clock.mclk_scale = 256;
&machine->audio_clock.mclk_scale) < 0)
dev_dbg(&pdev->dev, "Missing property mclk-fs\n");
}
ret = add_dai_links(pdev);
if (ret < 0)

5
sound/soc/tegra-alt/utils/tegra_asoc_utils_alt.c
View File

@@ -87,11 +87,6 @@ int tegra_alt_asoc_utils_set_rate(struct tegra_asoc_audio_clock_info *data,
pll_out = pll_out >> 1;
if (data->mclk_scale)
aud_mclk = srate * data->mclk_scale;
/*
* mclk_rate is the fixed clock from DT, this overrides mclk_scale.
* TODO: manage MCLK fixed or dynamic rate from a single DT property.
*/
aud_mclk = data->mclk_rate ? data->mclk_rate : aud_mclk;
if (data->set_pll_base_rate != new_pll_base) {
err = clk_set_rate(data->clk_pll_base, new_pll_base);