MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.
To satisfy the requirements of this rule, a "U" suffix is added to all
the integer literals used for initializing the arrays in mclk_gp106.c.
JIRA NVGPU-844
Change-Id: I0880519615f0e0302715b2e680a5cdf9accc03a0
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990495
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MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.
To satisfy the requirements of this rule, a "U" suffix is added to all
the integer literals used for initializing the _pginitseq_gv11b array.
JIRA NVGPU-844
Change-Id: I6200936455117a6205bd282365d4bc90ee1ccccc
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990492
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MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.
To satisfy the requirements of this rule, a "U" suffix is added to all
the integer literals used for initializing the _pginitseq_gp10b array.
JIRA NVGPU-844
Change-Id: I573dd94fb0fc354d297fa94ab1d9a74d5a2b1809
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990482
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MISRA Rule 7.2 Definition: A "u" or "U" suffix shall be applied to all
integer constants that are represented in an unsigned type.
To satisfy the requirements of this rule, a "U" suffix is added to all
the integer literals used for initializing the _pginitseq_gm20b array.
JIRA NVGPU-844
Change-Id: I04f3b4db1601c1d5c21d7c48a8a513db4e12a542
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990479
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Currently all the global contex buffers are mapped into each graphics
context. Move all the mapping/unmapping support to gr/ctx unit since
all the mappings are owned by context itself
Add nvgpu_gr_ctx_map_global_ctx_buffers() that maps all the global
context buffers into given gr_ctx
Add nvgpu_gr_ctx_get_global_ctx_va() that returns VA of the mapping
for requested index
Remove g->ops.gr.map_global_ctx_buffers() since it is no longer
required. Also remove below APIs
gr_gk20a_map_global_ctx_buffers()
gr_gk20a_unmap_global_ctx_buffers()
gr_tu104_map_global_ctx_buffers()
Remove global_ctx_buffer_size from nvgpu_gr_ctx since it is no
longer used
Jira NVGPU-1527
Change-Id: Ic185c03757706171db0f5a925e13a118ebbdeb48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987739
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Add new unit common/gr/ctx.c to manage GR context
This unit provides interfaces to allocate/free/map/unmap GR context,
patch context, pm context, ctxsw {preempt/spill/betacb/pagepool/rtvcb}
buffers.
It also provides APIs to set size of above buffers
Add new header file include/nvgpu/gr/ctx.h to declare all the interfaces.
Move nvgpu_gr_ctx, patch_desc, pm_ctx_desc, zcull_ctx_desc structures
to this unit
Add new structure nvgpu_gr_ctx_desc to hold context description
parameters. For now we add sizes of all the buffers here.
Add this structure to gr_gk20a for global reference
Remove gr_gp10b_alloc_buffer() since it is no longer used
Rename g->ops.gr.alloc_gfxp_rtv_cb() to g->ops.gr.init_gfxp_rtv_cb()
since this HAL now only sets the size of rtvcb ctxsw buffer
Remove gr->ctx_vars.buffer_size and gr->ctx_vars.buffer_total_size
since they were redundant. We already have gr->ctx_vars.golden_image_size
to denote golden image size
Jira NVGPU-1527
Change-Id: I8847b347f80235209dd5e28d979e79984ab85408
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987702
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The nvgpu managed syncpoint is not needed for anything if a channel uses
usermode submits; in that case the channel would allocate an
user-managed syncpoint and use that. Create the channel sync in
nvgpu_channel_setup_bind() only if usermode submit is not enabled.
Bug 200466905
Change-Id: I976f4b4fd0c3131cb310c72b286329fb16f1f29a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990270
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Remove a BUG() call in nvgpu_vm_find_mapping(). This bug was
present to ensure that we evaluate whether this function is
necessary or useful before deleting it.
nvgpu_vm_find_mapping() facilitates map caching in the VM
layer. This feature is not necessary for unit testing at the
moment. As such delete the BUG() and allow this code to run.
JIRA NVGPU-1352
Change-Id: If7cdf3c0dfe0e94e32061d7775d2eef7318cf63f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987807
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Local golden image is copy of global GR context buffer hence move its
ownership to global context unit
Add new structure nvgpu_gr_global_ctx_local_golden_image to hold all meta
data for local golden image and move it to struct gr_gk20a
Expose and use new APIs to initialize/deinitialize and load local golden image
Jira NVGPU-1625
Change-Id: Ieb68e52c205ca0ecd27f8bf4bb31922a01e7ae54
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1984952
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Turing board (PG189) variants (A00, A01, A02, A03) need
different dealys for valid power good (PG) signal. To support
all board variants change the delay to minimum required value
of 250ms.
Bug 200452556
JIRA NVGPU-1100
Change-Id: Iba2a6b17dec7552197cb0b7873132d83e9e09aea
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987659
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The channel timeout ends up in a strange state during timeout handling
for a brief moment; it can become stopped and started again, and the
timeout lock is released in the middle. Add a more explicit rewind
function to reset the timeout to start if it's active. The active check
allows to use this from gk20a_channel_timeout_restart_all_channels(), so
that's also modified.
Also replace the return statements with more readable control flow in
gk20a_channel_timeout_handler().
Change-Id: Ia7d67242dfc149ace1f4f841a837e90b6c985308
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989327
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Add clk arbiter support for tu104
setup clk_arb for supporting functions in hal_tu04
TU104 supports GPCCLK and not GPC2CLK
Remove multiplication and division by 2 to convert gpcclk to gpc2clk
Provide support for following features
*Domains: Currently GPCCLK is supported
*clk Range: From P0 min to P0 max
*Freq Points: Gives the VF curve from PMU
*Default: Default value(P0 Max)
*Current Pstate: P0 is supported
All request for change is freq is validated against P0 value
Out of bound values are trimmed to match the Pstate limits
Multiple requests are supported and max of that will be set
Requests are sent to PMU via change sequencer
Bug 200454682
JIRA NVGPU-1653
Change-Id: I36735fa50c7963830ebc569a2ea2a2d7aafcf2ab
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1982078
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for drivers/gpu/nvgpu/common.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I53fe750f1b41816a183c595e5beb7bd263c27725
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971221
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MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for gv11b.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: Idda45b86c95b535154b4d4632fdc23a18950e380
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971168
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MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for gp10b.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I9291a520fb4a28571b3d7d7b102e43227c1df07e
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971167
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MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for gm20b.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I0c8b3f04c943a1cea23ce3f678ebb915e8a5a5da
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971166
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MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for gk20a.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I965eae017350156c6692fd585292b7a54e4190d8
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971010
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MISRA rule 10.1 prohibits using signed values with bitwise operators.
Make fifo invalid ID macros compliant with this MISRA rule.
Also use these macros in source code instead of hardcoded numbers to
make the code more readable.
JIRA NVGPU-1006
Change-Id: I2f336d1decbc53b08f93587f2e00ea2cce47f72b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983700
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Current code creats golden image using dedicated gr_ctx called
GOLDEN_CTX. But on RM server it's no easy to create a GOLDEN_CTX since
virtual addresses are managed by guest OSes. There's no special reason
why we have to use a separate gr_ctx for golden image. This patch moves
it to use current channel gr_ctx. And the function will be re-useable
by RM server.
Jira GVSCI-191
Change-Id: I9920703e61f7e1d8b3ad6612811e47a3815d0c0f
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983702
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Split out native-specific engine info collection out of
nvgpu_init_runlist() so that it only contains common code. Call this
common function from vgpu code that ends up being identical.
Jira NVGPU-1309
Change-Id: I9e83669c84eb6b145fcadb4fa6e06413b34e1c03
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978060
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Extract non-chip-specific code that manages the runlists (init, update,
reschedule etc.) to a new file in the common directory. Move the
declarations to a new matching runlist.h header.
Jira NVGPU-1309
Change-Id: I3c7e0032899516487037f47ddc9a7e7aa4b0b33a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978058
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OS specific implementation of fecs trace bind_channel function
needs to handle special case for vserver to retrieve vmid from
channel id. Native code should be independent of server code.
Modify struct fecs_trace member function bind_channel to pass
vmid parameter enabling retrieving and passing vmid from server
code.
Jira GVSCI-44
Change-Id: I96223376f2068e2cbf60a9c9b35ff564a65e5dc3
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970693
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Add common/falcon/falcon_priv.h file that will contain declarations
private to Falcon unit. Clean up the falcon header files inclusion.
Rules followed:
1. Remove unneeded header file includes.
2. Falcon unit source files will only include falcon_priv.h.
3. Base architecture Falcon source (falcon_gk20a.c) will only
include hw_falcon_*.h file.
4. Derived architecture source will include hw headers if needed.
5. Other units should not include hw headers for Falcon.
6. HAL source will include the Falcon unit header if needed.
JIRA NVGPU-1459
Change-Id: Ia9f03f7b577fe10b8c0f417e6302fa7ebd4131cc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961634
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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pmu.g & sec2.g were set in nvgpu_falcon_sw_init. They are now set
in nvgpu_early_init_pmu_sw & nvgpu_init_sec2_setup_sw. Pass gk20a
& pmu struct to nvgpu_init_pmu_fw_support like sec2.
pmu_fw_support & sec2_setup_sw are separated from respective init
sequence and now are called earlier since we need ->g member earlier
and most of the setup is sw only.
nvgpu_init_pmu_fw_ver_ops is now being exported.
JIRA NVGPU-1594
Change-Id: I6c71c6730ce06dad190159269e2cc60301f0237b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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