gk20a_pm_runtime_suspend can fail and invoke gk20a_pm_finalize_poweron
that can cause double mapping of the usermode mmap region via
io_remap_pfn_range(). Avoid this by using a boolean variable to track
whether the region is already mapped.
Bug 2707416
Change-Id: I4d8cbe427400a5b986348a19af145367cc08ffc6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2229312
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Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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1. Move common.class HAL outside gk20a.h for documentation purpose.
2. Add the new HAL header file to yaml.
3. Add doxygen comments to all the FUSA public defines and HALS.
4. Use @cond...@endcond to skip documentation for NON-FUSA HALs.
JIRA NVGPU-2487
Change-Id: Ib80e8e6e56073fe26a1810fd082c8ec6a115e22d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2232234
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The devinit executes in parallel with PCIE link training
to reduce exit latency. Therefore, all PCIE settings that
normally occur during devinit after the PCIE link is up are
deferred until nvgpu has resumed control.
Bug 2661545
Change-Id: Ifdd4f645b2e1791d93567cc34d6ab0691a25d101
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210625
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Move graphics related defs and functions under CONFIG_NVGPU_GRAPHICS
switch.
Move classes not supported in GV11B under CONFIG_NVGPU_NON_FUSA
switch.
Add missing valid class numbers to gpu_class.is_valid HAL.
Also remove un-used class defs from class.h header.
Lot of qnx safety tests are still using graphics 3d class.
Until those tests got fixed, allowing 3d graphics class
as valid class for safety build.
JIRA NVGPU-4301
Change-Id: Ifd2a13bee3210821799c2bca10e7245eb3c79121
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224658
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Whitelist 2 MISRA Rule 17.2 violations in MM that were approved as
deviations in TID-278. These two violations are for recursive functions
that handle page table descriptors in the GMMU page table. Both cases
are tightly controlled recursion by limiting the recursion depth to the
number of possible page table levels in the hardware. For current
hardware that is a maximum recursion depth of 5 which is easily an
acceptable depth and should cause no stack issues.
JIRA NVGPU-3489
JIRA NVGPU-3492
JIRA TID-278
Change-Id: I5b801ff77f66bb8698f1d6adcd41ebbad3f86f92
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2230077
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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This function gets the GPU chip architecture, implementation and
revision information by reading the MC boot register, hence it
is more suited to be located in HAL files.
test_check_gpu_state is now being run after test_hal_init as the
gops.mc needs to be initialized for test_check_gpu_state subtest.
JIRA NVGPU-2524
Change-Id: I85355af11d3505a9eb4f10a3fe4e6d9b56285047
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226018
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226017
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Currently nvgpu queue APIs are in nvgpu_rmos folder
but they can be moved to Posix layer. This change adds
the queue APIs to posix layer and the same will get deleted
from the nvgpu_rmos folder.
JIRA NVGPU-2679
Change-Id: I1d33c9f8eeae5fcb8e628b755e788d0be6310e47
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2229355
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The two MM functions nvgpu_set_pd_level() and nvgpu_vm_do_free_entries()
are simple recursive functions for processing page descriptors (PDs) by
traversing the levels in the PDs. MISRA Rule 17.2 prohibits functions
calling themselves because "unless recursion is tightly controlled, it
is not possible to determine before execution what the worst-case stack
usage could be." So, this change limits the recursion depth of each of
these functions to the maximum number of page table levels by checking
the level against the MM HAL max_page_table_levels().
This also required configuring this HAL in various unit tests as they
were no previously using this HAL.
JIRA NVGPU-3489
Change-Id: Iadee3fa5ba9f45cd643ac6c202e9296d75d51880
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224450
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nvgpu_falcon_setup_bootstrap_config functionality can be kept static.
nvgpu_falcon_bl_bootstrap and nvgpu_falcon_bl_info are removed as it
is replaced by nvgpu_falcon_hs_ucode_load_bootstrap.
Update the test case accordingly, SWUTS and doxygen comments. Other
nits addressed about doxygen documentation.
JIRA NVGPU-2412
Change-Id: Idaa670ce6d6d6b735b4a2af34e1f1a229ff2a3e9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220089
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Moved mmu replayable fault related code under CONFIG_NVGPU_REPLAYABLE_FAULT
switch, so that it will be compiled out for safety build.
Following hals and their related code also moved under
CONFIG_NVGPU_REPLAYABLE_FAULT switch:
void (*handle_replayable_fault)(struct gk20a *g);
int (*mmu_invalidate_replay)(struct gk20a *g, u32 invalidate_replay_val);
JIRA NVGPU-4302
Change-Id: I191ee0c181b276a04bc1531488862380af81a5c9
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2227176
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Writing same value to railgate_enable_store should be treated as nop
and made successfully. Doing so is not only an optimization for the
operation but also convention that users expect for "settings". This
change is primary for fixing a peculiar situation in the driver:
root@localhost:/sys/devices/17000000.gp10b# cat railgate_enable
0
root@localhost:/sys/devices/17000000.gp10b# echo 0 > railgate_enable
bash: echo: write error: Invalid argument
Attempt to disable railgating on a platform where railgating isn't
supported shouldn't be treated as 'invalid'. It's disabled after all.
Bug 200562094
Change-Id: I3c04934bdbaf337c33d7de9cac6d53c96b4dacae
Signed-off-by: Leon Yu <leoyu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2225476
(cherry picked from commit 10b3b5b1d5)
Reviewed-on: https://git-master.nvidia.com/r/2226185
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Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
This patch updates NVGPU_DEFAULT_DBG_MASK to be u32.
Jira NVGPU-4075
Change-Id: I3af250d27bb629a6c531dd6843bc6dbcb9a1cca5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224778
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Add doxygen comments to all the FUSA public APIs and HALS
The APIs identified as NON-FUSA are -
a. nvgpu_fbp_get_num_fbps()
b. nvgpu_fbp_get_rop_l2_en_mask()
Add @cond ... @endcond to skip NON FUSA functions from
design document.
The FBP HAL fbp.fbp_init_support() is redundant and will be replaced
by calls to nvgpu_fbp_init_support() directly.
JIRA NVGPU-4140
Change-Id: I08ec79dfcab7b898b40491997963466938e5e4cd
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2221967
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