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7732 Commits

Author SHA1 Message Date
Philip Elcan
882cf68562 gpu: nvgpu: unit: add fault injection for timer init 
Add fault injection handling for the nvgpu_timeout_init() API.

JIRA NVGPU-2219

Change-Id: I0c3ba06d3726e87d1097e695698124ffabc68ab9
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255353
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
24210bdbc9 gpu: nvgpu: unit: add tests for gp10b pbdma HAL 
Add unit tests for the following HALs:
- gp10b_pbdma_get_signature
- gp10b_pbdma_get_fc_runlist_timeslice
- gp10b_pbdma_get_config_auth_level_privileged

Jira NVGPU-3694

Change-Id: I672acc76490db358951b31c1231fb8542852dfee
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253635
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
7b1f5a327f gpu: nvgpu: unit: add tests for gm20b pbdma HAL 
Add tests for the following HALs:
- gm20b_pbdma_acquire_val
- gm20b_pbdma_handle_intr
- gm20b_pbdma_read_data
- gm20b_pbdma_reset_header
- gm20b_pbdma_device_fatal_0_intr_descs
- gm20b_pbdma_restartable_0_intr_descs
- gm20b_pbdma_format_gpfifo_entry
- gm20b_pbdma_get_gp_base
- gm20b_pbdma_get_gp_base_hi
- gm20b_pbdma_get_fc_subdevice
- gm20b_pbdma_get_userd_aperture_mask
- gm20b_pbdma_get_userd_addr
- gm20b_pbdma_get_userd_hi_addr

Jira NVGPU-3694

Change-Id: I3d97f2e70d6c364d673a4f231ff1a3fad349c14e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253634
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
ecab3ddbce gpu: nvgpu: unit: add tests for gv11b pbdma HAL 
Add tests for the following HALs:
- gv11b_pbdma_setup_hw
- gv11b_pbdma_intr_enable
- gv11b_pbdma_handle_intr_0
- gv11b_pbdma_handle_intr_1
- gv11b_pbdma_channel_fatal_0_intr_descs
- gv11b_pbdma_get_fc_pb_header
- gv11b_pbdma_get_fc_target
- gv11b_pbdma_set_channel_info_veid
- gv11b_pbdma_config_userd_writeback_enable

Jira NVGPU-3694

Change-Id: Ieea746e07cae4a3c1b5289674d93654edf7de941
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253633
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
9191461a6a gpu: nvgpu: rename set_channel_info_veid parameter 
gops_pbdma.set_channel_info_veid takes a subctx_id (i.e. veid),
not a channel_id.
Renamed parameter to subctx_id.

Jira NVGPU-3694

Change-Id: If64d06b1041fd42b6a0fcaf6bbb30e156235fa54
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253631
Reviewed-by: Automatic_Commit_Validation_User
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
64b0794ab8 gpu: nvgpu: fix precision for acquire_val 
In gm20b_pbdma_acquire_val, use a single multiply operation to
convert to ns and apply 80% factor, for improved precision.

Jira NVGPU-3694

Change-Id: I5be3c5455ba53eccfadbb8c8678f28d0cf36e867
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253630
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Lakshmanan M
a52ee77837 gpu: nvgpu: Add SM diversity gpu characteristic flag 
To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute
on different hardware resources.
This feature requires a change in software to make it possible
to modify the virtual SM id to TPC mapping across mission and
redundant contexts.

This CL adds only SM diversity flags which are exposed to
its clients through ioctl/devctl interfaces.
Actual virtual SM id to TPC mapping implementation
will be part of upcoming patch sets.

Added NvGpu CFLAGS to identify the safety build
"CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY"

JIRA NVGPU-4133

Change-Id: I5a18256780e6726e399e39c1c8d155d2ef07d7bd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250461
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 2020-12-15 14:10:29 -06:00
vinodg
b0862a168c gpu: nvgpu: compile out nonsecure code in gr.falcon 
For Safety code NVGPU_SEC_SECUREGPCCS bit will be set by default.

Compile out the code called for nonsecure gpccs under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT checking.
This includes:
Hals for load_ctxsw_ucode_header and  load_ctxsw_ucode_boot.
nvgpu_gr_falcon_load_gpccs_with_bootloader and static functions
called from this function.

Jira NVGPU-4453

Change-Id: I56e6d585a26fcf593059a5157de07b77e3b9f00d
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255490
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
63de725df9 gpu: nvgpu: unit: add tests for usermode gv11b HAL 
Add unit tests for the following usermode HALs:
- gv11b_usermode_base
- gv11b_usermode_bus_base
- gv11b_usermode_doorbell_token
- gv11b_usermode_ring_doorbell

Jira NVGPU-4389

Change-Id: I7fdad23b0482c1437d309e8eeab239aad1fb5c99
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254548
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
4e9c117848 gpu: nvgpu: unit: add tests for userd gk20a HAL 
Add unit test for the following HAL:
- gk20a_userd_entry_size

Jira NVGPU-4389

Change-Id: I8da4fcc3c3e3aadf69e7cf1ae26fba6f2701a557
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
2846c26c1e gpu: nvgpu: unit: enable engine tests on target 
Add the following tests to target makefile:
- engine
- engine/gm20b
- engine/gp10b
- engine/gv100
- engine/gv11b

Fix build issues for unit tests on QNX safety.
Update export files to fix link issues.
Update list of required tests in JSON file.

Jira NVGPU-3695

Change-Id: I373c6c8575ed4cbf6c5597502f2ca6ec2f078ca4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253506
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
e211535142 gpu: nvgpu: unit: add tests for gm20b engine HAL 
Add unit test for the following HAL:
- gm20b_read_engine_status_info

Jira NVGPU-3695

Change-Id: I8752e3ac83fb647704ad5547d650574d2b5a95c7
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253505
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
94056dedf5 gpu: nvgpu: unit: add tests for gp10b engine HAL 
Add unit test for the following HAL:
- gp10b_engine_init_ce_info

Jira NVGPU-3695

Change-Id: Id63818b9b2478408f84489cf70c496f4a5645a47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253504
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
2c83d780b0 gpu: nvgpu: unit: add tests for gv11b engine HAL 
Add unit test for the following HAL:
- gv11b_is_fault_engine_subid_gpc

Jira NVGPU-3695

Change-Id: I968fe6d189f311c9b9627f6b59998ef3cbd0b3f5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253503
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
71b7e85b50 gpu: nvgpu: unit: add tests for gv100 engine HAL 
Add unit tests for the following HALs:
- gv100_read_engine_status_info
- gv100_dump_engine_status

Jira NVGPU-3695

Change-Id: I66ba608802431d0f7ac2471d9ce726817f32c73e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253502
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
d58e14e4d0 gpu: nvgpu: unit: add negative tests for common.gr.fs_state 
Add negative tests that inject memory allocation failures and verify
error handling path in common.gr.fs_state unit.

Jira NVGPU-4373

Change-Id: If8774a60ffc951bd2c9978196268c20e10188026
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247846
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
04adc71304 gpu: nvgpu: add assert on number of SMs 
HAL gops.gr.config.init_sm_id_table() initializes SM count in struct
nvgpu_gr_config. It is almost impossible that SM count is detected as
zero.

Hence remove the error check and add an assert instead.

This also helps with code coverage tests since it is difficult to
simulate error condition of having zero SMs detected.

Also, HAL gops.gr.config.init_sm_id_table() should always be defined
for each platform. Hence remove unnecessary check.

Jira NVGPU-4373

Change-Id: Ibd9b301b28d5bd2952367346a8f12fabcee2abd9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247845
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
4554b4654a gpu: nvgpu: make gops.gr.init.fs_state return void 
This HAL function does not return any real error at all.
So just change the return type to void.

In case of vGPU, this function only calls another HAL
gops.gr.config.init_sm_id_table(). So unset gops.gr.init.fs_state()
for vGPU, and call gops.gr.config.init_sm_id_table() directly.

Jira NVGPU-4373

Change-Id: I06a80520e9be50a0703608a79187c553b33aa582
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247844
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Deepak Nibade
a5cc0d9976 gpu: nvgpu: compile out user provided tpc_fs_mask in safety 
User can update tpc_fs_mask either through sysfs or from Device tree.
Both the use cases are not supported in safety.

Hence compile out corresponding support with CONFIG_NVGPU_NON_FUSA
compile time config

Jira NVGPU-4373

Change-Id: I1269509409e2c980bd41364cf460e818d8c13267
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
8a26aa5916 gpu: nvgpu: rearrange code for gr.falcon unit 
gr_falcon_sec2_or_ls_pmu_bootstrap function is valid only
with CONFIG_NVGPU_DGPU or CONFIG_NVGPU_LS_PMU setting.

Rearrange code in gr_falcon_recovery_bootstrap and
gr_falcon_coldboot_bootstrap to avoid extra error checking.

Jira NVGPU-4453

Change-Id: I1fcba852610214a2647f324be1f182db57835cff
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254704
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
a8866825d2 gpu: nvgpu: fix the doxygen comments due to ECC and MC refactoring changes 
nvgpu_mc_log_pending_intrs is debugging related function hence compile
out that and related functionality under CONFIG_NVGPU_NON_FUSA.
nvgpu_mc_intr_enable is applicable for older chips hence compile out
under CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA.
Update BUS, CE, ECC, FIFO, MC, PRIV_RING, GR, LTC, FB, PMU units'
doxygen comments based on recent ECC and MC refactoring.

JIRA NVGPU-4439

Change-Id: I337318683d6311b9c2b5748f2fb07dff29a6584f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252853
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 2020-12-15 14:10:29 -06:00
Scott Long
bf49a248be gpu: nvgpu: MISRA 4.4 fix to regops 
MIRA Advisory Rule 4.4 states that sections of code
should not be commented out.

This change removes the following unused regop type from
our regops support:

  /*#define NVGPU_DBG_REG_OP_TYPE_FB  (0x00000020)*/

Jira NVGPU-3178

Change-Id: I2a65c50aabf6b51072dd6fc1e344d543e3359525
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245762
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
dcb19f578a gpu: nvgpu: unit: ltc: increase line/branch coverage 
This increases the line and branch coverage for nvgpu.common.ltc unit
test.

Add testing for nvgpu.common.hal.ltc for gv11b.

Also, add Targets tag for SWUTS/traceability.

JIRA NVGPU-2219

Change-Id: Ic0e3772b6348ba7ce43fd869567467bc13b8943c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248093
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 2020-12-15 14:10:29 -06:00
Philip Elcan
b8c25a5a55 gpu: nvgpu: unit: init: add quiesce testing 
Add testing of quiesce functionality to init unit test.

JIRA NVGPU-3981

Change-Id: Idc64179bc8d532bea385e705d96fb4b376d15cd9
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247154
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 2020-12-15 14:10:29 -06:00
Debarshi Dutta
4cc1fa1a0b gpu: nvgpu: construct initial utf for sync unit. 
This patch constructs the initial setup for sync unit.
There are three simple tests currently. The first test inits the
environment necessary such as regspace init, hal init. The second
step simply fails the creation of the sync and the last test is meant
as a deinit step.

JIRA NVGPU-913

Change-Id: I1db72d9833c3c4bc3c3903a7d81cce06e9983509
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248493
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 2020-12-15 14:10:29 -06:00
vinodg
bb942331e8 gpu: nvgpu: compile out unused code in gr.falcon unit 
NVGPU_GR_FALCON_METHOD_HALT_PIPELINE section is used only
with CONFIG_NVGPU_ENGINE_RESET setting.

Jira NVGPU-4453

Change-Id: Ia33e370486ebcd2052b7ec9d530503f93e798cbf
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253865
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Tejal Kudav
c8c8e59a46 gpu: nvgpu: unit: add priv_ring unit tests 
Add unit tests for common.priv_ring unit.

JIRA NVGPU-934

Change-Id: Ic825f571a3032cf9a194773df09a255bcba1bf79
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248567
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 2020-12-15 14:10:29 -06:00
Debarshi Dutta
037c5761e7 gpu: nvgpu: handle syncpoint buffer alloc failure 
Add check for syncpoint buffer allocation failure in the function
nvgpu_channel_sync_syncpt_create. Return NULL if the allocation fails.

Also, put a reference to the syncpoint allocated if the above
buffer allocation fails.

Change-Id: I56ab03df3b37a3c8148ee17ec6a7829686e44de6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247637
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
8592b0591c gpu: nvgpu: Add fail scenarios in ACR unit tests 
- Add more fail scenarios in ACR unit tests to cover
  branches
- Return "err" value when "get_lsf_ucode_details" ops
  for fecs fails.

JIRA NVGPU-4319

Change-Id: Ic9ba0afb26b23f6e0c0ebd76feae5b1ba3098b93
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252801
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
1ab3f73230 gpu: nvgpu: unit: improve coverage for gm20b channel HAL 
Add unit test for the following HAL:
- gm20b_channel_force_ctx_reload

Jira NVGPU-4384

Change-Id: Icb802348349a790371e6d84efe449c309105c5e8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250014
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 2020-12-15 14:10:29 -06:00
vinodg
770090630c gpu: nvgpu: add error injection test in common.gr.setup 
Add error injection test for gr.setup.alloc_obj_ctx function.
Add doxygen for test_gr_setup_alloc_obj_ctx_error_injections call.

Clear ch->subctx variable after freeing the memory.

Jira NVGPU-3968

Change-Id: I17541ad86e3efb540bd3c8a9d008767c588377f3
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250094
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Prateek sethi
eb7e295534 nvgpu_rmos: Add fault injection instances for QNX devctl APIs 
Jira NVGPU-2667

Change-Id: I950d69906e626bfc62e9f112f1469d772b70d14e
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252568
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Rajesh Devaraj
0d19c7a546 gpu: nvgpu: update fault injection 
This patch updates fault injection for nvgpu_thread_create_priority().

JIRA NVGPU-2694

Change-Id: I254649cfd6b7a76afe89b227991fbe9e03c422ea
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252737
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
ajesh
c46a68c231 gpu: nvgpu: add rwsem unit test 
Add unit tests for rwsem unit.

Jira NVGPU-2698

Change-Id: Id8c6f336b3cc2c458f42a8c21a9bace3a7711e05
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208425
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
df5924cf57 gpu: nvgpu: unit: add common.class unit tests 
Add unit tests for API exposed by common.class unit

Jira NVGPU-4373

Change-Id: Id72df78c5a3c8a85ac71dd3b559d19c296c87b5f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2246808
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
84a24c9593 gpu: nvgpu: Remove TPC powergate from safety build 
- Remove non-safe TPC powergate feature from the safety
  build by introducing a new flag:
  CONFIG_NVGPU_TPC_POWERGATE

- Move nvgpu_init_power_gate_gr() under same compile time flag.
  and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c

- Also, remove the negative test scenario and
  usage of tpc_powergate from unit tests

JIRA NVGPU-4149

Change-Id: If489482401e94de499e472b16b1bc091b00992e6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242323
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 2020-12-15 14:10:29 -06:00
Tejal Kudav
836abc253d gpu: nvgpu: unit: common.fbp tests 
Add unit tests for all the APIs exposed by common.fbp unit.

JIRA NVGPU-4393

Change-Id: I4aef64359919418ee5446925331fa9ef9eb5d5f0
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244373
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
44a87d320e gpu: nvgpu: split lists for hwpm control regs 
FECS ucode introduces separate register lists for control registers, so
that they can be restored separately from PM state.
Added support for:
- LIST_compressed_nv_perf_sys_control_ctx_regs
- LIST_compressed_nv_perf_pma_control_ctx_regs
- LIST_compressed_nv_perf_fbp_control_ctx_regs
- LIST_compressed_nv_perf_gpc_control_ctx_regs

Bug 200507276

Change-Id: Ifce398bcb298822f3a46cf372ef9610a46a8df0c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193528
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 2020-12-15 14:10:29 -06:00
Prateek sethi
31ac3a1f6e gpu: nvgpu: doxygen: add NVCPU_IS_AARCH64 flag 
The doxygen config file did not have NVCPU_IS_AARCH64 flag which is
required by os_utils barrier subunit.
Add flag to enable source enclosed with the flag.

JIRA NVGPU-4410

Change-Id: Ic3be19d636db775a489a9cbdb0c82da8a069ffcd
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2249533
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
0ba37ecf4d gpu: nvgpu: unit: enable pbdma tests on target 
Add missing pbdma, runlist and channel files to tmake
makefile and fix compilation issues.
Update exports to fix link issues.
Update required tests in JSON file.

Jira NVGPU-3490

Change-Id: Ib5f7dd15ebbd81c5f5f304f8c22ea8299c469a93
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247248
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 2020-12-15 14:10:29 -06:00
Rajesh Devaraj
b5acb44f2f gpu: nvgpu: add flag to enable the usage of 3lss error injection support 
This patch introduces the flag CONFIG_NVGPU_3LSS_ERR_INJECTION to enable
the usage of 3lss error injection support in non-safety build (DEV PCT).

JIRA ESS-4206

Change-Id: I9081d6073e66d3657b4cf8b5ee691f031555739a
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247708
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
2a81cea0e0 gpu: nvgpu: unit: setup preemption error test 
Add Setup set_preemption_mode error tests with
test_gr_setup_preemption_mode_errors function.

Update Doxygen for test_gr_setup_preemption_mode_errors.

Jira NVGPU-3698

Change-Id: I21e84c9f7f2618656cb6b79b97802e182aed4516
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247378
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 2020-12-15 14:10:29 -06:00
vinodg
b5ab4342fd gpu: nvgpu: update gr code for safety build 
Move code used only with graphics under
CONFIG_NVGPU_GRAPHICS check.

gm20b_gr_init_load_sw_bundle_init hal get called
without CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION check.

Remove dead code in
nvgpu_gr_ctx_check_valid_preemption_mode function.

Jira NVGPU-3968

Change-Id: I399126123006ae44dba29b3c08378d11fe82e543
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247346
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 2020-12-15 14:10:29 -06:00
vinodg
c50de751dd gpu: nvgpu: compile out unused code in gr.falcon hal 
gm20b_gr_falcon_submit_fecs_sideband_method_op is used only with
graphics support. Add CONFIG_NVGPU_GRAPHICS checking for that function.

Jira NVGPU-3968

Change-Id: I858f9b27ec668ebbfa02abf89dd58d7496f5678d
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
e647a146e1 gpu: nvgpu: store engine_id in CE engine_info 
engine_id was not updated in engine_info structure for CE.
Add engine_id update in gp10b_engine_init_ce_info.

Jira NVGPU-3490

Change-Id: I260767a2baf1d04702f7c2b622069fdaa33d49cb
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242700
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
945e9ebee2 gpu: nvgpu: checks in nvgpu_engine_init_info 
Return error in nvgpu_engine_init_info if g->ops.top.get_device_info
is NULL. In particular, do not attempt to init CE info.

Jira NVGPU-3693

Change-Id: I521cb43233a48b6e765ffd0b1feee81a30dbd739
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242699
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 2020-12-15 14:10:29 -06:00
Philip Elcan
95c3e56961 gpu: nvgpu: unit: propagate fault injection to threads 
Change approach to how the fault injection state is stored to facilitate
propagating fault injection state to child-threads. Rather than each
unit maintaining a thread-local object, there is a thread-local
container stored in the posix-fault-injection itself. This container is
initialized for each test module so that is independent of other other
test modules (for parallel test module execution). When child threads
are created with nvgpu_create_thread(), the fault injection container is
configured for the child.

JIRA NVGPU-3981

Change-Id: I9b580dc7f1621a7770eef8eba796f3918f2738bf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2238474
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 2020-12-15 14:10:29 -06:00
Tejal Kudav
aec0296c17 gpu: nvgpu: Remove Non-FUSA code from common.fbp 
Rop_L2_en_mask and num_fbps are not accessed by Safety code; so move
their initialization code out Safety build using CONFIG_NVGPU_NON_FUSA.

JIRA NVGPU-4393

Change-Id: I9c518239cbfc99bbe0140386ecd4ca111f59b358
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244372
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
a8c9c800cd gpu: nvgpu: reorganization of MC interrupts control 
Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.

For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.

JIRA NVGPU-4336

Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
daf5475f50 gpu: nvgpu: split ecc support per GPU HW unit 
To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.

Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.

JIRA NVGPU-4336

Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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 2020-12-15 14:10:29 -06:00