There are three issues with shadow domain submission:
1. runlist mem is not being swapped with mem_hw for shadow domain when
there is non-shadow domain being bound to tsg which does not allow runlist
to have all the tsgs. To fix this nvgpu_runlist_swap_mem() is being called
for shadow domain as well.
2. tsg num_active_channels is being set as part of non-shadow domain which
does happen after shadow domain. Due to this, runlist tsg length is not
being set as part of runlist reconstruct and leaving tsg length 0 for last
tsg. To fix this, tsg num_active_channels always get set for shadow domain
as it gets configured first.
3. NV_BUILD_CONFIGURATION_VARIANT_IS_EMBEDDED is not solving the purpose
to differentiate l4t and embedded_linux builds so using
NV_BUILD_SYSTEM_TYPE in place of this to find out the build type.
L4t is using round robin scheduling and this issue coming with manual mode
scheduling so adding the fix only for manual mode scheduling support.
Bug 3884011
Change-Id: Ic55da8f75294eb32c8df6e35fb1fa47df78db8f8
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2833880
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This patch introduces the flag NVGPU_DISABLE_STATIC_POWERGATE. Further,
static pg related initialization APIs have been updated to check whether
this newly added flag is enabled. If this flag is enabled, then static
pg init gets skipped.
JIRA NVGPU-9350
Change-Id: I450b6dd2c541d31fc40fb5540e557b5db730fee2
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2834021
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This change is to adapt to shift of ACR t234 safety code from
iGPU to dGPU.
Required changes consists of:
Adding support for new LSB, WPR and ACR descriptor structures
which are more aligned with what dGPU currently uses.
Change old riscv LSB header to version 1, as version 2 will
be used for new header to align with dGPU header nomenclature.
Jira NVGPU-9298
Change-Id: Id75f7d0a03dc65c1983822ead428b330a83481a1
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2811116
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
EPL lib constructor is replaced by NvEplInit() by safety services.
NvGPU, being an EPL user, needs to call NvEplInit before using EPL
API to report errors.
NvEplInit() usage is limited to user space in Linux, so NvGPU is not
expected to call NvEplInit on Linux.
Bug 3863536
Change-Id: I7fc9b33d3443bd39a6367a0c691bddb80b9edb68
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2817245
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The memory leak issue was due to nvgpu_profiler_unbind_context() calling
nvgpu_profiler_pm_resource_release() for all resources which clears the
flag required by nvgpu_profiler_free_pma_stream() to release the memory
for perf_buf instance block.
Fixing this issue by splitting nvgpu_profiler_unbind_context() to release
all the pm resources at a later time separately.
Bug 3510455
Change-Id: Ibab8d071693e600c46f7e7f16575e36e6f62af3c
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2825013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This patch is required for
- enabling NVGPU driver on OOT by enabling various
configs required.
- replacing new APIs for some deprecated APIs by
guarding with linux version for soc.c.
- CONFIG_TEGRA_HV_MANAGER is enabled by default in OOT kernel,
removing CONFIG_TEGRA_HV_MANAGER check from various places.
Bug 3812973
Change-Id: I07f0b738ca95d4a3996e7f3ee5e895463db0626b
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822434
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On T234 theCTXSW LS ucodes are encrypted. ACR will perform the
decryption and the decrypted content will be written back
into the same WPR location. So on recovery with LSPMU absence
and on warm boot case, to perform the authentication , the ucode
blob needs to be copied into the WPR from sysmem always.
Below are the LS ucodes authentication type
* LSPMU - Only Signed ( Only for non-safety build, for safety LSPMU is NA)
* CTXSW FECS/GPCCS - Encrypted and Signed (on both safety and non-safety build)
ACR FW P4 Change : 32110924
JIRA NVGPU-7903
Change-Id: If447148c02b9cf310102cfb9c688eef402699409
Signed-off-by: Dinesh Kamalakannan <dineshka@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822656
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
nvpmodel updates the devfreq frequency limits as per power requirements
for specific chip. Clock arbiter ignored these limits and set clock
to maximum supported frequency which may lead to leaking power and
over heating.
Add support to get the devfreq limits by registering PM_QOS notifiers.
Note that with this patch we enable CONFIG_GK20A_PM_QOS when PM_DEVFREQ
is enabled. So it will be enabled for all supported kernels (4.9, 4.14
kernels continue to support this. For 5.10+ kernels notifiers added in
this patch will be used. Thermal framework related notifiers for kernels
after 4.14 will not be registered as those use downstream interfaces
that are not available.)
We maintain devfreq min/max limits in the scale profile and update those
in the notifier calls. We use these limits to clamp the frequency in the
clock arbiter.
Bug 3852824
Change-Id: I734a9fb080fee1a91e9b5da071b662dbd9a18682
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822686
(cherry picked from commit eacaf8cec2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822682
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Changes
1. Remove dGPU flag dependency on calling gsp sw init on tot.
2. Created Enable flag for gsp scheduler to enable them on ga10b
platforms.
3. Engine config flag is only enabled for dGPU enabled platforms, as gsp
is using engine functions it need to be enabled for all gsp sched
enabled builds.
4. Changes in gsp_sequence_init/de_init where on qnx we are seeing
issues.
NVGPU-9297
Change-Id: Ia4bce85ae8fd2794da1553e9ea418c76845a10ac
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822537
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- As part of mmap call handler mmap_sem is being acquired which is
causing an BUG: scheduling while atomic:. This is happening because
mmap callback gets called with mmap_sem held. The mmap file handler
is called via call_mmap() via mmap_region() via do_mmap(), and the
caller of do_mmap() must hold down_write(¤t->mm->mmap_sem).
To fix this issue removing the mmap_sem locking from nvs mmap handler.
- If remap_vmalloc_range() is used to map the pages to userspace then
allocated pages should be mapped into virtually contiguous space by
passing VM_USERMAP flag to vmap(). Passing VM_USERMAP to vmap() call
if API nvgpu_dma_alloc_flags_sys() is called with flag
NVGPU_DMA_VM_USERMAP_ADDRESS.
Bug 3884011
Change-Id: I64264f6f6e0dd75b1f828dc58355d740e6ef5ccb
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820781
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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As part of supporting GPU minimal boot, some of the HALs are assigned
with NULL. Before dereferencing such HALs, check for NULL.
Further, this patch reorganizes needs_init API to first check whether a
function pointer is NULL, to enable quick turnaround to the caller of this API.
JIRA NVGPU-9283
Change-Id: I768d1cddef8766948c99892c59f6ebe6f31be9d8
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814225
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add API to query all memhandles used for pde and pte.
- Some direct pde/pte allocation should also add entry to the pd-cache
full list.
- Add OS API for querying MemServ handle from nvgpu_mem.
- Traverse through all pd-cache partial and full lists to get memhandles
for all pde/pte buffers.
Jira NVGPU-8284
Change-Id: I8e7adf1be1409264d24e17501eb7c32a81950728
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2735657
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Now that we are planning to enable CTRL_FIFO support with NVS,
there is no need for a separate enabled flag for the same.
CTRL_FIFO support is instead determined by the presence of
NVGPU_SUPPORT_NVS enable flag alone.
For non-auto platforms, Control-Fifo can be disabled by restricting
access to /dev/nvsched_ctrl_fifo.
Jira NVGPU-8619
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I9dbec60e5668f38e1460c43800584e88b16a2550
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814435
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Use CONFIG_KMD_SCHEDULING_WORKER_THREAD instead of
CONFIG_NVS_KMD_BACKEND to remove confusion about the CPU based
KMD scheduling worker thread.
The KMD based scheduling worker thread caters to both Manual Mode
CPU based scheduler as well as Automatic Round Robin CPU based
scheduler.
For the traditional submit path, add correct handling of the
CONFIG_NVS_PRESENT. CPU based worker thread should be part of
CONFIG_NVS_PRESENT. Eventually, when DCONFIG_KMD_SCHEDULING_WORKER_THREAD
is removed, the application must switch to GSP.
Jira NVGPU-8619
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I0886ef3b2e0124b6fe22c2bf0bf7d1fa98039d00
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2810217
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Mon subelement needs to access GPC TPC configuration registers
to figure out GPC/TPC count post floor sweeping. These registers
are needed as part of intr handling.
Move priv ring init ahead in RM boot to make sure priv ring
enumeration is done before any unit enables it's interrupts.
This ensures that priv ring is enumerated before any interrupt
handler is run to access GPC/TPC count.
JIRA NVGPU-6528
Change-Id: I8aa6ac182e6dd60a79fa76af6813ea70102316f4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2809442
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- The pmu_pg_task thread remains alive in the background
during railgate and rail-ungate.
- During rail-ungate, the PG task thread starts again and
executes PG-related tasks.
- It comes in pmu_pg_init_powergating() and waits for GR
initialization. Here it waits for gr to be initialized.
- In parallel, the main GPU thread works on rmmod (from
gpu_module_reload test).
- By this time, the main gpu thread has started rmmod and
gr->initialized can be set to false, thus causing an uninterruptible
wait for pmu_pg_task thread.
- To solve this, wake gr wait wq in rmmod path when
NVGPU_DRIVER_IS_DYING and NVGPU_KERNEL_IS_DYING flgas are set.
Bug 3806514
Change-Id: Id78d92f30b75aba1aee22398cc86a3acebd50ef6
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2798003
(cherry picked from commit d9345065bcb6d9ff497c127fa4cd52077f4ecfa4)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2807245
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Any corrected or uncorrected error reported by gpu hw
will be seen by nvgpu-mon. nvgpu-mon will raise a devctl call
to notify nvgpu-rm if its a fatal error interrupt.
nvgpu_cic_mon_handle_fatal_intr is the corresponding handler which will
walk through the entire tree structure of interrupts for all the subunits
and enter quiesce state.
Change-Id: I3c00c61a7f2c52ae1920f84ee7dfb65cba6b683d
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2801693
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Get the device id from runlist pri base instead of reading from
runlist structure which could be failing if the device node not
present inside the runlist struct.
This Change will call the get device id hal to get it from rlend_id
and runlist pri base.
NVGPU-8531
Change-Id: Ia81189a6c2281ed09ee52eb461f0cd87164c5fc4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2791605
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In order to share the TSG across different devices securely, device
instance IDs are to be exchanged for endpoint identification. Add
device instance ID field to gk20a_ctrl_priv which is generated
from gk20a level device instance id value.
Share this ID to userspace via gpu characteristics.
Bug 3677982
JIRA NVGPU-8681
Change-Id: I79d92a81c02272c52e24f5b12c452c8993137037
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2792079
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Currently, the registeration with error injection utility is done
only for GA10b using HAL. But HALs are not initialized during the
probe stage when we try to register the error injection utility.
So, the callback registration does not happen HAL is set to NULL.
Move the callback registration from probe to poweron stage when HAL
is initialized.
Update the nvgpu_cic_mon_init_lut() API name as it is no longer
doing only LUT initialization.
Bug 3828050
Change-Id: Ide718029e9317124749b4a51c423ae70dc8227c8
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2790269
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Implement the ioctls NVGPU_TSG_IOCTL_CREATE_SUBCONTEXT and
NVGPU_TSG_IOCTL_DELETE_SUBCONTEXT. These will allocate and
free the VEID numbers.
Address space association with the VEIDs is verified to
ensure that channels association with VEIDs and address
space remains consistent.
Bug 3677982
JIRA NVGPU-8681
Change-Id: I2d913baf61a6bdeec412c58270c0024b80ca15c6
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2766765
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
