As the docs of nvgpu_thread say, each thread (which the worker loop is)
should wake up and check also nvgpu_thread_should_stop() to manage
graceful and quick exit as requested. The loop does have that check
already, but the workqueue condition does not, so the cond wait might
end up waiting until its timeout hits.
It's not robust to trust the worker users to have a swift timeout for
exiting the thread, so read the should-stop flag in the wakeup condition
too.
Simplify the clk arb worker ops now that calling
nvgpu_worker_should_stop from there is no longer necessary. (Other
worker users did not have those, so they were technically buggy.)
Change-Id: I5409b8037564d4b6445a15cdbd4f1f3d616c4083
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2635808
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Instead of using multiple struct use a single nvgpu_clk_slave_freq
to store the slave freq of gpcclk.
With this patch single struct can be used by both clk_arb and clk_domain.
This will remove nvgpu_set_fll_clk struct as nvgpu_clk_slave_freq serves
the purpose.
NVGPU-4692
Change-Id: Ie45d63e4376b83e153a9aa75e2c4631c6dad857b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339213
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In the upstream kernel ACCESS_ONCE is now deprecated with reason as
given in the following related commit:
commit 381f20fceba8e ("security: use READ_ONCE instead of deprecated
ACCESS_ONCE")
ACCESS_ONCE() does not work reliably on non-scalar types. For
example gcc 4.6 and 4.7 might remove the volatile tag for such
accesses during the SRA (scalar replacement of aggregates) step.
Replace usages of ACCESS_ONCE with READ_ONCE and WRITE_ONCE in nvgpu.
Bug 2834141
Change-Id: I9904c49e1a4d7b17ed2fe54360051d08595a2982
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294096
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Current clk unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from pmuif which only
clk can access.
All public items are moved into include/clk.h which other units can
access
This will help in documentation of items for public items.
NVGPU-4491
Change-Id: Iccb0571e05ecb3cb13363390bed8c7214409b543
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292318
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-Created perf.h file and moved all private functions
and structures into it
-Created single sw_setup/pmu_setup for whole perf
unit
-Changed public function and structure names as per
standard format
-Deleted lpwr unit specific file from make file as
it is no longer used
-Removed support_vfe and support_changeseq flags as
it is no longer used
-Removed clk_set_boot_fll_clks_per_clk_domain function
as it is no longer used for tu10a
-Removed perf unit headers from pmuif folder
NVGPU-4448
Change-Id: Ia29e5b5a1a960b5474a929d8797542bf6c0eccf1
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283587
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-Created ucode_perf_pstate_inf.h and moved all
pstate interface structs and MACROs.
-Created nvgpu_perf_pstate_get_lpwr_index for getting
lpwr index
-Created nvgpu_clk_domain_get_from_index for getting
clk_domain from index
-Removed pstate_get_status code which is not needed
for tu10a profile
-Removed MACROs and includes which are not needed
NVGPU-4448
Change-Id: I516816a1d92a60a91ea479cb9c334d332d3d7a89
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264716
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Rule 5.7 doesn't allow an identifier to be reused. This patch renames
identifier 'notification' to resolve this violation.
- Rule 8.3 requires all functions and prototypes to have same parameter
names and type qualifier.
- Rule 10.x necessitates operands to have essential type, and left and
right operands should be of same width.
- Rule 11.9 requires pointers to be compared with 'NULL' instead of '0'.
- Rule 14.4 requires if statement condition to be Boolean type.
- Rule 15.7 needs if-elseif constructs to be terminated with else
statement.
- Rule 16.x requires all switch statements to be well-formed with
unconditional break statement terminate every switch-clause.
- Rule 20.7 requires macro parameters to be enclosed in parentheses.
- Rule 21.x doesn't allow reserved identifier or macro names to be
reused or defined.
This patch fixes above listed violations in common/clk_arb/clk_arb.c.
Jira NVGPU-3740
Change-Id: I871ce240ca7fb0372240a8886a53c8d4c460acea
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2147640
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-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0
JIRA NVGPU-3418
Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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PG189 has multiple sensors which can provide interrupt when board
temperature reaches programmed threshold.
This Interrupt is implemented in nvgpu and provide events via clk_arb.
Support is enabled for TU104 with NVGPU_SUPPORT_DGPU_THERMAL_ALERT flag.
Board specific config is added in DT which will be parsed by nvgpu.
Nvgpu does the following.
1.Read gpio line number, interrupt type, and event delay from DT.
2.Call kernel methods and register the interrupt with kernel.
3.Create work queue which will process the interrupt in process context.
4.When interrupt occurs disable interrupt, add work to work queue.
5.In work queue post events and sleep for delay time then enable
Interrupt
Bug 2492512
Change-Id: Ic5694fe366ca492f8afe8a67de4350e9a51af2af
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119411
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MISRA Rule 14.2 requires for loop to be well-formed. A well-formed for
loop has below requirements:
1. first clause can be empty or should assign value to a single loop
counter
2. second clause should exist and use loop counter or loop control flag.
It should not use any variable modified in the loop body.
3. third cluase should only update loop counter and should not use
objects modified in the loop body.
This modifies for loops to process single loop counter. The patch moves
additional initializations before for loop, conditions at loop start
and variable updates at the end of for loop.
Jira NVGPU-855
Change-Id: I93ccf1ac0677ff355364a718d2d953467f1d9d95
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108188
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MISRA rule 2.2 doesn't allow unused functions and assignments in code.
The reason is presence of unused functions or variable assignments may
indicate error in program's logic. This patch removes an unused function
following rule 2.2.
Jira NVGPU-858
Change-Id: I80b4ae3486038de1a9b1c3afc3b4f17f18cc9efd
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111616
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Moved nvgpu_clk_pmupstate structure from gk20a to
nvgpu_pmu.The aim is to have single pmu structure inside
gk20a, that is "nvgpu_pmu" struct and all the global
structures of all units in PMU should be included in
"nvgpu_pmu" struct.
NVGPU-3220
Change-Id: I531aab568a692c55e640ca2c33aa7508b83a9593
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104129
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Currently, both clk_arb and channels use their own implementation of
a background worker. These implementations are almost identical and can
be extracted out into a single self-contained unit name nvgpu_worker.
Another advantage of using a single worker unit is to avoid duplication
of Unit Tests for this unit in other units.
channel and clk_arb units provide their own specific implementations
via an ops interface named nvgpu_worker_ops which is a part of the
nvgpu_worker struct.
The following high level APIs are exposed by the nvgpu_worker
nvgpu_worker_should_stop
nvgpu_worker_enqueue
nvgpu_worker_init
nvgpu_worker_deinit
The nvgpu_worker_ops containg the following function pointers
pre_process
wakeup_early_exit
wakeup_post_process
wakeup_process_item
wakeup_condition
wakeup_timeout
The specific code in channel and clk_arb is changed to use the above
implementations instead of their own separate implementations.
Jira NVGPU-3101
Change-Id: I14a0bba6a3d61a642b858dec70d5818d5a0472a4
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090475
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Description:
Present p-state unit handle both pstate boardobj and
initializing all the units. As part of restructuring,
the pstate unit is separated into two units:
1) Perf_pstate: This unit will handle pstate boardobjs.
2) Pmu_pstate: This unit will initialize all the units
which supoort performance states.
Changes:
1) Created pmu_pstate unit.
2) Pstate boardobjs are moved under perf_pstate which
is under perf unit.
NVGPU-1958
Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096339
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This patch fixes below two issues.
1.Currently clk arb exit is called after GPU registers are released.
This causes crash when clk arb WQ accesses GPU HW register for status.
The ideal way is to exit the clk_arb which removes the WQ from running
before calling lockout register.
2.Check if dGPU is dying during processing of PMU Commands.
This prevents race condition when PMU is waiting for response and device
is shutdown.
Bug 200488054
Change-Id: I812b07af7db4494d5ea2ed6197742ceb23d30a4b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081916
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Description:
nvgpu_clk_pmupstate is the global structure in clk units. It is declared
in clk.h and all clk units will include clk.h header.
nvgpu_clk_pmupstate struct will have structure pointers to all clk units
and will include genereic function pointers which are used by most clk
units. The reason why the function pointers is defined in this sturct,
and not included inside g->ops is because, these are only clk specific
functions and rest of the driver code is not dependent on this.
Each unit will have init function to allocate memory for its structure
and will initialize its local functions.
Changes:
1) Introduced nvgpu_clk_pmupstate in clk.h file. All the changes needed
to call the above struct from individual clk units.
2) Removed cyclic dependency headers in clk units by calling function
through pointers defined in clk.h.
3) Initialization of each unit is done in respective unit instead of
doing it in clk unit. Added *_init_pmupstate and *_free_pmupstate to
individual clk units.
4) Each unit clean up will be done separately while refactoring that
unit.
NVGPU-1963
NVGPU-2965
Change-Id: Iee79d7a812b62407252636057b104f952c94a229
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033537
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch ensures that WARN and WARN_ON always return void; and
introduces a new nvgpu_do_assert construct to trigger the equivalent
of WARN_ON(true) so that stack can be dumped (depends on OS support)
JIRA NVGPU-677
Change-Id: Ie2312c5588ceb5b1db825d15a096149b63b69af4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018706
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As a part of regoranizing clk_arb code, This patch does the folowing
1. Move clk_arb HAL files under common/clk_arb unit.
2. Move clk_arb from common/pmu to common/clk_arb.
3. Append public functions with nvgpu.
4. Make local functions as static.
Jira NVGPU-1966
Change-Id: If45c3dbfc4bbe74fe8d30e33e64894d553f3cda5
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027335
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