WAR assume 1:1 IPA to PA mapping when hyp_read_ipa_pa_info fails for
the syncpt address which falls into syncpt shim aperture. API
nvgpu_mem_phys_sgl_ipa_to_pa() is taking care of IPA to PA mapping for
the syncpts which makes this WAR invalid.
Patch removes the WAR.
Bug 200673604
Change-Id: I966711e11c2ff1b5b5dd3f5e09674bea66c5d04b
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478068
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Add new MAPPING_MODIFY ioctl to the linux nvgpu driver.
This ioctl is used (for example) by the NvRmGpuMappingModify API to
change the kind of an existing mapping.
For compressed mappings the ioctl can be used to do the following:
* switch between two different compressed kinds
* switch between compressed and incompressed kinds
For incompressed mappings the ioctl can be used to do the following:
* switch between two different incompressed kinds
In order to properly update an existing mapping the nvgpu_mapped_buf
structure has been extended to cache the following state when the
mapping is first created:
* the compression tag offset (if applicable)
* the GMMU read/write flags
* the memory aperture
The unused ctag_lines field in the nvgpu_ctag_buffer_info structure
has been replaced with a new ctag_offset field.
Jira NVGPU-6374
Change-Id: I647ab9c2c272e3f9b52f1ccefc5e0de4577c14f1
Signed-off-by: scottl <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2468100
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Rename struct nvgpu_runlist_info to struct nvgpu_runlist; the
info is not necessary. struct nvgpu_runlist is soon to be a
first class object among the nvgpu object model.
Also rename the fields runlist_info and active_runlist_info to
simply runlists and active_runlists respectively. Again the info
text is just not necessary and somewhat misleading. These structs
_are_ the runlist representations in SW; they are not merely
informational.
Also add an rl_dbg() macro to print debug info specific to
runlist management and some debug prints specifying the runlist
topology for the running chip.
Change-Id: Id9fcbdd1a7227cb5f8c75cca4abbff94fe048e49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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The NEXT bit can remain set for the channel if timeslice expires before
scheduler clears it. Due to this nvgpu fails TSG unbind and in turn
nvrm_gpu fails channel close. In this case, checking the channel hw
state after some time can help see NEXT bit cleared by scheduler.
Reenable the tsg and return -EAGAIN to nvrm_gpu for it to retry again.
Bug 3144960
Change-Id: I35f417f02270e371a4e632986b73a00f8a4f921a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2468391
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For Linux v5.11, commit 6619ccf1bb1d ("dma-buf: Use struct dma_buf_map
in dma_buf_vmap() interfaces") changes to the dma_buf_vmap() and
dma_buf_vunmap() APIs to pass a new parameter of type
'struct dma_buf_map'. Update the NVGPU to support these updated APIs
for Linux v5.11+.
Finally, the legacy dma_buf_vmap() API returns NULL on error and not an
error code and so correct the test of the return value in the function
gk20a_cde_convert().
Bug 200687525
Change-Id: Ie20f101e965fa0f2c650d9b30ff4558ce1256c12
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2469555
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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New profiler APIs set regop type based on whether context is bound or
not in nvgpu_prof_get_regops_staging_data(). But it is possible that
ctxsw is not enabled for some particular HWPM resource even if context
is bound to profiler object.
Fix this by extracting regop type based on per-resource ctxsw flag
instead of bound context.
Add reg_op_type[] array in profiler object to track regop type for each
HWPM resource. Initialize the array based on resource ctxsw flag in
nvgpu_profiler_pm_resource_reserve().
Update profiler_obj_validate_reg_op_offset() to get regop type from
nvgpu_profiler_validate_regops_allowlist() and use this type and
prof->reg_op_type[] to get actual type that should be used for that
regop.
Update validate_reg_ops() to validate the offset first since regop
type is now determined in offset validation. Set ops[i].status to 0
for each validation iteration, and if op is valid set it to
REGOP(STATUS_SUCCESS) at the end of iteration.
Bug 2510974
Jira NVGPU-5360
Change-Id: Ib1f75d840d04d288789473adabda02cdc807eea0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460003
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Add gv11b and tu104 HALs to get allowed HWPM resource register ranges,
offsets, and stride meta data.
Add new enum nvgpu_pm_resource_hwpm_register_type for HWPM register
type. Add new struct nvgpu_pm_resource_register_range_map to store all
the register ranges for HWPM resources. Add pointer of map in struct
nvgpu_profiler_object along with map entry count.
Add new API nvgpu_profiler_build_regops_allowlist() to build the regops
allowlist dynamically while binding the resources. Map entry count is
received with get_pm_resource_register_range_map_entry_count() and only
those resource ranges are added for which resource is reserved by
profiler object.
Add nvgpu_profiler_destroy_regops_allowlist() to destroy the allowlist
while unbinding the resources.
Add static functions allowlist_range_search() to search a register
offset in HWPM resource ranges. Add another static function
allowlist_offset_search() to search the offset in per-resource offset
list.
Add nvgpu_profiler_validate_regops_allowlist() that accepts an offset
value, checks if it is in allowed ranges using allowlist_range_search()
and then checks if offset is in allowlist using allowlist_offset_search().
Update gops.regops.exec_regops() to receive profiler object pointer as
a parameter.
Invoke nvgpu_profiler_validate_regops_allowlist() from
validate_reg_ops() if prof pointer is not-null. This will be true only
for new profiler stack and not legacy profilers.
In gr_exec_ctx_ops(), skip regops execution if offset is invalid.
Bug 2510974
Jira NVGPU-5360
Change-Id: I40acb91cc37508629c83106ea15b062250bba473
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460001
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With Generic Power Domains (genpd), bpmp driver will manage the GPU
powergating. With the nvgpu idle/unidle flows updated for VPR with
genpd/RPM, the usage of the below tegra bpmp calls can be removed
from nvgpu from railgate APIs for t186 and t194. Note that genpd
is available in k4.14 onwards, so this will work on current
downstream kernel.
tegra_bpmp_running
tegra_powergate_is_powered
tegra_powergate_partition
tegra_unpowergate_partition
Runtime suspended state indicates that the device is railgated.
Update the t186 and t194 is_railgated handlers with this. t210
railgate/unrailgate will be still managed by nvgpu as bpmp
support is not present.
Bug 200602747
JIRA NVGPU-5356
Change-Id: Iadfd794cb51bc41ca927b84fc212ac766d60094d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376642
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Extend the runtime suspend/resume based idle/unidle logic in the
probe case to handling done in gk20a_do_idle/unidle for nvgpu
after the probe completion.
If the railgating is disabled, setting autosuspend_delay to 0 will
enable the suspend. If railgating is enabled, autosuspend delay
will be > 0. Setting it to 0 will enable the immediate suspend.
With this approach based on RPM, forced_reset logic is removed.
force_reset_in_do_idle is also removed as railgating is
supported.
Bug 200602747
JIRA NVGPU-5356
Change-Id: Iaf6d5ab651b8200f0547b45d90f812110cf63c0e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2375941
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With genpd based runtime PM, the device railgating is managed by the PM
core and the nvgpu manages the clocks. To suspend/resume the device for
idling/unidling while initializing secure alloc, runtime PM is to be
enabled during probe.
nvgpu platform railgate handlers will be only managing the clocks.
During probe, the nvgpu driver poweroff/poweron are not to be
invoked as part of driver runtime suspend/resume hence probe
state is added.
After platform probe initializes the clock, explicit runtime resume of
the device is required to sanely suspend it during gk20a_do_idle.
Runtime PM configuration differs based on the NVGPU_CAN_RAILGATE
capability, hence the runtime PM is enabled ("truly") only for
the duration of nvgpu_probe and then the state is reverted at
the beginning of gk20a_pm_late_init.
Bug 200602747
JIRA NVGPU-5356
Change-Id: I1fbd03d3f49da07ccbee9714387e00ffc688864e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2375939
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With genpd based runtime PM, the device railgating is managed by the PM
core and the nvgpu manages the clocks. To suspend/resume the device for
idling/unidling while initializing secure alloc, runtime PM will be
enabled before init_secure_alloc.
nvgpu platform railgate handlers will be only managing the clocks. The
clocks and secure alloc initialization was done in platform probe
(applicable to tegra).
To suspend (railgate and clks disable) and resume cleanly during secure
alloc init, the platform probe should happen first that initializes the
clocks. Post that device runtime PM will handle the device idle/unidle
properly.
Hence, move gk20a_tegra_init_secure_alloc to platform late_probe.
Runtime PM changes are introduced in the later patches.
Bug 200602747
JIRA NVGPU-5356
Change-Id: I5130ff43f7b75ddc51cb7096ba6532b3f5397258
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2375938
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In K5.9 those two functions are changed to reject calls directly
using global pmc pointer. So it's a bit complicated to revert to
the point where GPU can feel free to call them.
For an easier future mantainance, a new set of APIs are added to
all existing kernels to let GPU driver control clamp without any
direct access to PMC registers.
Bug 200663781
Change-Id: Ifce4765525eee6d61083896fc9a126892cbb86ba
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2441010
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This CL covers the following code changes,
1) Added some more documentation for gpu_instance_id
and gr_instance_id.
2) Used the gr_sys_pipe_id for gr_instance_id.
2) Removed gr_syspipe_id attribute.
4) Removed NVGPU_GPU_FLAGS_SUPPORT_MIG flag.
3) Changed the device node name to use gpu instance id + syspipe id
combination insted of gpu instance id + gr engine instance id.
Bug 2802347
Change-Id: Id6ca7db5765ab31b5d83472be35dde432c2281ed
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2440532
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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On Linux, nvrm_gpu can open channel/tsg/address space only using ctrl
node. This tricks nvrm_gpu into considering physical instance as
actual available fGPU if ctrl node is exposed for physical instance.
There is no current requirement to expose physical instance ctrl node.
It might be needed later for profiling use cases.
For now, skip dev node creation for physical instance.
Jira NVGPU-5648
Change-Id: I23398ba993f97e2d2f344876c0c6b0c82b336402
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2439880
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Store nvgpu_cdev pointer in struct tsg_private and assign it in
nvgpu_ioctl_tsg_open.
In gk20a_tsg_ioctl_bind_channel_ex(), extract gpu_instance_id from
cdev pointer and then extract instance specific max VEID count from
gpu_instance_id.
Use this max veid count to validate subcontext id coming from user.
Jira NVGPU-5648
Change-Id: I71cea5180e1ced1a72818d160f1a951c1c6ec770
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2438925
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nvgpu_channel_get_max_subctx_count() right now always returns max subctx
count for 0th instance. Update this function to return max subctx count
for GPU instance for which channel is allocated.
For CE channels that are allocated and managed by nvgpu, cdev pointer is
not set in channel private data (since it is assigned in OS specific
code). For those channels continue returning max subctx count for 0th
instance. CE channels should not need subcontexts anyways.
Add nvgpu_cdev pointer in struct nvgpu_channel_linux. Assign it in
__gk20a_channel_open() and clear it in gk20a_channel_release()
Move code to get runlist and gpu_instance_id after nvgpu_get() call.
Accesses to gk20a pointer should always come after nvgpu_get().
Also add a debug print to dump runlist_id and gpu_instance_id being
used for channel.
Jira NVGPU-5648
Change-Id: Idf58ccefdb7dc9fec78100f79c647e5a00b8fb29
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2438924
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Separate out nvgpu_gpu_fetch_engine_info_item() that populates
engine_id/engine_instance/runlist_id for given nvgpu_device.
Update Existing API nvgpu_gpu_get_engine_info() to use above function.
Add new API nvgpu_gpu_get_gpu_instance_engine_info() that populates
instance specific engine information.
Update NVGPU_GPU_IOCTL_GET_ENGINE_INFO sequence to trigger
nvgpu_gpu_get_gpu_instance_engine_info() for fGPU instances in
MIG mode. Continue using nvgpu_gpu_get_engine_info() in
non-MIG mode and for physical instance in MIG mode.
Jira NVGPU-5648
Change-Id: Ia946748fa2b0c27efa7704847cdf9bb44a0749da
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2436753
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Update gk20a_ctrl_dev_ioctl() to fetch gpu_instance_id with
nvgpu_get_gpu_instance_id_from_cdev() and gr_instance_id with
nvgpu_grmgr_get_gr_instance_id().
Get instance specific GR engine configuration pointer with
nvgpu_gr_get_gpu_instance_config_ptr()
Update gk20a_ctrl_ioctl_gpu_characteristics() to return instance
specific characteristics with below changes :
- 0th GPU instance is a physical instance. Set a limited and relevant
characteristics flags for 0th instance.
For rest of the instances and non-MIG mode, continue fetching flags
with nvgpu_ctrl_ioctl_gpu_characteristics_flags.
- nvgpu_set_preemption_mode_flags() should be set only for non-MIG mode
and non-zero instance in MIG mode.
- In MIG mode, 0th instance does not support any classes. Rest of the
instances support only compute, copy and gpfifo classes.
Non-MIG mode supports all the classes including graphics ones.
- Fetch gpu_instance_id/gr_sys_pipe_id/gr_instance_id from gpu_instance
pointer.
- Fetch max_veid_count_per_tsg from gpu_instance pointer.
Also update nvgpu_gr_get_zcull_ptr() and nvgpu_gr_get_zbc_ptr() to
return instance specific pointers. zcull/zbc are not supported in MIG
mode, this is just for consistency of the code.
Jira NVGPU-5648
Change-Id: I764526061542c48ed87659844e16dd0e0253c588
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2436752
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- Modify NVGPU_GPU_IOCTL_ALLOC_AS and struct nvgpu_alloc_as_args to
accept start address and size of user memory. This allows configurable
address space allocation.
- Modify gk20a_as_alloc_share() and gk20a_vm_alloc_share() to receive
va_range_start and va_range_end values.
- gk20a_vm_alloc_share() initializes vm with low_hole = va_range_start,
and user vma size = (va_range_end - va_range_start).
- Modify nvgpu_as_alloc_space_args and nvgpu_as_free_space_args to
accept 64 bit number of pages.
Bug 2043269
JIRA NVGPU-5302
Change-Id: I243995adf5b7e0e84d6b36abe3b35a5ccabd7a37
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2385496
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In __gk20a_channel_open(), if runlist_id is provided as -1,
pick up correct GPU instance sprcific default runlist id using
nvgpu_grmgr_get_gpu_instance_runlist_id().
Also, get GPU instance is using nvgpu_get_gpu_instance_id_from_cdev()
If runlist_id is received as input, check if it is valid for given
GPU instance with nvgpu_grmgr_is_valid_runlist_id()
Jira NVGPU-5648
Change-Id: I69303a3dd81f28f474b40564da51254bcaa1ed15
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435467
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Add new API nvgpu_get_gk20a_from_cdev() that extracts gk20a pointer
from cdev pointer. This helps in keeping cdev related implementation
details in ioctl.c and away from other device ioctl files.
Also move struct nvgpu_cdev, nvgpu_class, and nvgpu_cdev_class_priv_data
from os_linux.h to ioctl.h since all of these structures are more IOCTL
related and better to keep them in ioctl specific header.
Jira NVGPU-5648
Change-Id: Ifad8454fd727ae2389ccf3d1ba492551ef1613ac
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435466
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Add new API nvgpu_get_gpu_instance_id_from_cdev() that returns GPU
instance id from nvgpu_cdev pointer.
Store cdev pointer in channel private data channel_priv and ctrl node
private data gk20a_ctrl_priv.
Update below functions to pass cdev pointer :
__gk20a_channel_open()
gk20a_channel_open_ioctl()
In gk20a_channel_ioctl(), extract gpu instance id using cdev pointer
stored in channel_priv and new API nvgpu_get_gpu_instance_id_from_cdev().
Extract GR instance id using nvgpu_grmgr_get_gr_instance_id()
Invoke context creation API inside nvgpu_gr_exec_with_err_for_instance()
so that context is created with correct GR instance id.
Jira NVGPU-5648
Change-Id: I5a4e79165e021b56181d08105b2185306a19703b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435465
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Reviewed-by: Lakshmanan M <lm@nvidia.com>
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GVS: Gerrit_Virtual_Submit
In MIG mode, each of the dev nodes should be enumerated for each fGPU.
And for physical instance only the "ctrl" node should be enumerated.
Support this with below set of changes :
- Add struct nvgpu_mig_static_info that describes static GPU instance
configuration. GPCs are enumerated only during poweron and grmgr unit
will populate instance information based on number of GPCs.
For linux, GPU poweron happens only with first gk20a_busy() call and
instance information is not available during probe() time. Hence this
static table is a temporary solution until proper solution is
identified.
- Add nvgpu_default_mig_static_info for iGPU and
nvgpu_default_pci_mig_static_info for dGPU that describes GPU instance
partition.
- Add new function nvgpu_prepare_mig_dev_node_class_list() that parses
the static table and creates one class per instance in MIG mode.
Non-MIG mode classes are now enumerated in
nvgpu_prepare_default_dev_node_class_list().
- Add new structure nvgpu_cdev_class_priv_data to store private data for
each cdev. This will hold instance specific information and pointer to
private data will be maintained in struct class and also passed as
private data while creating device node with device_create()
- Add nvgpu_mig_phys_devnode() to set dev node path/names for fGPUs and
add nvgpu_mig_fgpu_devnode() to set dev node path/names for physical
instance in MIG mode.
- Add new field mig_physical_node to struct nvgpu_dev_node. This field
is set if corresponding dev node should be created for physical
instance in MIG mode. For now set it only for "ctrl" node.
Jira NVGPU-5648
Change-Id: Ic97874eece1fbe0083b3ac4c48e36e06004f1bc2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434586
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Remove devnode_class pointer from struct nvgpu_os_linux and replace it
by a list head.
Add new structure nvgpu_class to store class related meta-data and
create it dynamically in nvgpu_create_class().
Add new function nvgpu_prepare_dev_node_class_list() to prepare list of
all classes that are required for each GPU.
For now there is only one class per GPU, but in MIG mode multiple
classes will be created with one class per instance.
Update gk20a_user_init() to loop through list of classes and create
dev nodes for each class.
gk20a_user_deinit() frees up the linked list.
Jira NVGPU-5648
Change-Id: I891a55c0ce1c2ff9db094564529b3f569df9735c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2428501
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GVS: Gerrit_Virtual_Submit
Remove static dev node meta data from struct nvgpu_os_linux and replace
it by a dynamic list. Struct nvgpu_os_linux will only keep track of list
head and number of entries.
Add new structure nvgpu_cdev to store meta data of each dev node and
create/setup it dynamically in gk20a_user_init(). Once done, add the new
node under list head maintained in nvgpu_os_linux.
Add a static list dev_node_list[] that contains list of dev node names
and file operations. This static list is used to create nvgpu_cdev data
structures and to register new device nodes.
Update all dev node open file operations (e.g. gk20a_as_dev_open()) to
extract struct gk20a pointer from device pointer of dev node.
gk20a device is the parent of dev node device.
Jira NVGPU-5648
Change-Id: If070c3428afd6215e45b4919335d9f43e04c36f9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2428500
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GVS: Gerrit_Virtual_Submit
Remove static class definition and registration for iGPU and dGPU.
Create the class dynamically in gk20a_user_init() and setup the callback
function to create devnode name based on GPU type.
For now add nvgpu_pci_devnode() callback for dGPU that sets correct
dev node path for dGPUs. For iGPU, Android apparently does not honor dev
node path set in callback and hence override the device name for iGPU
with function nvgpu_devnode().
Destroy the class in gk20a_user_deinit().
This will overall be helpful in adding multiple classes and dev nodes
for each GPU instance in MIG mode.
Set GPU device pointer as the parent of new devices created with
device_create(). This is helpful in getting GPU device name in
callback function nvgpu_pci_devnode().
Update functions to not pass class structure and interface names :
nvgpu_probe()
gk20a_user_init()
gk20a_user_deinit()
nvgpu_remove()
Remove static interface name format like INTERFACE_NAME since it is no
longer needed.
Update GK20A_NUM_CDEVS to 10 since there are 10 dev nodes per GPU right
now.
Jira NVGPU-5648
Change-Id: I5d41db5a0f87fa4a558297fb4135a9fbfcd51080
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2423492
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Use fixed address mapping for pma byte buffer so that the address of
this buffer always fits in 32 bits.
This also requires to move unmap sequence to OS specific function since
different unmap API is now needed for linux and QNX.
Also call nvgpu_prof_free_pma_stream_priv_data() before
nvgpu_profiler_free_pma_stream() since former uses mm->perfbuf which
is released in later.
Bug 2510974
Jira NVGPU-5360
Change-Id: I398b0ca4f96527d6e09c9aacacb4b43c90f5bfc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2424691
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GVS: Gerrit_Virtual_Submit
Background: There is a race that occurs when l2_fb_ops ioctl is
invoked. The race occurs as part of the flush() call while a
gk20_idle() is in progress.
This patch handles the race by making changes in the l2_fb_ops
ioctl itself. For cases where pm_runtime is disabled or railgate is
disabled, we allow this ioctl call to always go ahead as power is
assumed to be always on.
For the other case, we first check the status of g->power_on. In the
driver, g->power_on is set to true, once unrailgate is completed and is
set to false just before calling railgate.
For linux, the driver invokes gk20a_idle() but there is a delay after
which the call to the rpm_suspend()'s callback gets triggered. This
leads to a scenario where we cannot efficiently rely on the
runtime_pm's APIs to allow us to block an imminent suspend or exit if
the suspend is currently in progress. Previous attempts at solving this
has lead to ineffective solutions and make it much complicated to
maintain the code.
With regards to the above, this patch attempts to simplify the way this
can be solved. The patch calls gk20a_busy() when g->power_on = true.
This prevents the race with gk20a_idle(). Based on the rpm_resume and
rpm_suspend's upstream code, resume is prioritized over a suspend
unless a suspend is already in progress i.e. the delay period has been
served and the suspend invokes the callback. There is a very small
window for this to happen and the ioctl can then power_up the device as
evident from the gk20a_busy's calls.
nvgpu power state is queried using nvgpu_is_powered_off to determine
whether to skip the resume. power state is protected under spinlock.
Bug 200507468
Change-Id: I5c02dfa8ea855732e59b759d167152cf45a1131f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299545
(cherry picked from commit 06942bd268)
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2425682
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GVS: Gerrit_Virtual_Submit
In linux kernel v4.14 and below gpu sysfs node is created under
/sys/devices. In linux kernel v5.x it is created under
/sys/devices/platform.
Create symbolic link gpu.0 under /sys/devices/ as various tests
and scripts expect it to be there.
Bug 200665782
Change-Id: I807ce72fad94438f927df25e829082e771b72543
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2426544
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Fuse registers should be queried with physical gpc-id and not the
logical ones. For tu104 and before chips physical gpc-ids are same as
logical for non-floorswept config but for newer chips it may differ.
Also, logical to physical mapping is not present for a floorswept gpc so
query gpc_tpc mask only upto actual gpcs that are present.
Jira NVGPU-6080
Change-Id: I84c4a3c1f256fdd1927f4365af26e9892fe91beb
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417721
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The simulator ring buffer DMA interface supports buffers of the following sizes:
4, 8, 12 and 16K. At present, it is configured to 4K and it happens to match
with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once
4K is reached. However, this is not always true; for instance, take 64K pages.
Hence, replace PAGE_SIZE with SIM_BFR_SIZE.
Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace
latter with former.
Bug 200658101
Jira NVGPU-6018
Change-Id: I83cc62b87291734015c51f3e5a98173549e065de
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728
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