The QNX compiler seems to automatically link against this library
and as such the extra -lpthread is not necessary. Instead it
causes a link failure since the pthread library is not present.
JIRA NVGPU-525
Change-Id: Id5a6fcdffb067ed961665a3ee44a9d44301b725b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722157
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Integrity already typedefs these and complains if you override them
even with the same underlying type.
Since we only use these in the regops_gk20a.h header file (outside of
the Linux specific code, that is) this patch just changes the __uXX to
uXX. With that we can delete the now unnecessary __uXX defs.
JIRA NVGPU-525
Change-Id: I01dd2723b68db2170449342f73c711ee5a589adb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721186
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Instead of referencing the header from $NVGPU/drivers/gpu/nvgpu/common
reference it from $NVGPU/drivers/gpu/nvgpu. This makes the POSIX
compilation happy since we don't do a -Idrivers/gpu/nvgpu/common.
Not sure exactly why the regular kernbel build does this but it
probably should not.
Change-Id: I00aee373b651e3b7710669fa04c5b75fc1c814d9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1727426
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The number of samples has to be at least the number of percentile ranges
(here 20) for the reporting to work as expected and also to not cause
negative indices in reading the sorted profile data. If there are not
enough samples, just report all zeroes.
Change-Id: Ie893859d95074f5ceabf6abe873941873668861d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721892
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Add below two new HALs
gops.fb.enable_hub_intr() to enable hub interrupts
gops.fb.disable_hub_intr() to disable hub interrupts
Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs
Call the HALs everywhere instead of calling the APIs directly
Jira NVGPUT-44
Change-Id: Id299c6d228733ed365a71be6b180186776cc1306
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1725977
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Regenerated the gating_reglist.c files for various
chips after fixing the script for MISRA C-2012
violations
Rule 15.5: Multiple points of exit detected
Rule 15.6: "if" body without compound statement
Rule 10.3: Implicit conversions of 64bit to 32bit int
Rule 7.2: Const must be declared with "U"
Rule 5.7: Tags with name xxx already declared
Add preprocessor conditional gaurds in
gating_reglist header files
JIRA NVGPU-671
JIRA NVGPU-656
JIRA NVGPU-688
JIRA NVGPU-686
JIRA NVGPU-644
Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Before passing in an unsigned value to abs() cast the result
of the subtraction to signed.
In Linux this happens automatically but on non-Linux platforms
abs() does not necessarily do this. clang flags this case as
a pointless operation: abs(x) obviously must equal x for any
unsigned x.
This change should hopefully preserve the Linux behavior but
avoid the compiler warning from clang.
JIRA NVGPU-525
Change-Id: I71320964c0922f1e4890c8b25d801f17e54ed3c0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724093
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The forced PRAMIN reads and writes for sysmem buffers haven't worked in
a while since the PRAMIN access code was refactored to work with
vidmem-only sgt allocs. This feature was only ever meant for testing and
debugging PRAMIN access and early dGPU support, but that is stable
enough now so just delete the broken feature instead of fixing it.
Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1723725
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On Tegra platforms that have clock management under BPMP, and do not
support Tegra DVFS, GPU driver cannot access Fmax@Vmin (get interface
always returns "0"). Added such access through BPMP DVFS shim driver.
Bug 2045903
Change-Id: I0222f2e2917cda15d18ea3296dd1fe53b2ea6b45
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722431
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As part of the MISRA fixes, moving all the
gating_reglist files to common/clock_gating dir,
the new directory structure suggested to follow.
Removed unused gating_reglist files for gk20a
JIRA NVGPU-646
Change-Id: I388855befcf991ee68eeffed10fe9ac456210649
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1722330
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gv100 cannot use idle filter values defined for
gp106 since values are different. Also gv100 cannot
use gv11b idle filter values since prod values are
different between gv100 and gv11b. Finally since
PROD values match with POR INIT values, there
is no need to init idle filters for gv100.
Bug 2115080
Change-Id: I9e7cfbde364d993ae04d80af14650739f32345cc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724060
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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-timeouts will be enabled only when timeouts_disabled_refcount
will reach 0
-timeouts_enabled debugfs will change from u32 type to file type
to avoid race enabling/disabling timeout from debugfs and ioctl
-unify setting timeouts_enabled from debugfs and ioctl
Bug 1982434
Change-Id: I54bab778f1ae533872146dfb8d80deafd2a685c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588690
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Code related to MC module is updated for handling
MISRA violations
Rule 10.1: Operands shalln't be an inappropriate
essential type.
Rule 10.3: Value of expression shalln't be assigned
to an object with a narrow essential type.
Rule 10.4: Both operands in an operator shall have
the same essential type.
Rule 14.4: Controlling if statement shall have
essentially Boolean type.
Rule 15.6: Enclose if() sequences with braces.
JIRA NVGPU-646
JIRA NVGPU-659
JIRA NVGPU-671
Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720926
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For CDE work a sync fence is always requested, but kernel does not need
it and submit flags from userspace will be passed to the submit function
in cde path so a sync fence will get created if necessary. To reduce
some complexity, remove the explicit boolean in favor of just
NVGPU_SUBMIT_FLAGS_SYNC_FENCE.
Jira NVGPU-705
Change-Id: I8aac85288513ed7cc640acd021d892cee86f41d8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1721785
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Add below new HALs for bios operations
gops.bios.devinit()
gops.bios.preos()
gops.bios.verify_devinit()
Export existing APIs gp106_bios_devinit() and gp106_bios_preos() and set them
to above HALs on gp106 and gv100
And call new HALs from gp106_bios_init() if supported instead of directly
calling APIs
Jira NVGPUT-48
Change-Id: Ic89f1c86cf6e3e0785b3663fe733b201d6f2f773
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The mechanism of posting events to userspace is OS specific.
In linux this works through poll fd, wherein we can make use
of nvgpu_cond variables to poll and trigger the corresponding
wait_queue.
The post event functionality on QNX doesn't work on poll though.
It uses iofunc_notify_trigger to post the events to the calling
process. As such QNX can't work with nvgpu_cond's.
To overcome this issue, it is proposed to create OS specific
interface function for posting clk arb events. Linux can call
nvgpu_cond based implementation, which makes sense since these
are already initialized and poll'ed in Linux specific code only.
QNX can implement this interface to call iofunc_notify_*
functions, as per its need.
Jira VQRM-3741
Change-Id: I7d9f71dae2ae7f6a09cd56662003fd1b7e50324c
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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With the removal of rcu locks and using spinlocks in place,
the usage of xchg for atomic pointer swap is unneccesary.
A few places already have barriers in place before changing
the pointer values, so a simple pointer assignment would do.
Jira VQRM-3741
Change-Id: I03296202b273b5175f166ab3e094c0e4de910eb8
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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TLC buffer sizes and credit init values do not match with
the values recommended by IAS for dGPU-Xavier configuration.
These buffer configuration values affect the latency over link.
JIRA NVLINK-158
Change-Id: I7822747cb0ae5a5efdd2d57e2104d0cb30bf9352
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686601
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist,
and optionally check host and FECS status to preempt pending load of
context not belonging to the calling channel on GR engine during context
switch.
This should be called immediately after a submit to decrease worst case
submit to start latency for high interleave channel.
There is less than 0.002% chance that the ioctl blocks up to couple
miliseconds due to race condition of FECS status changing while being read.
For GV11B it will always preempt pending load of unwanted context since
there is no chance that ioctl blocks due to race condition.
Also fix bug with host reschedule for multiple runlists which needs to
write both runlist registers.
Bug 1987640
Bug 1924808
Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549050
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Fix the following compiler errors:
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c: In function 'gp106_init_clk_support':
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:109:3: error: unknown field 'cntr' specified in initializer
cc1: warnings being treated as errors
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:109:3: error: missing braces around initializer
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:109:3: error: (near initialization for '(anonymous).<anonymous>')
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:110:3: error: unknown field 'cntr' specified in initializer
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:112:3: error: unknown field 'cntr' specified in initializer
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:115:2: error: initialized field with side-effects overwritten
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:115:2: error: (near initialization for '(anonymous).scale')
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:122:3: error: unknown field 'cntr' specified in initializer
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:122:3: error: missing braces around initializer
Not sure why this shows up for the L4T userspace compiler but not in
any other compilers.
JIRA NVGPU-525
Change-Id: I0609c1d9ad20232053768258103debadd6d9206f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720924
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This header doesn't have anything in it yet but the header is
now present. A change recently went in that only checked for
__KERNEL__ before falling back to including the QNX header.
This caused the POSIX build in GVS to attempt to include the
QNX header. The QNX src is not synced in userspace dev-kernel
tests builds resulting in a missing header.
JIRA NVGPU-525
Change-Id: I60f29ad69cbed38b6ea47f95ca504dab51fa01e7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1714083
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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For most of the builds we have in GVS userspace is 64 bits. But
it seems like at least some L4T userspace builds are either not
32 bits or have an UL that only covers 32 bits. This is seen in
GVS:
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c: In function 'gv11b_gpu_phys_addr':
/dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:273:3: error: left shift count >= width of type
make[2]: *** [/dvs/git/dirty/git-master_modular/tmake/artifacts/CommonRules.tmk:318: mm_gv11b.o] Error 1
This patch simply bumps the UL to ULL in BIT() to make sure that
we always have at least 64 bits available for the BIT() macro.
JIRA NVGPU-525
Change-Id: I67de4338afc5bee4f1fa16faee6116e0e7dbf108
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1718564
GVS: Gerrit_Virtual_Submit
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Release runlist_lock and then initiate recovery if preempt
timed out. Also do not issue preempt if ch, tsg or runlist
id is invalid. tsgid could be invalid for below call trace
gk20a_prepare_poweroff->gk20a_channel_suspend->
*_fifo_preempt_channel->*_fifo_preempt_tsg
Bug 2065990
Bug 2043838
Change-Id: Ia1e3c134f06743e1258254a4a6f7256831706185
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662656
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Migrate to the new NVLINK MINION ucode format. The new format strips out
an unnecessary ACR header from the ucode image. Moving to the new format
will allow MINION ucode generation scripts to be unified.
Bug 2113404
Change-Id: I9a72d6c3fa5edd50a4ec5eb835d157672931f994
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709986
Reviewed-by: Automatic_Commit_Validation_User
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Semaphore methods currently being used in Volta are deprecated for future chips
And on Volta we support both old and new methods
So replace old methods by new methods on Volta itself so that new methods
get tested on silicon
Implement below HALs for Volta with new semaphore methods
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer
Also use new methods in these APIs
gv11b_fifo_add_syncpt_wait_cmd()
gv11b_fifo_add_syncpt_incr_cmd()
And change corresponding APIs to reflect correct size of command buffer
gv11b_fifo_get_syncpt_wait_cmd_size()
gv11b_fifo_get_syncpt_incr_cmd_size()
Jira NVGPUT-16
Change-Id: Ia3a37cd0560ddb54761dfea9bd28c4384cd8a11c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704518
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Add below new HALs
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer
Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/
release sequence and set it to gops.fifo.add_sema_cmd()
Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size()
to return respective command buffer sizes
Jira NVGPUT-16
Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704490
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- Added vf change inject support for gv10x
- Updated clk_pmu_vf_inject() to fill required data
for pascal or volta vf change inject support
- Added new ctrl clk interface for gv10x clk domain list
- Added pmu interface for gv10x clk domain list &
vf change inject request
- Modified clk cmd, msg & RPC id's to match
with chips_a_23609936 branch
Bug 200399373
Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700746
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