Move functions related to init_ctxsw_ucode to common
falcon from gr_gk20a.c. Modified code to call this new
function and modified function names in common falcon
to reflect new re-org.
JIRA NVGPU-1881
Change-Id: I389f5c902bfbec17cdb4b16840a5ba66f6b1e331
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081331
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Created gr falcon hal unit with moving following hal functions
from gr to gr falcon:
u32 (*fecs_base_addr)(void);
u32 (*gpccs_base_addr)(void);
void (*dump_stats)(struct gk20a *g);
u32 (*fecs_ctxsw_mailbox_size)(void);
u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g);
Modified chip hals to populate these new functions and related code
now refers to gr falcon hals.
Modified kernel headers to have following defs for
fecs/gpccs base address in gm20b/gp10b/gv11b/tu104:
static inline u32 gr_fecs_irqsset_r(void);
static inline u32 gr_gpcs_gpccs_irqsset_r(void);
Created base gm20b hals for fecs/gpccs_base_addr and
removed redundant gp106 related hals.
JIRA NVGPU-1881
Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081245
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Group gr falcon init related function together during init and
gr_reset sequence. This init sequence has following functions:
gr_gk20a_init_ctxsw
gr->ops.gr.init_ctx_state
gk20a_init_gr_bind_fecs_elpg
This init sequence will be moved to common gr falcon unit.
During gk20a_gr_reset sequence, instead of separate function calls
for fecs reglist operations, switched to helper function
gk20a_init_gr_bind_fecs_elpg. Also, this call needs to be protected
with g->can_elpg setting since it involves gpmu instblk.
JIRA NVGPU-1881
Change-Id: I74542ccb5f5ffce11374d30b8d5a5cc705feed9f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081244
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Created sub-unit for ltc interrupt handling.
Following 2-hals are moved from ltc to ltc intr unit:
void (*isr)(struct gk20a *g, u32 ltc);
void (*en_illegal_compstat)(struct gk20a *g, bool enable)
Added new hal in ltc intr sub-unit for configuring ltc interrupts:
void (*configure)(struct gk20a *g);
Moved ltc interrupt related code from ltc to ltc intr unit.
Chip ltc.intr hals are populated with updated function names
created in ltc intr unit.
Converted all "unsigned int" usage to "u32" in ltc and ltc intr units
to match with hardware 32 bit register read/write.
JIRA NVGPU-3042
JIRA NVGPU-2044
Change-Id: I8684dfcc8ae343e4588b93f2b0ccde0e227635df
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081140
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Move g->ops.gr.commit_global_cb_manager() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_cb_manager()
Move hal definitions to gm20b/gp10b hal files appropriately
Add nvgpu_gr_config pointer to the parameter list of this hal so that
it does not have to dereference struct gr_gk20a in hal.gr.init unit
Jira NVGPU-2961
Change-Id: Iaff476648fa6abdf5a79be500f65a40eb90c0b08
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Move g->ops.gr.commit_global_attrib_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_attrib_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b/gv11b hal files appropriately
Jira NVGPU-2961
Change-Id: I5437a190a9e027997f63ef0e741d99e6bbebab3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077218
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Move g->ops.gr.commit_global_pagepool() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_pagepool()
Also move g->ops.gr.pagepool_default_size() hal to
g->ops.gr.init.pagepool_default_size()
Add global_ctx boolean flag as parameer to
g->ops.gr.init.commit_global_pagepool() to distinguish between
committing global pagepool v/s ctxsw pagepool buffers
Remove register header accessors from gr_gk20a_commit_global_ctx_buffers()
and move them to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Remove g->ops.gr.pagepool_default_size() hal for gv11b since gv11b can
re-use gp10b hal
Jira NVGPU-2961
Change-Id: Id532defe05edf2e5d291fec9ec1aeb5b8e33c544
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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As part of PG unit refactoring move chip specific PG code
from common/pmu/pmu_<chip_name>.c/.h files to common/pmu/pg
folder
Make new files such as pg_sw_gp106.c/.h, pg_sw_gp10b.c/.h
and pg_sw_gv11b.c/.h for PG code.
NVGPU-1973
Change-Id: I97fa2395e388559edc26be5d64bfbc547d6a3e22
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077111
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Unit test to target the interface.bsearch unit. The goal here is to
provide line coverage for the unit. Considering that the underlying
implementation is using POSIX's bsearch, there is no need to verify
the behavior of bsearch in depth.
JIRA NVGPU-2265
Change-Id: I93ec3193bb0f93aaa47aa0c6c44eca09320893ca
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078427
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Compatible VBIOS version for PG189 is .5A, but it must still boot
with VBIOS .18 and higher.
Added a vbios_compatible_version field in platform descriptor.
Do not boot if VBIOS version is < vbios_min_version.
Otherwise, warn if VBIOS version is not vbios_compatible_version.
Bug 2500899
Change-Id: Ib6be2d1da96221def7784c28f362b904ce770231
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079527
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Delete apply_ctxsw_timeout_intr ops and add
ctxsw_timeout_enable ops
Move chip specific sched_error and ctxsw_timeout
functions to hal/fifo/fifo_intr_* and hal/fifo/ctxsw_timeout_*
Add nvgpu_rc_ctxsw_timeout function under common/rc/rc.c
Do not check ctxsw timeout for channels that are no more
bound to tsg.
JIRA NVGPU-1312
Change-Id: Ide977fb60b3b72a27d9f22873f7a416c3bd1181d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075734
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timeout_ms_max is renamed as ctxsw_timeout_max_ms
timeout_debug_dump is renamed as ctxsw_timeout_debug_dump
timeout_accumulated_ms is renamed as ctxsw_timeout_accumulated_ms
timeout_gpfifo_get is renamed as ctxsw_timeout_gpfifo_get
gk20a_channel_update_and_check_timeout is renamed as
nvgpu_channel_update_and_check_ctxsw_timeout
JIRA NVGPU-1312
Change-Id: Ib5c8829c76df95817e9809e451e8c9671faba726
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076847
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common.fifo.userd unit has both safe as well as non-safe functions.
The build flag NVGPU_USERD is used to restrict the use of
non-safe functions of the userd unit in safety builds.
Jira NVGPU-2713
Change-Id: Idf3b244b24816789892ea802c2dcb42ca92649e1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075928
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Move init_gpc_mmu hal to hal.gr.init and update the
g->ops.gr.init_gpc_mmu call as g->ops.gr.init.gpc_mmu
Add new hal, pes_vsc_stream which will enable the master bit to
take floorsweep into consideration.
Modify the disable_rd_coalesce hal as su_coalesce hal and
set_rd_coalesce call as lg_coalesce hal and move to hal.gr.init
su_coalesce hal function touches only the surface read coalesce bit.
lg_coalesce hal function touches only the lg read coalesce bit.
JIRA NVGPU-2951
Change-Id: Ifc5e36f7e75d3b74142a83a3c78a9cb2b81752eb
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079532
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Introduce nvgpu_bitmap_set() and nvgpu_bitmap_clear() APIs to wrap the
bitmap_set() and bitmap_clear() APIs, respectively. The new nvgpu_*
versions accept unsigned length parameters since length is logically an
unsigned value where bitmap_set and bitmap_clear accept signed values.
We inherit bitmap_set and bitmap_clear from the OS, so we can't
directly change those.
Also, change uses of the old APIs to the new ones.
These changes resolve MISRA Rule 10.3 violations for implicit assignment
of objects of different essential or narrower type.
JIRA NVGPU-2953
Change-Id: I2c8f790049232a791f248b350c485bb07452315b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077624
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Currently SEC2/GSP uses the PMU VM space for memory access which adds
dependency on PMU, So, created separate VM space for SEC2/GSP of
size 32MB as currently used for ucode handling by these units.
SEC2/GSP VM space allocation happens if NVGPU_SUPPORT_SEC2_VM/
NVGPU_SUPPORT_GSP_VM enable flags set.
JIRA NVGPU-2910
Change-Id: I4dfe50a1c0adb7e83379bf6c15343fe57ff44c38
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077596
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Remove use of struct gk20a and struct gr_gk20a from common.gr.config
hal functions.
This requires a reference to struct gk20a *g for many nvgpu_* ops. Also,
nvgpu_gr_config is updated to include sm_count_per_tpc.
JIRA NVGPU-1884
Change-Id: I874c2b3970d97ef3940b74d8ef121a7261061670
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075681
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Create interrupt hal unit under hal.gr.intr.
This holds the interrupt and exception related hals.
Move enable_exceptions and enable_gpc_exceptions hal functions to
hal.gr.init location.
Modify enable_exceptions hal to pass gr->config and enable or disable
parameters.
Modify enable_gpc_exceptions to pass gr->config parameter.
Add new hal function enable_interrupts with enable or disable parameter
This hal helps to enable and disable the gr interrupts as needed.
gr init calls that use these hals are modified to
g->ops.gr.intr.enable_exceptions
g->ops.gr.intr.enable_gpc_exceptions
JIRA NVGPU-3016
Change-Id: Ib62f8bf0b5289b815c8eff4d32a47387f24af51b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077857
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Move g->ops.gr.commit_global_bundle_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_bundle_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Jira NVGPU-2961
Change-Id: I6358dce963857402aa1d4d5606bf75398b9be83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077216
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Move g->ops.gr.get_global_ctx_cb_buffer_size() and
g->ops.gr.get_global_ctx_pagepool_buffer_size() hals to hal.gr.init
unit
Move corresponding hal definitions to hal.gr.init unit
Jira NVGPU-2961
Change-Id: Ifff3e2073f6d9bca5b37244f7e107bad885e7ca7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077215
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Add new unit vgpu subctx under common/vgpu/gr to manage
GR subcontext. This unit provides interfaces to allocate
and free subctx header.
Rename vgpu_subctx_gv11b* files to subctx_vgpu* files
renaming functions vgpu_gv11b_alloc_subctx_header to
vgpu_alloc_subctx_header and vgpu_gv11b_free_subctx_header
to vgpu_free_subctx_header which are called only if
NVGPU_SUPPORT_TSG_SUBCONTEXTS is enabled or free_channel_ctx_header
HAL op is set which is set only for gv11b for virtualization.
Also assign fifo HAL op free_channel_ctx_header to
vgpu_channel_free_ctx_header for vgpu gv11b which in turn
calls vgpu_free_subctx_header.
Jira GVSCI-334
Change-Id: Ib46e7be911632eba01cd21881077683b795f8bad
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075872
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Moved following ltc related data to struct nvgpu_ltc
and has a reference to it from struct gk20a:
struct nvgpu_spinlock ltc_enabled_lock;
u32 max_ltc_count;
u32 ltc_count;
u32 slices_per_ltc;
u32 cacheline_size;
Added function remove_support for ltc and it is called
during nvgpu remove sequence.
Added following helper functions in ltc.h:
u32 nvgpu_ltc_get_ltc_count(struct gk20a *g);
u32 nvgpu_ltc_get_slices_per_ltc(struct gk20a *g);
u32 nvgpu_ltc_get_cacheline_size(struct gk20a *g);
Removed redudnant ltc.init_fs_state call from vgpu init
sequence since it is getting called from nvgpu_init_ltc_support.
NVGPU-2044
Change-Id: I3c256dc3866f894c38715aa2609e85bd2e5cfe5a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073417
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Remove below variables from struct gr_gk20a
u32 bundle_cb_default_size;
u32 min_gpm_fifo_depth;
u32 bundle_cb_token_limit;
u32 attrib_cb_default_size;
u32 alpha_cb_default_size;
u32 attrib_cb_gfxp_default_size;
u32 attrib_cb_gfxp_size;
u32 attrib_cb_size;
u32 alpha_cb_size;
Instead add below hals in hal.gr.init unit to get all of above sizes
u32 (*get_bundle_cb_default_size)(struct gk20a *g);
u32 (*get_min_gpm_fifo_depth)(struct gk20a *g);
u32 (*get_bundle_cb_token_limit)(struct gk20a *g);
u32 (*get_attrib_cb_default_size)(struct gk20a *g);
u32 (*get_alpha_cb_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_size)(struct gk20a *g);
u32 (*get_attrib_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_alpha_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_global_attr_cb_size)(struct gk20a *g, u32 max_tpc);
Define these hals for all gm20b/gp10b/gv11b/gv100/tu104 chips
Also add hal.gr.init support for gv100 chip
Remove all accesses to variables from struct gr_gk20a and start using
newly defined hals
Remove below hals to initialize sizes since they are no more required
g->ops.gr.bundle_cb_defaults(g);
g->ops.gr.cb_size_default(g);
g->ops.gr.calc_global_ctx_buffer_size(g);
Also remove definitions of above hals from all the chip files
Jira NVGPU-2961
Change-Id: I130b578ababf22328d68fe19df581e46aebeccc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077214
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Change the global_ctx_buffer_index member in the nvgpu_gr_ctx struct
to be an enum nvgpu_gr_global_ctx_index. global_ctx_buffer_index is
used as an array of these indicies, but had been declared as an int.
This change resolves a number of MISRA Rule 10.3 violations for implicit
assignment of objects of different essential or narrower type.
In order to use this enum, it is moved out of global_ctx.h into a new
header file ctx_common.h that can be used by both ctx.h and global_ctx.h.
JIRA NVGPU-2955
Change-Id: I5e399ba3b0821d696aa0b9909d3bc6bbe99d274c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075753
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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The POSIX definitions of U8_MAX, U16_MAX, U32_MAX, and U64_MAX in use
was causing a MISRA 10.8 violation because the value 0U was being used
as an 8-bit value per the spec. This updates the definitions to cast 0
to the appropriate bit width instead of using 0U. This eliminates the
MISRA violation.
JIRA NVGPU-2955
Change-Id: Ib3220df8c08566b4594136f8a7deb0dec8b01ab3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078364
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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As part of ACR bootstrap, falcon bootstrap request is sent to engine HAL
functions along with bootloader structure & perform falcon boot, but
this adds constraint to HAL separation due to struct parameter, so
made ACR to handle falcon boot by using falcon interfaces along with
new HAL ops to setup engine falcon setup. This also helps to reduce
code duplication too.
JIRA NVGPU-2039
Change-Id: I6ca29390b74d75bad0467a3c17623a395ec9bc25
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072940
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Make a new structure: nvgpu_pmu_pg for PG unit
- This new struct combines all PG unit variables like
elpg_stat, elpg_refcnt, pg_init etc. into one
structure as a part of PG unit refactoring.
- Use pmu_pg struct to access all PG variables.
- Eg: &pmu->pmu_pg.elpg_mutex, &pmu->pmu_pg.pg_mutex
and so on.
NVGPU-1973
Change-Id: I9973072826f4089f6315827bce49fa30dbcbcdda
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071306
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Add nvgpu_tsg_set_error_notifier function for setting error_notifier
for all channels of a tsg.
Add nvgpu_tsg_timeout_debug_dump_state function for finding if
timeout_debug_dump is set for any of the channels of a tsg.
Add nvgpu_tsg_set_timeout_accumulated_ms to set
timeout_accumulated_ms for all the channels of a tsg.
JIRA NVGPU-1312
Change-Id: Ib2daf2d462c2cf767f5a6e6fd3436abf6860091d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077626
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new hal fifo_access to control the gr_gpfifo_ctl_r register to
enable or disable the access bit and semaphore access bit.
g->ops.gr.init.fifo_access function call with true or false
parameter to enable or disable the fifo_access.
JIRA NVGPU-2951
Change-Id: I67ad7ce9f176d7ce347e8acb425f7a4bb9e088ca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
