Split handling of stalling interrupt to Linux specific chip
agnostic and OS independent chip specific parts.
Linux specific chip independent part contains handler for ISR
and passing the control to a bottom half worker. It uses the new MC
HALs intr_nonstall (query interrupt status), intr_nonstall_pause
(pause interrupts), intr_nonstall_resume (resume interrupts), and
is_intr1_pending (query per-engine interrupt bit).
MC HAL isr_nonstall is removed, because its work is now handled in
chip independent code.
JIRA NVGPU-26
Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497048
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add MC HAL is_intr1_pending. At the same time introduce nvgpu_unit
that is passed as parameter to is_intr1_pending. The API is passed
contents of intr1 register and an engine number, and returns true
if there's an interrupt pending for the engine.
JIRA NVGPU-26
Change-Id: I8e6363dd78572f8e41dbab2b258036ed168b6f75
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1497870
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Split handling of stalling interrupt to Linux specific chip
agnostic and OS independent chip specific parts.
Linux specific chip independent part contains handler for ISR
and passing the control to a bottom half. It uses the new MC HALs
intr_stall (query interrupt status), intr_pause (pause interrupts)
and intr_resume (resume interrupts).
MC HAL isr_stall now returns void and gets called in thread context
and thus remove isr_thread_stall and replace the implementation with
isr_stall.
JIRA NVGPU-26
Change-Id: I206f330f6fc4a1f4def47c5f986585ac4080216d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1480243
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add wrapper header nvgpu/types.h. It checks if build is for Linux
kernel and pulls in linux/types.h.
Delete also all #includes for linux/types.h which are not strictly
necessary, and change the remaining ones to use the new wrapper.
JIRA NVGPU-13
Change-Id: I1ddfef0b0b9d840e3e41a62f69c7cb9148d2d5fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1453371
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Clean up gk20a.c by removing direct accesses to MC and moving the
accesses to happen via MC HAL.
The chip detection logic has to violate the HAL and call gk20a
version directly, because HAL ops cannot be set up before chip has
been identified.
Change-Id: I4cdd0ef3fcf7d3b561a3fca4247a8356fe8d18e1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321576
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JIRA: EVLR-1004
(*) Refactor the non-stalling interrupt path to execute clear on the
top half, so on dGPU case processing of stalling interrupts does not
block non-stalling one.
(*) Use a worker thread to do semaphore wakeups and allow batching of
the non-stalling operations.
(*) Fix a bug where some gpus will not properly track the completion
of interrupts, preventing safe driver unloads
Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1312796
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
-Handle pbus and priv stall interrupts first.
In general critical interrupts should be
handled before any other non critical ones.
-Dump info enabled with gpu_dbg_intr if priv_ring
interrupt is flagged by fmodel.
JIRA NVGPU-25
Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1311273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move the gp10b HW headers to a new directory specially for them:
include/nvgpu/hw/gp10b
And change the code to include like so:
#include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
This is part of the process to restructure the nvgpu driver.
Bug 1799159
Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280326
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
Pascal GPU series
5) Removed hard coded engine_id logic and
made generic way
6) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156022
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Implement a helper function engine_enum_from_type. This allows
parsing device_info entries for LCE engine type.
Pascal has logical copy engine instead of CE2, so so add definition
of that.
Change-Id: I71f59c308641d84ac59fd57fc37d9b627bb07a43
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1147747
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
ce interrupts use different register mapping
and format from gk20a and gm20b.
Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/681646
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
