The gv11b and gm20b gr status reg dumps can get printed so early that
this array is null, so don't access it in that case.
Commit 946f1e6359 ("gpu: nvgpu: don't read
missing gpc_tpc_count in dump") fixed this for gp10b only.
Bug 2049965
Change-Id: I9739fd63b5a153f43000d719a5c509e3be5135cf
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1643692
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Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.
Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
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Added sw method support for SET_BES_CROP_DEBUG4.
In this sw method:
CLAMP_FP_BLEND_TO_MAXVAL forces overflow and
CLAMP_FP_BLEND_TO_INF blend results to clamp to FP maxval.
Added support for this sw method in gp10b/gp106/gv11b
and gv100.
Bug 2046636
Change-Id: I3a9e97587aca76718f7f504ea3b853f87409092a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1641529
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The idling and unidling of deterministic channels in the
do_idle/do_unidle path assume that each deterministic channel holds a
power reference. This is no longer the case if railgating has been
allowed for a channel via the deterministic options ioctl which also
causes the channel to drop the power ref that it holds otherwise during
its lifetime.
All this is happening inside the deterministic_busy rwsem, which also
guards the ioctl changing those deterministic option states.
Bug 200327089
Change-Id: I9ce312bbaa459b3cf4a7541fa369186b78c3afdc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642310
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix a race condition where we'd still be booting up the gpu and/or
initializing the driver but elsewhere assume that all is done already.
Some userspace APIs to make sure that we're ready by testing
g->gr.sw_ready, but this flag is set in the middle of bootup; there are
other things after gr initialization. Add a new flag that is enabled
after bootup is fully complete at the end of finalize_poweron, and
change the checks in user API paths to test the new flag only.
These checks are only in the ioctl paths for ctrl, dbg and tsg, and in
the ctrl device's opening path.
The gr.sw_ready flag is still left there to signify whether just gr has
had its bookkeeping initialized.
Bug 200370011
Change-Id: I2995500e06de46430d9b835de1e9d60b3f01744e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640124
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In the buddy allocator use the actual size of the PDE to determine
the pte_blk_order field which is used to determine what page size a
buddy has (or doesn't). Previously this was just set as the large
page size times 1024 which would over allocate PDE ranges for Pascal+
chips. This caused userspace, which was using the real PDE size, to
sometime allocate small and large pages in what the buddy allocator
mistakenly thought was one PDE.
Bug 200105199
Change-Id: I7ab7db7962015fc268bad61b558a18704133e1cb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639731
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Syncpoints can longer be disabled/enabled during run time as
NVGPU_HAS_SYNCPOINTS flag is set based on has_syncpoints
value in platform data during probe. Based on this, either
of syncpoint or semaphore pool is initialized.
Bug 2040115
Change-Id: Ib256e1a6ec8b1584799adb6f183fd567aebfaf13
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640380
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Enable devfreq for gv11b by enabling ""nvhost_podgov"
governor in platform data.
Reuse scaling functions from gp10b/gk20a.
Remove emc floor on railgate for power saving and make
max emc frequency as floor in rail-ungate for faster gpu boot.
Bug 2039013
Bug 200377508
Change-Id: I65ee7735202e3decbe3451157f7fc1f1f273c3ff
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639752
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Created nv_pmu_rpc_cmd & nv_pmu_rpc_msg struct, &
added member rpc under pmu_cmd & pmu_msg
- Created RPC header interface
- Created RPC desc struct & added as member to pmu payload
- Defined PMU_RPC_EXECUTE() to convert different RPC
request to make generic RPC call.
- nvgpu_pmu_rpc_execute() function to execute RPC request
by creating required RPC payload & send request to PMU
to execute.
- nvgpu_pmu_rpc_execute() function as default callback handler
for RPC if caller not provided callback
- Modified nvgpu_pmu_rpc_execute() function to include check
of RPC payload parameter.
- Modified nvgpu_pmu_cmd_post() function to handle RPC
payload request.
JIRA GPUT19X-137
Change-Id: Iac140eb6b98d6bae06a089e71c96f15068fe7e7b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613266
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add cleanup to the gk20a_probe() function since it will often fail
due to probe deferal. These "failures" cause this function to be
called multiple times and potentially allocate many resources over
and over again, leaking the old allocations.
Bug 200369627
Change-Id: Ic0bba0ae6542485135d9cb7393086e4460cd271d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640628
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-MMU_CTRL_USE_PDB_BIG_PAGE_SIZE is set to TRUE and hence
RAMIN_BIG_PAGE_SIZE should be set to 64KB i.e. val 1.
By default this is set to 128KB i.e. val 0.
-This change will also fix an issue where perfbuffer_enable and
nvgpu_init_hwpm function pass 0 as big page size while initializing
inst_block and due to which ramin_big_page_size does not get updated
to 64KB and remains set to unsupported 128KB value.
-Volta supports 64KB for big pages. Selecting 128KB for
big pages results in an UNBOUND_INSTANCE fault.
Bug 200327596
Change-Id: Ie304e4e5ff7bedaead27e9380d64c59013dd64ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639540
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Following fb iso register is not valid for gv11b but
hw headers has it. So, removing it manually from
gating register list:
0x00100D1C
Following sm blcg register not hooked up correctly
in gv11b. So, removing it manually from gating register
list:
0x00419c84
Once hw headers are updated, gating register tool will
automatically remove them from kernel code.
Bug 2042775
Change-Id: I4839b857656220566e53b66d3aead676893aaa59
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1636787
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add HAL for dumping ctxsw statistics. The statistics are dependent on
the architecture, and the function that calls this operation needs to
be moved to gk20a.
Bug 1842197
Change-Id: I285c74b8ddc8c7854c85b3fef4cbfc582098919e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1632681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Upon receiving MMU_FAULT error, MMU will forward MMU_NACK to SM
If MMU_NACK is masked out, SM will simply release the semaphores
And if semaphores are released before MMU fault is handled, user space
could see that operation as successful incorrectly
Fix this by handling SM reported MMU_NACK exception
Enable MMU_NACK reporting in gv11b_gr_set_hww_esr_report_mask
In MMU_NACK handling path, we just set the error notifier and clear
the interrupt so that the User Space sees the error as soon as
semaphores are released by SM
And MMU_FAULT handling path will take care of triggering RC recovery
anyways
Also add necessary h/w accessors for mmu_nack
Bug 2040594
Jira NVGPU-473
Change-Id: Ic925c2d3f3069016c57d177713066c29ab39dc3d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631708
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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runlist event interrupt is not needed to be enabled as
s/w polls for preemption completion for preempts issued
in RUNLIST_PREEMPT. Even though it is not enabled, intr
will get set in fifo_intr_0 status register whenever
RUNLIST_PRREMPT is successfully completed. Since intr
is disabled, fifo intr will not be triggered but it will
be handled during handling of other fifo interrupts
whenever fifo intr is triggered.
Bug 2039371
Change-Id: I0817c2b6e9f3f14958ca7c738392bc67875be5d5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1630283
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in
vgpu constants to properly dimension the virtual SM to TPC/GPC
mapping in virtualization case.
Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping.
Bug 2039676
Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631203
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Used chip specific attrib_cb_gfxp_default_size and
attrib_cb_gfxp_size buffer sizes during committing
global callback buffer when gfx preemption is requested.
These sizes are different for gv11b from gp10b.
For gp10b used smaller buffer sizes than specified
value in hw manuals as per sw requirement.
Also used gv11b specific preemption related functions:
gr_gv11b_set_ctxsw_preemption_mode
gr_gv11b_update_ctxsw_preemption_mode
This is required because preemption related buffer
sizes are different for gv11b from gp10b. More optimization
will be done as part of NVGPU-484.
Another issue fixed is: gpu va for preemption buffers
still needs to be 8 bit aligned, even though 49 bits
available now. This done because of legacy implementation
of fecs ucode.
Bug 1976694
Change-Id: I2dc923340d34d0dc5fe45419200d0cf4f53cdb23
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1635027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In case we need to re-initialize GR after floorsweeping TPC,
gp10b_ltc_init_comptags() will try to allocate comptag memory again
Skip this during re-initialization since it is unnecessary to
re-allocate all those buffers
Comptag buffer size is 33MB and reallocating causes huge memory leak
anyways
Bug 2031635
Change-Id: I935f96eb133283d6f935589c0e581e0997e980e2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1634737
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit caf168e33e.
Might be causing an intermittency in quill-c03 graphics submit. Super
weird since the only change that seems like it could affect it is the
header file update but that seems rather safe.
Bug 2044830
Change-Id: I14809d4945744193b9c2d7729ae8a516eb3e0b21
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1634349
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
