Reduce the size of memory allocations in the channel debug dump by
capturing only the necessary values from the instance block. This also
simplifies the allocation path slightly with the downside of having to
add a capture_channel_ram_dump HAL for reading the interesting parts
explicitly beforehand to the now smaller staging buffer.
Also rename struct ch_state to struct nvgpu_channel_dump_info.
Jira NVGPU-886
Change-Id: I5d7518d9d474b0b728b183383bc83d89ecf91b98
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928207
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Sometimes longer 64-bit values are composed of pairs of low and high
parts in a same nvgpu_mem. Add a function to read the two and to do the
bit ops given the low and high word offsets.
Jira NVGPU-886
Change-Id: I4fe698d7c5a891ef5740ea0fb31549195e2e6c43
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928206
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MISRA rule 18.7 doesn't allow flexible array members. To work around
that, modify the instance block member in struct ch_state to be an
explicit pointer and allocate it separately for simplicity.
Jira NVGPU-886
Change-Id: I34299bec79bf7706f9cdfa42dee7fba765c9f312
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928205
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MISRA rule 10.4 doesn't allow arithmetic conversions on operands of
different essential type category.
Fix violations where an arithmetic conversion is performed on boolean
and non-boolean types.
JIRA NVGPU-994
Change-Id: I2af9937678462b632bb6ec6178e10d02104fc3bc
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832337
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The only declaration from gr is struct nvgpu_gr_ctx and that can now be
forward-declared. Do that and remove the gr_gk20a include; add the
include to gk20a.h where it was missing.
Jira NVGPU-967
Change-Id: Idf77e7dc2ca043e9bbde9e9db03306fdd37e3c04
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822024
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Update the PD cache code to handle 64KB pages. To do this the
number of partial/full lists is expanded for when we have 64K
pages. Currently we only explicitly support 4K and 64K page
sizes. Other pages sizes (16K for example) will fail compilation
during preprocessing.
This change also cleans up the definitions for some of the
internal structs. They have been moved into pd_cache.c since
they are not used outside of pd_cache.c.
This allows the following functions to be removed from the global
context:
__nvgpu_pd_cache_alloc_direct()
__nvgpu_pd_cache_free_direct()
They have been replaced by calls to nvgpu_pd_{alloc,free}().
The nvgpu_pd_mem_entry alloc_map also had to be expanded to a
real bitmap. 32 or 64 bits is not sufficient for packing 256
byte PDs into a 64K page (there's 256 PDs per nvgpu_pd_mem_entry
in that case). To prevent doing too many find_first_zero
operations on the bitmap an 'allocs' field was also added which
tracks how many allocs are done. We can use this instead of
comparing a mask against the bitmap to determine if an
nvgpu_pd_mem_entry is full.
Note: there's still a limitation with the TLB invalidate code:
it simply assumes an nvgpu_mem is a 1 to 1 with a PDB. This means
we can't invalidate a PDB allocated at an offset greater than 0
in a nvgpu_pd_mem_entry. This in turn means we must always use a
full page size for a context's PDB.
Bug 1977822
Change-Id: I6a7a3a95b7c902bc6487cba05fde58fbc4a25da5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1718755
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in lpwr/*.c code
over to use nvgpu_memcpy() with appropriate casts applied.
Also changed the bios image table ptrs to type u8 * from u32 *
to avoid unnecessary casts (note this is consistent with other
portions of nvgpu that walk the bios image tables).
JIRA NVGPU-849
Change-Id: I61da0e26872912cf6757ff2b6136ae5ddd84c309
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936182
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in pmgr/*.c code
over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: I949f8cff49755c4cbe328ae628cf71ace18622c7
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936181
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in therm/*.c code
over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: I6ef4010d35c3f6df8a23e8c0241883481880e1c7
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936180
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in volt/*.c code
over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: Ia58f6dddfead31fdd08361a17e6a15e0f0ed29b7
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936179
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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If num_in_flight jobs is set use that to determine the proper
size of the priv_cmd_buf. If num_in_flight is not set then use
the original logic: the priv_cmd_buf is sized based on a worst
case assumption for the GPFIFO.
Also clean up MISRA issues.
Bug 2327792
Change-Id: Ie192caeb6cc48fdcac57e5cbb71c534aeaf46011
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1831095
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Instead of using num_inflight_jobs to determine whether to pre-alloc
resources for a channel use the c->deterministic flag and the
number of inflight jobs field. Non-determinsitic channels do not
require pre-alloced resources and deterministic channels with 0
in flight jobs (i.e no kernel job tracking, AKA fast path sumits)
also do not require pre-alloced resources.
Bug 2327792
Change-Id: I7e8eb0478c22e005ca2c46c555415afa0ded0be1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850123
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Import userd and gpfifo buffers from userspace if provided via
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token
(i.e., the hw channel id) to userspace.
To keep the buffers alive, store their dmabuf and attachment/sgt handles
in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for
buffers that are mainly in kernel use. The buffers are freed via a new
API in the os_channel interface.
Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the
usermode gpfifo buffer.
Bug 200145225
Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795821
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Add a mmap callback on the control device node for mapping the usermode
register region to userspace. Each such mapping is removed when the GPU
railgates, and brought back again on unrailgate.
The mapping offset must be 0 and its size must be 4 KB.
Bug 200145225
Change-Id: Ie8d3758da745b958376292691d7d1d02a24e7815
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795819
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Usermode submit needs to access the usermode region of registers from
userspace. Store the start address of register resource in struct
nvgpu_os_linux to be used in remap to userspace.
Bug 200145225
Change-Id: I3796b6bf67942af0cc16c86accb82a013032bfc8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811838
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations by renaming them
to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there
is no keyword repetition between file name and directory or
'NVGPU_HEADER-NAME' when there is repetition.
Deviate from the convention mentioned earlier in the case of clk.h.
There are two files with name clk.h. One under include/nvgpu directory
and other on in clk/ directory. Both of them will have header guards
with name NVGPU_CLK_H under the convention. Thus clk/clk.h will have
header guard with name NVGPU_CLK_CLK_H and include/nvgpu/clk will have
header guard with name NVGPU_INCLUDE_CLK_H
JIRA NVGPU-1028
Change-Id: I386d39649f39a98019a9e06bc65c8b623a43629b
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923539
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The context switch timeout works by triggering a hardware timeout at 10
Hz. When handling these, we check whether a channel has actually timed
out. Currently the timeout limit can be shorter than the 10 Hz interval
which always causes us to recover a channel but would also cause
detection of progress if there was any in the interval.
Handling both situations at the same time would reuse the channel
pointer local to the function after a loop has finished and would cause
memory corruption. Fix this by making the two branches mutually
exclusive, and move the recover case to happen first because that's how
our tests assume things to work.
Jira NVGPU-967
Change-Id: I26aa0fa7fd80ab42a9a1a93a6cca2cd29c9d3f3f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932449
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in bios.c over to
use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: I218068dd1f1f2c978ea8ab2ba230b3e5fb3da171
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936149
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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This fixes a bug where the POSIX dma module was calling malloc for
dma allocation requests with the incorrect size.
Bug found as a result of JIRA NVGPU-1235
Change-Id: Ia2933dc90f12d84a7da91a50eb3eafd6eb0e129e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930799
GVS: Gerrit_Virtual_Submit
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in hw headers
by renaming them to follow the convention, 'NVGPU_HEADER_NAME'.
JIRA NVGPU-1028
Change-Id: Ib335e3e08b5c4e0d28855e4a057c5b6aaa7a35a2
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923546
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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MISRA rule 8.2 makes it mandatory for all function prototypes
to have named parameters. There were few instances where parameter
name(s) for function prototypes were omitted. This patch will
fix the same.
JIRA NVGPU-861
Change-Id: I6cb28482becc2938c574b7d8c6f22463d346d27a
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917939
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There are two places where C standard identifiers are being
redefined. This is forbidden by MISRA rule 21.2. This patch will
fix two violations 'div' and 'exp' by renaming them 'divisor'
and 'exponent' respectively. Renamed 'man' as 'mantissa' for
uniformity.
JIRA NVGPU-1035
Change-Id: I0bbd38e5021c0047f9ce646dd6f90a30a3e4f3a5
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1852429
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MISRA rule 17.2 forbids recursion as a hazard on the stack space. To
comply and additionally to make the code somewhat more straightforward
to read, rewrite the runlist construction with three explicit functions
that work as the three levels of the earlier recursion. These levels map
to the three priority levels of TSGs and having more than that is
unlikely.
When "runlist interleaving" is enabled, TSGs with higher priorities get
interleaved between the switch of each pair of lower-level priority
TSGs, so that the latency for a job at priority level X is no more than
all jobs' timeslices of priority X and higher, plus at most one job at a
lower level.
This can be illustrated as follows (low, medium, high TSGs 1 and 2):
L1 L2 (only low-priority TSGs)
H1 H2 (only high-priority TSGs)
H1 H2 M1 H1 H2 M2 (no low-priority TSGs)
M1 M2 L1 M1 M2 L2 (no high-priority TSGs)
H1 H2 L1 H1 H2 L2 (no medium-priority TSGs)
H1 H2 M1 H1 H2 M2 H1 H2 L1 H1 H2 M1 H1 H2 M2 H1 H2 L2 (no empty levels)
Without interleaving, the items are simply grouped by priority.
Jira NVGPU-1174
Change-Id: Ic3b5106945df7105633730ecd1d150af770a5e83
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918226
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struct nvgpu_channel_sync is moved to a private header i.e.
channel_sync_priv.h present in common/sync/. All accesses to callback
functions inside the struct nvgpu_channel_sync in NVGPU driver is replaced by
the public channel_sync specific APIs.
Jira NVGPU-1093
Change-Id: I52d57b3d458993203a3ac6b160fb569effbe5a66
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929783
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Add the following public APIs.
nvgpu_channel_sync_to_semaphore
nvgpu_channel_sync_semaphore_create
struct nvgpu_channel_sync_semaphore and semaphore specific static
implementations of the channel_sync callbacks as well as
definitions of the public APIs are moved to a
separate execution unit i.e. channel_sync_semaphore.c.
Jira NVGPU-1093
Change-Id: I32c62a75ef999e8f3047e2a593f77d32cbde5646
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929781
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Add the following syncpt specific APIs
nvgpu_channel_sync_get_syncpt_id
nvgpu_channel_sync_get_syncpt_address
nvgpu_channel_sync_wait_syncpt
nvgpu_channel_sync_to_syncpt
nvgpu_channel_sync_syncpt_create
Definition of struct nvgpu_channel_sync_syncpt and syncpoint
specific static implementations of the channel_sync callbacks
as well as definitions of the public APIs are moved to a
separate execution unit i.e. channel_sync_syncpt.c
Jira NVGPU-1093
Change-Id: Ib0163c6b9bc6dfc2ab2a2b7a5fa5027be13316e2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929780
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The nvlink needs to be de-initialized as part of system
shutdown or reboot. Add the shutdown callback of pci driver
and use it to trigger nvlink de-initialization.
Bug 200422323
Change-Id: Iec8193d9665bc77ddbf3680ea130dfa4c1b3b0ad
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928821
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA Rule 9.5 requires designated initializers to be used to
initialize an array object. The size of the array shall also
be specified explicitly.
Add GP106_NUM_MEM_CONFIG to specify mem_config array size, and
use explicit indexes in the array initializer for mclk switching
scripts.
Renamed memory configuration for OEM version 12 of PG189 VBIOS
to GP106_MEM_CONFIG_GDDR5_PG419_12. Also shorten the name of
related scripts.
Jira NVGPU-891
Change-Id: Ib10786ed080f5dc415ca5ea3ccf82f6b9f3b1658
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930925
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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-On Turing, LS PMU RTOS is bootstrapped by SEC2 RTOS,
so PMU needs some time to boot & get ready to process
request as boot happened bit late in flow.
-So issue here is, code execution reaches function
gk20a_init_pstate_pmu_support() to send boardobj
commands to PMU before PMU ready to accept.
-As a result, this cause command request failure
as PMU is not ready yet due to falcon clock is
slower compared CPU clock.
-To fix issue, waiting for pmu_ready flag to become
true before staring PSTATE requests to PMU.
-pmu_ready flag will be set to true as soon as
INIT message received from PMU RTOS.
-Pre Turing-PMU RTOS will be ready much ahead of
reaching this point.
JIRA NVGPU-1150
Change-Id: I4fb5d4ca6dabc22fac34ae32880d7a1f3164e1b7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925240
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Add nvgpu_memcpy/nvgpu_memcmp which are MISRA-compliant versions
(Rule 21.15) of memcpy/memcmp.
Also convert some clk/gr calls over to use the new routines;
all of the remaining calls will be converted in subsequent patches.
JIRA NVGPU-849
Change-Id: Ib3a602cd08886764ba9a50285462a8b07bfb18ba
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1919470
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
