nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00
Code Issues Packages Projects Releases Wiki Activity
4,198 Commits 57 Branches 84 Tags
2bc421dd52f95aead2076c152d8da3bf698e3c1a
Commit Graph

174 Commits

Author SHA1 Message Date
Seshendra Gadagottu
57a75c3ba6 gpu: nvgpu: gp10b: update prod setiings 
Add/update following prod settings:
  blcg ce
  slcg ce2

Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1030986
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:11 +05:30
Seshendra Gadagottu
313fcdb1d3 gpu: nvgpu: gp10b: update thermal programming 
Add required fileds and values for thermal slow-down
settings in thermal header file and corrected
thermal register programming with correct values.

Bug 1695567

Reviewed-on: http://git-master/r/822200
(cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981)

Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/823013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
4d3f44849b gpu: nvgpu: gp10b: Report Pascal DMA copy class 
Announce supporting Pascal DMA copy class instead of Maxwell.

Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/808140
(cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7)
Reviewed-on: http://git-master/r/815679
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
9fb5c25782 gpu: nvgpu: gp10b: update slcg xbar prod settings 
Bug 1689806

Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/806115
(cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd)
Reviewed-on: http://git-master/r/805482
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
8e1c566896 gpu: nvgpu: gp10b: Always disable security in sim 
Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801850
Reviewed-on: http://git-master/r/806192
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
71afbe484f gpu: nvgpu: fuse read to boot in SECURE mode 
-Read fuse to boot in secure/production
 mode else non sercure mode.

Bug N/A

Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/791323
Reviewed-on: http://git-master/r/806191
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Sami Kiminki
95a2719059 gpu: nvgpu: Add CDE program number selection for GP10B 
Add CDE program number selection for GP10B.

Bug 1604102

Change-Id: I0054e670e3bc6b8c2380124eb58204088aaae275
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/785459
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
4b806879d5 gpu: nvgpu: gp10b: Add regops whitelists 
Add regops whitelists for gp10b. The whitelist is generated, and is the
same for context switched and global registers.

Bug 1633363

Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760935
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
a22aa6d4d3 gpu: nvgpu: gp10b: Do not set up gm20b clocks 
gm20b clock registers do not exist in gp10b. Skip setting the clock
HAL to gm20b variants.

Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
93e001d24f gpu: nvgpu: gp10b: Gating reglist 
Change-Id: I4931958c21692306d6c78bffdc45e21c553b913c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/731494
 2016-12-27 15:22:05 +05:30
Mahantesh Kumbar
0f2a1edd65 gpu: nvgpu: secure boot flag, default disabled 
- set "privsecurity" to 1 to enable secure boot else
  set to 0.

Bug 200085428

Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/729101
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:05 +05:30
Deepak Nibade
0158c38037 gpu: nvgpu: gp10b: fix sparse warnings of static symbol 
Fix sparse warnings of below type by making necessary
symbols static:

warning: symbol '<symbol>' was not declared. Should it be static?

Bug 200088648

Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2016-12-27 15:22:05 +05:30
Seshendra Gadagottu
750014be79 gpu: nvgpu: gp10b: support for replayable faults 
Add support for enabling replayable faults during
channel instance block binding. Also fixed register
programing sequence for setting channel pbdma timeout.

Bug 1587825

Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/681703
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Sam Payne
20a1ab0785 gpu: nvgpu: gp10b: add ce interrupt support 
ce interrupts use different register mapping
and format from gk20a and gm20b.

Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/681646
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:04 +05:30
Terje Bergstrom
eff1aa4d92 gpu: nvgpu: gp10b: Set correct PBDMA signature 
GPFIFO class was set to Maxwell class number. Also implement the
PBDMA signature HAL.

Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/672921
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
ea29b9e779 gpu: nvgpu: gp10b: Enable debug spew 
Change-Id: I58811bbce0e39b85074f3aa9022a730f696e407e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/679704
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
667143ed93 gpu: nvgpu: gp10b: Enable cycling through ctx bins 
Remove hard coded NETB for gp10b. This enables cycling through
available firmware files.

Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/676557
Reviewed-by: Peng Du <pdu@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:03 +05:30
Mahantesh Kumbar
5452d16154 gpu: nvgpu: gp10b: gpmu elpg support 
Temporally used gm20b elpg sequencing values for gp10b elpg.

Bug 1525971

Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/662517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
1f11c7ffe7 gpu: nvgpu: gp10b: Add new supported kind 
Bug 1567274

Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606931
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
c23f7708ac gpu: nvgpu: gp10b: Define physical address width 
GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.

Bug 1567274

Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
7918de1c1b gpu: nvgpu: gp10b: Implement L2 query 
Bug 1567274

Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/602858
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
317e7bb758 gpu: nvgpu: gp10b: Fill class numbers 
Fill class numbers to characteristics structure.

Bug 1567274

Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/594404
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
0b50f2a202 gpu: nvgpu: Implement gp10b intr processing 
Bug 1567274

Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/591628
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Kenneth Adams
16c511220e gpu: nvgpu: t18x, gp10b framework 
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.

Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30