This change eliminates MISRA Advisory Rule 18.4 violations in the
following cases:
* nvgpu_submit_append_gpfifo_user_direct()
* nvgpu_submit_append_gpfifo_common()
- use array-indexing to access gpfifo entry lists
* gv11b_gr_intr_record_sm_error_state()
- use array-indexing to access sm_error_states table
Advisory Rule 18.4 states that the +, -, +=, and -= operators should
not be applied to an expression of pointer type.
JIRA NVGPU-3798
Change-Id: I736930e4ba09a88888b0ef48f62496c4082ea5a1
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210173
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Change nvgpu_finalize_poweron() to call the subunit init functions by
using a table. The table is local to nvgpu_finalize_poweron() since the
function pointers are stored at runtime in the gk20a struct during HAL
init. The table also includes a field for checking an enable flag before
calling the init op, if required.
The primary motivation for this change is to reduce CCM for
nvgpu_finalize_poweron(). This change reduced the TCC metric from 40 to
10.
The init unit test is disabled until it can be updated to match the new
design.
JIRA NVGPU-3980
Change-Id: Ic93d3fdd185cc7feb883c898284e15b251277a8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202974
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Remove the second parameter for the nvgpu_bios_sw_init()
function so the function only requires the gk20a object. The
g->bios was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Id70e2b6b3a9b2705815591d02730d2d2620771c0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202972
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Remove the second parameter for the nvgpu_init_sec2_setup_sw()
function so the function only requires the gk20a object. The
g->sec2 was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.
JIRA NVGPU-3980
Change-Id: I22f526d961da44da64d563f5f3136c62cf9f4adf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202970
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Remove the second parameter for the pmu_early_init() and pmu_init()
functions so they only require the gk20a object. The g->pmu was always
passed for this parameter. And this makes the API signature match the
other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Iae9361a5f14bc5c1d02f4ddb6583f30b71b22d59
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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This change eliminates MISRA Advisory Rule 18.4
violations in the following by accessing g->fifo.channel
with array indexing:
* nvgpu_channel_init_support()
* nvgpu_channel_semaphore_wakeup()
Advisory Rule 18.4 states that the +, -, +=, and -=
operators should not be applied to an expression
of pointer type.
JIRA NVGPU-3798
Change-Id: I6b1bf360db6ec25894cc0ea430c33067e0cddf64
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207550
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The correct config to be used is CONFIG_NVGPU_SW_SEMAPHORE and not
CONFIG_NVGPU_SW_SEMAPHPORE.
Due to this the s/w semaphores were not getting freed.
Bug 200542024
Change-Id: I5eee0d52f0c1116e68a304b94e01fd407e74526e
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207182
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Improve the code complexity for the rbtree function delete_fixup().
Create smaller functions, delete_fixup_right_child() and
delete_left_child() to handle those parts of the agorithm. Also, create
helper function has_no_red_children() to handle a common check in these
new functions.
This brings the TCC metric to 7.
JIRA NVGPU-4094
Change-Id: If34167be308093ae3b597e02bbd3da8b4e9d27aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205844
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Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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nvgpu_kzalloc can fail in gv11b_init_eng_method_buffers.
Added checks on returned pointer.
Also changed g->ops.tsg.init_eng_method_buffers to return an int,
and check return value in callers.
Jira NVGPU-3788
Change-Id: Icb541665c40b89d512929cc9cf9f6a3e7a0033db
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205851
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Currently after sending change seq RPC, nvgpu waits for a fixed time
of 20ms.
This CL replaces this with pmu_wait_message_cond, which will return
immediately after getting change seq completion event.
Also added debug fs node to get the change seq execution time.
Bug 200545366
Change-Id: Iba283f65d4949858be9cbff88de4d21a8c92ff81
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202423
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Add doxygen documentation for private GR structures defined in:
gr/gr_config_priv.h
gr/gr_falcon_priv.h
gr/gr_intr_priv.h
gr/gr_priv.h
Remove "p_va" field from struct nvgpu_ctxsw_ucode_info since it is
unused.
Compile out "pm_ctxsw_image_size" with flag CONFIG_NVGPU_DEBUGGER.
Compile out "preempt_image_size" with flag CONFIG_NVGPU_GRAPHICS.
Replace eUcodeHandshakeInitComplete enum value by macro
FALCON_UCODE_HANDSHAKE_INIT_COMPLETE. And remove enum value
eUcodeHandshakeMethodFinished since it is unused.
Compile "ctxsw_disable_mutex" and "ctxsw_disable_count" in struct
nvgpu_gr only if CONFIG_NVGPU_RECOVERY or CONFIG_NVGPU_DEBUGGER is
defined
Jira NVGPU-4028
Change-Id: Ie8769c1f3f8d313b479b182d3858a6715d49cd4c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201373
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Add doxygen documentation for private GR structures defined in:
gr/ctx_priv.h
gr/global_ctx_priv.h
gr/obj_ctx_priv.h
gr/subctx_priv.h
Compile out struct zcull_ctx_desc with flag CONFIG_NVGPU_GRAPHICS.
Compile out struct pm_ctx_desc with flag CONFIG_NVGPU_DEBUGGER.
Compile out field golden_img_loaded with flag CONFIG_NVGPU_NON_FUSA
since it is only used for VSERVER.
Jira NVGPU-4028
Change-Id: Ic63e751ee28c6b645cc13993b16f701a9dbcf3e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201372
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Some methods are implemented in SW, and it is expected that
nvgpu driver gets illegal method interrupts for these.
Do not report illegal method error if related method could
be handled. It avoids reporting false errors to 3LSS and
more importantly avoids entering SW quiesce state.
Jira NVGPU-3896
Change-Id: I1e6ddcf20e4038398259d22957619fe7bc2e9c7d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199906
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GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.
Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.
This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled
Bug 200289214
Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
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