Commit Graph

27 Commits

Author SHA1 Message Date
Ramesh Mylavarapu
98e6f68ccf Revert "Revert "nvgpu: gpu: Add boardobj class_ids to all units""
This reverts commit 29179624564c7fe538fef89708fd1b54a6e612ba.

Change-Id: Ic3dca94106cfea0c77cff07597545c4d6c8166c0
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194823
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2020-12-15 14:05:52 -06:00
Prabhu Kuttiyam
53a58c9bb4 Revert "nvgpu: gpu: Add boardobj class_ids to all units"
This reverts commit 0d3a489de0fbb67fb70a7431b6073f248384f6cf.

Change-Id: I23bda44bf6e933d5c2f62ec025c48eb76215857a
Signed-off-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194528
Reviewed-by: Akshatha Somayaji <asomayaji@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
2020-12-15 14:05:52 -06:00
rmylavarapu
5756924a8b nvgpu: gpu: Add boardobj class_ids to all units
- Class_ids of all the units has been changed in safety
PMU ucode, this CL will have the updated class_ids of all
units.
NVGPU-4007

Change-Id: Ic109b5140840da64f903be6b3de88c5d948b3d1c
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191523
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2020-12-15 14:05:52 -06:00
Abdul Salam
3ee12f5370 gpu: nvgpu: Use cached VF table for target voltage instead of RPC
Nvgpu uses RPC to get target voltage for a freq, though this gets
the latest Voltage, there could be mismatch b/w data in nvgpu & PMU.
To make it consistent, use the local VF table for getting the voltage.
Also the slave ratio calculation is inaccurate due to quantization.
So instead of calculating, use the slave ratio from parsed vbios table.

Bug 200545403

Change-Id: Ibb064f2a0f5eba77166e2b3f9868da9e3fcc7193
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2183546
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2019-08-27 01:00:53 -07:00
rmylavarapu
28af1331c8 gpu: nvgpu: Change clk load command to RPC
- Added RPC infra for clock domain load from cmd.

NVGPU-3731

Change-Id: Id5240ad83d1a67ff77e9c61b5673e7eb4c22cff1
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153109
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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2019-07-29 05:28:20 -07:00
rmylavarapu
fdccc426d2 gpu: nvgpu: Clock domain board_objs for chips_a fw
Added support for clk_mon structures in clk_domain boardobj set
interface.

NVGPU-3731

Change-Id: If98dd6c8c91efcc3564a308f144af631f87db21d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153107
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2019-07-29 05:27:54 -07:00
rmylavarapu
ebc0b3b381 gpu: nvgpu: Remove hardcoding related to Psate objs
In P4 #25076323, we have done many hard codings in PMU
which are related to Pstate board objs. As we are sending
Pstate objs now we can remove those hardcoding in NVGPU.

NVGPU-3597

Change-Id: I8b35e6b34c71721bb84fde9ffc280cf748232dbf
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131350
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2019-06-12 00:46:42 -07:00
Abdul Salam
84a6d4e656 gpu: nvgpu: Add support for Vmax from get_status
This patch does the following
1. Get the Vmax from get_status.
2. Compare the Vmax with voltage requested to pmu.
3. Make sure requested voltage is always less that Vmax.
4. Add maximum_voltage to expose this value via sysfs.

Bug 200454682

Change-Id: I1135f387d852a13ae435b4a665a7394ed5ed762f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129500
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2019-06-04 01:15:55 -07:00
Divya Singhatwaria
20fcf813dd gpu: nvgpu: Use sw ops for BIOS
Some functions are not accessing hardware directly
but are being called using HAL ops: For example

.init = gv100_bios_init,
.preos_wait_for_halt = gv100_bios_preos_wait_for_halt,
.preos_reload_check = gv100_bios_preos_reload_check,
.devinit = gp106_bios_devinit,
.preos = gp106_bios_preos,
.verify_devinit = NULL,

This was being called as:
g->ops.bios.init(g)
g->ops.bios.preos_wait_for_halt(g)
g->ops.bios.preos_reload_check(g)
g->ops.bios.preos(g)
g->ops.bios.devinit(g)
g->ops.bios.verify_devinit(g)

Change the function access by using sw ops, like:
Create new function: nvgpu_bios_sw_init()
and based on hardware chip call the chip specific
bios sw init function: nvgpu_gv100_bios_sw_init()
and nvgpu_tu104_bios_sw_init()to assign the sw
ops

JIRA NVGPU-2071

Change-Id: Ibfcd9b225a7bc184737abdd94c2e54190fcd90a0
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108526
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2019-05-28 02:05:43 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
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2019-05-23 00:56:55 -07:00
rmylavarapu
5ed6909d07 gpu: nvgpu: Fix MISRA violations in clk_domain unit
Fixed following MISRA violations:
-MISRA C-2012 Rule 11.3
-MISRA C-2012 Rule 16.1

NVGPU-3222

Change-Id: I9dcb6c5c3fab6be0135919dfbcf273f7ee44949b
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107418
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-05-06 04:05:25 -07:00
Nicolas Benech
3a3d78adf2 gpu: nvgpu: fix MISRA 17.7 in nvgpu.common.pmu.clk*
MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the nvgpu.common.pmu.clk.* units.

JIRA NVGPU-3035

Change-Id: I13863f43c6bea76917978a12df091a672a3e5098
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108887
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2019-05-01 10:05:03 -07:00
Abdul Salam
bc10ef568e gpu: nvgpu: Restructure boardobjgrpmask unit
This patch does the following for boardobjgrpmask unit.
1. Remove unused functions and its pointers.
2. Append public functions with nvgpu.
3. Remove unnecessary inclusion of header files.
4. Make local functions as static.
5. Rename function names to increase readibility.
6. Remove boardobj* from static functions.

Jira NVGPU-1977

Change-Id: Ie6d3bd8f55784d29ae4ba720fb3998487ad2b942
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107167
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2019-04-29 11:04:46 -07:00
rmylavarapu
be0eabeb6c gpu:nvgpu: Move nvgpu_clk_pmupstate into nvgpu_pmu
Moved nvgpu_clk_pmupstate structure from gk20a to
nvgpu_pmu.The aim is to have single pmu structure inside
gk20a, that is "nvgpu_pmu" struct and all the global
structures of all units in PMU should be included in
"nvgpu_pmu" struct.

NVGPU-3220

Change-Id: I531aab568a692c55e640ca2c33aa7508b83a9593
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104129
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2019-04-26 02:55:02 -07:00
rmylavarapu
6e67eec8d5 gpu:nvgpu: Restructure P-state unit
Description:
Present p-state unit handle both pstate boardobj and
initializing all the units. As part of restructuring,
the pstate unit is separated into two units:
1) Perf_pstate: This unit will handle pstate boardobjs.
2) Pmu_pstate: This unit will initialize all the units
which supoort performance states.

Changes:
1) Created pmu_pstate unit.
2) Pstate boardobjs are moved under perf_pstate which
is under perf unit.

NVGPU-1958

Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096339
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2019-04-23 07:14:09 -07:00
Sagar Kamble
bcbc87dc2e gpu: nvgpu: move pmu interface headers to include/nvgpu/pmu
Interface header files for PMU features are now moved under PMU header
files directory include/nvgpu/pmu. And fix bulk of coding style issues.
Update header file names and guards.

JIRA NVGPU-1971

Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093006
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2019-04-13 12:33:52 -07:00
Sagar Kamble
16953b9622 gpu: nvgpu: prepare pmu command unit
pmu_ipc.c had functionality for rpc response handling and message cond
checks. This patch moves them to msg unit. And prepare cmd.h to group
together structs and functions related PMU commands.

JIRA NVGPU-1970

Change-Id: Iec5d72d02ab3ee51963631c828b301c56af8dc48
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079146
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2019-04-05 05:06:22 -07:00
Sagar Kamble
499da418c1 gpu: nvgpu: prepare pmu sequences unit
PMU commands and messages management is based on sharing the data
through sequences. Functions for sending commands/allocating
payload update sequence data acquiring lock and those for
working on received messages read/free the sequence data
releasing lock.

JIRA NVGPU-1970

Change-Id: I4204dbfbf6f57b0f5a7016aed74ffea6e91ab06c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079141
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2019-04-05 05:05:11 -07:00
Sagar Kamble
2250ccbe35 gpu: nvgpu: remove seq_desc parameter of pmu callbacks
This parameter isn't used by the callbacks and plan is to keep
access to sequence struct members within IPC units.

JIRA NVGPU-1970

Change-Id: Idcdf4e8f493386be38a5c8a63a741ac06ce1b06e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079140
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2019-04-05 05:04:56 -07:00
Sagar Kamble
817e8f28c1 gpu: nvgpu: remove unneeded seq_desc and msg parameter of *_pmu_cmd_post functions
These parameters are not required. Removing those will simplify the
refactoring of the IPC units.

JIRA NVGPU-1970

Change-Id: Id381ba18b87ea21860c05cad1fa64dad8e1a59a1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079139
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2019-04-05 05:04:46 -07:00
rmylavarapu
6177eacc71 gpu: nvgpu: Restructure clk_domain unit
Changes: 
1) Removed PSTATE30 code.
2) Whitespace clean-up.

NVGPU-1962

Change-Id: I258ba5b5711c642de4ec9af98f08c02ff6c45efc
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078148
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2019-04-02 03:28:48 -07:00
rmylavarapu
722fe30d50 gpu: nvgpu: Restructure clk unit
Description:
nvgpu_clk_pmupstate is the global structure in clk units. It is declared
in clk.h and all clk units will include clk.h header.
nvgpu_clk_pmupstate struct will have structure pointers to all clk units
and will include genereic function pointers which are  used by most clk
units. The reason why the function pointers is defined in this sturct,
and not included inside g->ops is because, these are only clk specific
functions and rest of the driver code is not dependent on this.

Each unit will have init function to allocate memory for its structure
and will initialize its local functions.

Changes:
1) Introduced nvgpu_clk_pmupstate in clk.h file. All the changes needed
   to call the above struct from individual clk units.
2) Removed cyclic dependency headers in clk units by calling function
   through pointers defined in clk.h.
3) Initialization of each unit is done in respective unit instead of
   doing it in clk unit. Added *_init_pmupstate and *_free_pmupstate to
   individual clk units.
4) Each unit clean up will be done separately while refactoring that
   unit.

NVGPU-1963
NVGPU-2965

Change-Id: Iee79d7a812b62407252636057b104f952c94a229
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033537
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2019-03-29 05:34:26 -07:00
rmylavarapu
8daafcbae8 gpu: nvgpu: Restructuring clk.h into different units
Changes:
1) Separated clk.h which is in /nvgpu/include/pmu
 into different units
2) Renamed global functions

Intention: At present /nvgpu/include/pmu/clk.h
consists of structures and functions of different
clock units. It is difficult to work on individual
clk units if this file is not separated into
individual units. All stucts and functions in clk.h
are seperated into different clk units.
Individual private clk units were not touched.
Post this patch, the sebsequent patches would make
changes in the individual clk units.

NVGPU-2707

Change-Id: I7bf9fab38a73bceb451291530a67c70ed343b0cb
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021704
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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2019-02-19 01:55:54 -08:00
Philip Elcan
99ed40b7fb gpu: nvgpu: clk: fix MISRA 10.3 issues for size_t
MISRA Rule 10.3 prohibits implicit casting of objects to a different
type. This change addresses a number of MISRA 10.3 violations in
clk_domain.c where size_t values were being implicitly cast to u16.

JIRA NVGPU-1008

Change-Id: If2dc6c6a288fe4b16425a210bc6d76bbef2ce019
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001224
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2019-01-23 13:55:12 -08:00
Philip Elcan
2cff6844fb gpu: nvgpu: clk: use explicit BIT32 macro
Use the BIT32() macro to create 32 bit values when assigning to a u32.
This avoids MISRA 10.3 violations for assigning different types to a
u32.

JIRA NVGPU-1008

Change-Id: I0b50c3cf476737d38c943ecc12c4f17f9ba9ddb8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001223
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2019-01-23 13:55:08 -08:00
Philip Elcan
968db82a65 gpu: nvgpu: clk: fix incorrect casts in returns
Remove the u32 casting for return values in functions whose return type
is int.

JIRA NVGPU-1008

Change-Id: I87d4e3a4f8530f45b59a1f612180b295c5238b28
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001222
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2019-01-23 13:55:04 -08:00
Terje Bergstrom
dce78f7332 gpu: nvgpu: Move PMU code to common/pmu
Move code interfacing with PMU tasks to common/pmu.

JIRA NVGPU-961

Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950991
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-10 20:09:55 -08:00