Remove posting of events using old channel event API i.e.
gk20a_channel_post_event()
Also, update gk20a_channel_semaphore_wakeup() to post
events when called from ce2_nonblockpipe_isr()
Bug 200089620
Change-Id: I677cdab11183a649663ff9272a527c63b9994430
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1112275
(cherry picked from commit 4840efda393cd5928f1a8463db8b52cc586860bc)
Reviewed-on: http://git-master/r/1120289
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
fix below sparse warning :
drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol
'gr_gp10b_pre_process_sm_exception' was not declared. Should it be
static?
Bug 200088648
Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1009938
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
While posting CILP preemption complete event to
user space, raise the event to all channels of TSG
(if channel is part of TSG)
This is a WAR until we have proper sync mechanism
with user space to raise CILP events
Bug 200156699
Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1001696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add CILP support for gp10b by defining below function
pointers (with detailed explanation)
pre_process_sm_exception()
- for CILP enabled channels, get the mask of errors
- if we need to broadcast the stop_trigger, suspend all SMs
- otherwise suspend only current SM
- clear hww_global_esr values in h/w
- gr_gp10b_set_cilp_preempt_pending()
- get ctx_id
- using sideband method, program FECS to generate
interrupt on next ctxsw
- disable and preempt the channel/TSG
- set cilp_preempt_pending = true
- clear single step mode
- resume current SM
handle_fecs_error()
- we get ctxsw_intr1 upon next ctxsw
- clear this interrupt
- get handle of channel on which we first
triggered SM exception
- gr_gp10b_clear_cilp_preempt_pending()
- set cilp_preempt_pending = false
- send events to channel and debug session fd
Bug 200156699
Change-Id: Ia765db47e68fb968fada6409609af505c079df53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/925897
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
gr_*__set_alpha_circular_buffer_size() left max_batches field of
gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta
transitions and poor performance when tessellation or geometry
shaders are used
Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/840079
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Some of the allocated buffers are used during normal graphics
processing. Mark them as GPU cacheable to improve performance.
Bug 1695718
Change-Id: I71d5d1538516e966526abe5e38a557776321597f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/827087
(cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed)
Reviewed-on: http://git-master/r/828493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value
written in gk20a_init_gr_setup_hw() instead of hard coding here.
Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/813959
We used to allocate 1.5x buffer size. This leads to memory waste, as
we do not set the CB size via SW methods anymore.
Bug 1686189
Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801865
(cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2)
Reviewed-on: http://git-master/r/815683
Spill buffer size is in chunks of 256B. Multiply the size by
granularity to get the size in bytes.
Bug 1686189
Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801344
(cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0)
Reviewed-on: http://git-master/r/815680
If pagepool size equals max we should use zero. Add the comparison
to do that.
Bug 1686189
Change-Id: I15bd43663550b1089a726c0256b89f849c193e21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801526
(cherry picked from commit 9d89ea5ba345b19d2cff86130ba9d3c4c5f07e6e)
Reviewed-on: http://git-master/r/815681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
We program the default steady state beta CB size. The default is
for deep binning, but we've disabled deep binning. As result steady
state CB size was left too high.
Bug 1683535
Change-Id: I17029078d9c83e55eec6faacfc83c6d812f8c3c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/795306
Reviewed-on: http://git-master/r/806189
Alpha and beta sizes need to be clipped to a maximum value. For
alpha CB we were using beta size in clipping, and for both we were
not using number of TPCs to determine the max value.
Change-Id: I0c925464ba4c9f575e6e59dd5ba7759aa1cb6381
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752667
Reviewed-by: Automatic_Commit_Validation_User
Some fields have different widths, so duplicate the code to program
global bundle CB.
Change-Id: Ib6af5abf3e90dfa1bcda2fbc6b97ad1031e6ab16
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752635
When allocating betacb for a GfxP channel, add both alpha and beta
cb sizes together.
Change-Id: I8cef62f6272bfb3b5e9a3835a51590e5eb91dc92
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752633
Reviewed-by: Automatic_Commit_Validation_User
ZBC is safe to update and GPU is safe to rail gate when units are
in preempted or empty state. Idle may never be reached in case of
graphics preemption, so relax the ZBC update wait condition.
Bug 1640378
Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/745655
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
If betacb size has been given via debugfs, use that instead of the
calculated number.
Bug 1628352
Change-Id: I8c68c27a2bfdd7f013776734ef846377a89b0033
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/733332
Add a missing bitmask for clearing existing bits before setting a new
value, and shift the value the correct amount. Also format register
needs to be rounded down.
Bug 200087330
Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/726265
Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Program steady state CB size to be the HW default.
Bug 1626065
Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/725106
Move the fifo engine activity disabling and wait-for-idle from the
lowest-level functions higher, into the ioctl path of zbc operations, so
that the sw initialization path wouldn't call them. During the init
path, the disable isn't necessary, and the code path could result in a
deadlock in the fifo runlist mutex.
Change-Id: I56e73204e288331165358fc9856390f1eb724488
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/715196
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
