MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all remaining offending uses of memcpy()
in acr/* and vbios/* over to use nvgpu_memcpy() with appropriate
casts applied.
JIRA NVGPU-849
Change-Id: I30ec9481c1418289a8664bdb4ef5be7833218179
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941260
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in netlist/*
code over to use nvgpu_memcpy() with appropriate casts applied.
Also changed the type of the memcpy src variable from u32 * to
u8 * to avoid unnecessary casts.
JIRA NVGPU-849
Change-Id: I442596d6405ac543edc3d26c1367ed37fd02941c
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941259
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in pmu/*
over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: I8f66b3a271fdab3e5cfb625a9c9ccc56bf272182
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941258
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in mm/*
over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: I17be87475fde62e969b014d4d0fa455dae5d4373
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941257
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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This adds casts to eliminate MISRA 10.3 violations for implicit
assignments of values to different essential types. If values could
potentially not fit into the cast, they are checked before the cast
to ensure the value does not change. If possible, an error is
returned; otherwise, call BUG()/BUG_ON().
Change-Id: I14d0ef74bf3dfe62a8fb04ac4047f46c1bf9fcd4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930157
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When ACR and PMU BL fail to boot, the firmware are releasd, but the
firmware pointers are not re-initialized. That causes later invalid
pointer usage. Fix that by setting them as NULL.
Bug 200462464
Change-Id: Iacdf4b3c7f7144a77f595c77e6f5a29d35505672
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941671
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in GPU specific files.
JIRA NVGPU-1036
Change-Id: Iefadc38bdbea4f02de3c24b6ad1c71d6eb0af4bd
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929903
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in clk/*
and gp106/mclk* over to use nvgpu_memcpy() with appropriate
casts applied.
JIRA NVGPU-849
Change-Id: I21d3a8bed762adad64abf0b0bfc58d743a104cbb
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939866
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pmuif structures refer to the ctrl structures, so that means that ctrl
structures are part of the pmuif. Move the headers to the right place
and update all include statements to include from the right place.
JIRA NVGPU-596
Change-Id: I7be1a727be654d58eccd0e12d599979687dd0733
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1934022
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in volt.
JIRA NVGPU-1036
Change-Id: I68cb0de47721c21d31468a811d809d1538f9515a
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929907
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in power-related files.
JIRA NVGPU-1036
Change-Id: I6b9f2fa6f3cbf5f746a0e8499d3e8962d4781fe3
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929905
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in PMU files.
JIRA NVGPU-1036
Change-Id: Ie189acf13007f79a1046e8723cdec5b878d4ccc4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929904
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in common code.
JIRA NVGPU-1036
Change-Id: Id6dea92df371e71b22b54cd7a521fc22812f9b69
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929899
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I9e18ffc961d485225732c34d3ca561e84d182d07
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921370
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in therm.
JIRA NVGPU-1036
Change-Id: If6c8ef1f88c922f417e53fe446853587a65583e9
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929906
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in clk files.
JIRA NVGPU-1036
Change-Id: Ie5979d44b2b02cb9899add031989042edb28df80
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929902
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Posix interface.
JIRA NVGPU-1036
Change-Id: I2da417edc992f16de24cdff536c0538f1fde8b61
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Linux interface.
JIRA NVGPU-1036
Change-Id: I39b20f1d0e1a1da56d452f2c3d5ee049666cefe8
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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All the netlist parsing code is currently under GR unit, but netlist
ucode parsing does not really have any logical dependency to GR
Hence separate out a new unit common/netlist/ that parses the netlist
image and stores/exposes its content through netlist_vars structure
Structure nvgpu_netlist_vars is added to structure gk20a
Move netlist parsing code to common/netlist/netlist.c and chip
specific files to common/netlist/netlist_<chip>.c
Move simulation netlist parsing to common/netlist/netlist_sim.c
Rename g.ops.gr_ctx HAL to g.ops.netlist
Rename all the exported structures to be in the form of nvgpu_*
Rename all exported functions to be in the form of nvgpu_netlist_*()
Add netlist initialization to GPU boot path, and add deinitialization
to GPU remove path
Jira NVGPU-1317
Change-Id: I9af86e3b3230a89db5260cc8ed96ff5f72938c9a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936454
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In gk20a/gr_ctx_gk20a.c we right now directly read the GR register
gr_fecs_ctx_state_store_major_rev_id_r() which adds the dependency
to GR h/w header
Add a new HAL g.ops.gr.get_fecs_ctx_state_store_major_rev_id() to
read this register and use this instead
Also remove h/w header from gr_ctx_gk20a.c
Jira NVGPU-1317
Change-Id: Iab64fbfacff4d7ce4f3b61ca90b00ddc77e29551
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936453
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-Modifed volt policy construct to support of
type SINGLE_RAIL in volt_volt_policy_construct()
-Modified volt_get_volt_policy_table() to fetch
single rail data from bios table to construct
SINGLE_RAIL volt policy.
-Added volt_construct_volt_policy_single_rail() to construct
single rail volt policy boardobj needed for tu10x & PS3.5
JIRA NVGPU-1156
Change-Id: I495e005e46ee08a7851a317869bb5bc3f5f9a97e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921473
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-Add support for volt device OPERATION_TYPE_IPC_VMIN
support
-Added defines required for ipc vmin operation support
-Modified volt_get_voltage_device_table_1x_psv()
to add check to support IPC_VMIN & assign pwm source
based on operation type.
JIRA NVGPU-1156
Change-Id: Ia168669ea6b5896916747fccde8c6a52c271c4e3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921395
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- In vGPU code path, function vgpu_channel_abort_cleanup() does not
obtain channel reference before using the channel structure
(channel_gk20a)
- vgpu_channel_abort_cleanup() is called by vgpu_intr_thread() which
runs commands obtained from interrupt queue from RM server.
- If there is a scenario where gk20a_channel_release() function runs
before guest receives notification from RM server to abort channel
cleanup, channel gets freed before vgpu_channel_abort_cleanup() runs.
- However, because vgpu_channel_abort_cleanup() does not take explicit
reference to the channel, it ends up accessing structures
(such as ch->g) which are set to NULL and thus we end up in a crash.
- This patch explicitly takes reference of channel before
vgpu_channel_abort_cleanup() is called.
- If gk20a_channel_release() runs before vgpu_channel_abort_cleanup()
and ends up freeing channel, we dont get reference to freed
channel in vgpu_channel_abort_cleanup() and thus we return from
function rather than continuing with freed channel as was the case
previously.
Bug 200453473
JIRA EVLR-3411
Change-Id: I311043b2231336616b28246531cf8a0dc151b0cd
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932028
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in acr code
over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: Ib7bac9353cf69c402f8925927c84d4ae7ecbe49d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939422
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches all offending uses of memcpy() in pmu_perf/*.c
code over to use nvgpu_memcpy() with appropriate casts applied.
JIRA NVGPU-849
Change-Id: Iac5e0b1d460f094e950dd4e34e9ccf6a5b0a9edc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939421
Reviewed-by: Automatic_Commit_Validation_User
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Fix some mistakes from commit 0fbc1a2652 (gpu: nvgpu: avoid recursion in
runlist construction) and commit 998bf379df (gpu: nvgpu: add
runlist_append_tsg) for MISRA rules 10.3 and 10.4.
- cast a sizeof to u32 in a calculation to match in size,
- make the NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* constants unsigned to make
comparisons match in signedness.
Jira NVGPU-1174
Change-Id: I00aa9758ca4352d8eb53a0e8ded42a1ba3b14561
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938069
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Reduce the size of memory allocations in the channel debug dump by
capturing only the necessary values from the instance block. This also
simplifies the allocation path slightly with the downside of having to
add a capture_channel_ram_dump HAL for reading the interesting parts
explicitly beforehand to the now smaller staging buffer.
Also rename struct ch_state to struct nvgpu_channel_dump_info.
Jira NVGPU-886
Change-Id: I5d7518d9d474b0b728b183383bc83d89ecf91b98
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928207
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Sometimes longer 64-bit values are composed of pairs of low and high
parts in a same nvgpu_mem. Add a function to read the two and to do the
bit ops given the low and high word offsets.
Jira NVGPU-886
Change-Id: I4fe698d7c5a891ef5740ea0fb31549195e2e6c43
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928206
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MISRA rule 18.7 doesn't allow flexible array members. To work around
that, modify the instance block member in struct ch_state to be an
explicit pointer and allocate it separately for simplicity.
Jira NVGPU-886
Change-Id: I34299bec79bf7706f9cdfa42dee7fba765c9f312
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928205
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MISRA rule 10.4 doesn't allow arithmetic conversions on operands of
different essential type category.
Fix violations where an arithmetic conversion is performed on boolean
and non-boolean types.
JIRA NVGPU-994
Change-Id: I2af9937678462b632bb6ec6178e10d02104fc3bc
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832337
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The only declaration from gr is struct nvgpu_gr_ctx and that can now be
forward-declared. Do that and remove the gr_gk20a include; add the
include to gk20a.h where it was missing.
Jira NVGPU-967
Change-Id: Idf77e7dc2ca043e9bbde9e9db03306fdd37e3c04
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822024
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