Commit Graph

2177 Commits

Author SHA1 Message Date
Seema Khowala
3c3f947cf4 gpu: nvgpu: add fifo ops for *data_fault_id_enum_v
generated hw header for top_device_info_data_fault_id_enum_v
is different between legacy chips and t19x

JIRA GV11B-7

Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-02 08:53:38 -08:00
Seema Khowala
0aafa9e279 gpu: nvgpu: gm20b: add gr ops for load tpc mask
gr_fe_tpc_fs_r addr is different for t19x

Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1310326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 08:53:32 -08:00
Deepak Nibade
64e1782aee gpu: nvgpu: optimize duplicate buffer lookup in case of fixed offsets
In gk20a_vm_map_duplicate_locked(), we always do a linear search
in rb-tree to find a duplicate entry of the buffer

In case NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET is set, we first
traverse whole rb-tree linearly and then compare offset_align
with the address searched from rb-tree

If size of rb-tree is very large this linear lookup takes upto
7mS and causes huge delays

Hence in case of NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET, we can
use offset_align to perform a binary search on rb-tree and then
verify that dmabuf and kind match with the node obtained from
the search
This saves a lot of time per-lookup

Bug 1874516

Change-Id: Ia4924b64d66e586c14341ae2e2283beac394bf6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1309343
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 07:53:55 -08:00
Thomas Fleury
09504cdbc3 gpu: nvgpu: remove clock domain aliases
Remove MCLK and GPCCLK domain aliases, now that userspace
has swithed to new enumerations.

Jira DNVGPU-211

Change-Id: I2af2fd67dbed47088d7161ba0605e13dd7c674a5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1292609
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
2017-03-02 02:03:35 -08:00
Seema Khowala
0a3e5941ff gpu: nvgpu: add pbdma and eng bitmask for runlists
-Init pbdma and engine bit mask per runlist.
-Organize debug info to print supported pbdma instances
 for particular runlist.

JIRA GV11B-3

Change-Id: Ie34dd98ccbe2c779ca1c795855c2a7df4abd2715
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1309706
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-27 10:13:22 -08:00
Thomas Fleury
ac8cea9351 gpu: nvgpu: ignore set preempt mode to default
In native case, attempting to set graphics/compute preempt mode
to default is ignored if preemption mode has already been set
for the context. In virtualized case an error is currently
returned.
Align behaviour for native and virtualized case, by ignoring
such request.

Bug 200186530

Change-Id: Ieb3a37107bdbd3284804ee9fd392786409224082
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1306506
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-24 12:14:17 -08:00
Deepak Goyal
45303a7de5 gpu: nvgpu: pmu: make gp106_pmu_reset() public.
secure PMU reset i.e. gp106_pmu_reset() is changed
to a non-static function, so that it can be re-used
outside gp106 scope.

Change-Id: I7d4c4ec6ca1bd315bf8c681723fb350277103c3b
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-02-23 21:33:34 -08:00
Deepak Goyal
d6e40fc07a nvgpu: gpu: pmu: Use pmu ops to call pmu_reset().
In this patch hard coded function calls for PMU
reset are replaced by PMU ops.

Change-Id: I266c43e3540163a133895244dcf91169116812f5
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303757
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-23 21:33:33 -08:00
Mahantesh Kumbar
9c68af58a9 gpu: nvgpu: ACR interface headers reorganization
-Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to
Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/”
Folder.

- nvgpu_acr.h - Top-level header-file which include ACR interfaces
headers & defines required to communicate with ACR, including this
header file is good to get access into ACR interface & made changes
accordingly,

-Deleted acr.h & acr_t18x.h as not required anymore
& removed its include from dependent files.

Jira NVGPU-19

Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-23 01:04:48 -08:00
Deepak Nibade
8cdb91c527 gpu: nvgpu: remove use of DEFINE_MUTEX()
API DEFINE_MUTEX() is defined in Linux and might
not be available in other OSs.
Hence remove its usage from nvgpu

Declare and explicitly initialize below mutexes
for both nvgpu and vgpu
g->mm.priv_lock
g->mm.tlb_lock

Jira NVGPU-13

Change-Id: If72885a6da0227a1552303206172f1f2b751471d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1298042
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-22 04:15:08 -08:00
Deepak Nibade
8ee3aa4b31 gpu: nvgpu: use common nvgpu mutex/spinlock APIs
Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>

Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()

And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>

Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h

Jira NVGPU-13

Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-22 04:15:02 -08:00
Deepak Nibade
1f855af63f gpu: nvgpu: add mutex and spinlock abstraction files
Add new abstraction file <nvgpu/lock.h> for all mutex,
spinlock and raw_spinlock operations.

Add linux specific file <nvgpu/lock_linux.h>
which implements linux specific operations for above

Jira NVGPU-13

Change-Id: Idab96aa8bf949d6a92ea0edc9f40e90fca401ea4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293186
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2017-02-22 04:14:57 -08:00
Deepak Nibade
76611c4268 gpu: nvgpu: remove use of mutex_is_locked()
mutex_is_locked() API is defined on Linux only
and not on other OS like QNX.

Hence remove use of this API for OS abstraction
support to nvgpu.

Instead of using mutex_is_locked(), use
mutex_trylock() for same purpose

Jira NVGPU-13

Change-Id: I542daf20a2294153da8e8bfe89e0dc0387297523
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1297184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-22 04:14:57 -08:00
Alex Waterman
e99a3dec3a gpu: nvgpu: Disable IRQs only if enabled
In the PCI init/de-init code only disable IRQs if they were enabled.
The enable happens in the common power_on code. The PCI routines could
both be called without the common power_on code being called which
causes an extra disable to happen.

Bug 200275531

Change-Id: I43a8a9881f1e9ae254bf36230f29849df074657f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1301701
(cherry picked from commit cca70e9adccee1ef65a0a6d95a4494fc87500c17)
Reviewed-on: http://git-master/r/1298954
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-21 20:42:49 -08:00
Konsta Holtta
00ba4c0b0b gpu: nvgpu: assign ce_ctx->vm during ctx creation
Commit 7e403974d3 ("gpu: nvgpu: Simplify
ref-counting on VMs") accidentally broke the CE context creation while
moving away from direct ch->vm assignments. ce_ctx->vm isn't part of
that simplification, so initialize it because it's used elsewhere and
were left NULL.

Bug 1846718

Change-Id: I6219880227b881d2175005b7eaf6e6e08a6f888e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1306221
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-21 11:13:42 -08:00
Terje Bergstrom
c218fefe84 gpu: nvgpu: Fix unicast register accesses for SM
In two places we used broadcast register as base, but added the
unicast offset to it. This causes the write to go well beyond
valid register range.

Change the broadcast base to use unicast base instead in sequence
to resume a single SM and to record error state of SM.

Bug 200256272

Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c)
Reviewed-on: http://git-master/r/1306331
Reviewed-by: Automatic_Commit_Validation_User
2017-02-17 15:30:58 -08:00
Terje Bergstrom
4b8edeffe5 gpu: nvgpu: Prune gp106 clock gating list
Further prune registers that do not exist on gp106 that were not
caught by previous patch.

Bug 200256272

Change-Id: Ic8d6835d8726d850860d680dd1807e8020010a29
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit c1c9029b9b851652d7b62a96373d7c1636f3ad89)
Reviewed-on: http://git-master/r/1306330
Reviewed-by: Automatic_Commit_Validation_User
2017-02-17 15:30:58 -08:00
Terje Bergstrom
6a58857b65 gpu: nvgpu: Remove almost all gm204/gm206 support
Remove gm204/gm206 support. It was used only in the interim until
Pascal cards were available, and we don't maintain that code anymore.

This patch leaves only BIOS code.

Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302224
GVS: Gerrit_Virtual_Submit
2017-02-17 13:46:32 -08:00
Terje Bergstrom
53465def64 gpu: nvgpu: Generalize BIOS code
Most of BIOS parsing code is not specific to any particular GPU. Move
most of the code to generic files, and leave only chip specific parts
dealing with microcontroller boot into chip specific files.

As most of the parsing is generic, they do not need to be called via
HALs so remove the HALs and change the calls into direct function
calls.

All definitions meant to be used outside BIOS code itself are now in
<nvgpu/bios.h>

Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302222
GVS: Gerrit_Virtual_Submit
2017-02-17 13:46:32 -08:00
Richard Zhao
29a79e6b80 gpu: nvgpu: vgpu: set ch timeout value to 5s
It couldn't be zero, since it won't enable wdt.

JIRA VFND-3450

Change-Id: I9f6ab37bd438923596406a085603c70dcb83d46a
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1292715
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-17 13:46:13 -08:00
Mahantesh Kumbar
a9e1a6c70a gpu: nvgpu: Remove ACR gm204/gm206 support
- Remove ACR gm204/gm206 support as no more support
required Maxwell dGPU.
-Moved required ACR interface to gp106 from gm206
-Deleted acr_gm206.c/h files & removed its involvement
from dependent files.

Change-Id: I9cb7ce8f7ef8bb6fcc7515e644ffb11b774389f4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304556
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-15 19:33:29 -08:00
Mahantesh Kumbar
d465504534 gpu: nvgpu: Remove PMU gm204/gm206 support
-Created new methods for PMU gp106 whichever dependent
on gm206.
-Deleted pmu_gm206.c/h files & removed its involvement
from dependent files.

Change-Id: Ic578da53bff362efb3e142962275227787206233
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304492
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-15 19:33:28 -08:00
Peter Boonstoppel
907adfd785 gpu: nvgpu: Add NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTX
This ioctl can be used on gp10b to set a flag in the context header
indicating this context should be run at elevated clock
frequency. FECS ctxsw ucode will read this flag as part of the context
switch and will request higher GPU clock frequencies from BPMP for the
duration of the context execution.

Bug 1819874

Change-Id: I84bf580923d95585095716d49cea24e58c9440ed
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1292746
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-14 14:54:46 -08:00
Peter Boonstoppel
4fb3161ba3 gpu: nvgpu: Pull latest gp10b headers
HWCL 38000754

Bug 1819874

Change-Id: Ic28bd2abee4caac83c2d21b035a64558d72aa0fa
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1301674
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-14 14:54:41 -08:00
Aparna Das
28b0d6cfa8 gpu: nvgpu: remove call to invalidate tlb
Guest doesn't explicitly send command to the RM server
to invalidate tlb which is done implicitly when mapping
or unmapping buffer. Remove support for this call.

Bug 1665111

Change-Id: Icf2edae7feffa35b1dbf87c227b3e98b506e6519
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: http://git-master/r/1287728
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-14 11:15:27 -08:00
Alex Waterman
e7a0c0ae8b gpu: nvgpu: Move from gk20a_ to nvgpu_ in semaphore code
Change the prefix in the semaphore code to 'nvgpu_' since this code
is global to all chips.

Bug 1799159

Change-Id: Ic1f3e13428882019e5d1f547acfe95271cc10da5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284628
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
2017-02-13 18:15:03 -08:00
Alex Waterman
aa36d3786a gpu: nvgpu: Organize semaphore_gk20a.[ch]
Move semaphore_gk20a.c drivers/gpu/nvgpu/common/ since the semaphore
code is common to all chips.

Move the semaphore_gk20a.h header file to drivers/gpu/nvgpu/include/nvgpu
and rename it to semaphore.h. Also update all places where the header
is inluced to use the new path.

This revealed an odd location for the enum gk20a_mem_rw_flag. This should
be in the mm headers. As a result many places that did not need anything
semaphore related had to include the semaphore header file. Fixing this
oddity allowed the semaphore include to be removed from many C files that
did not need it.

Bug 1799159

Change-Id: Ie017219acf34c4c481747323b9f3ac33e76e064c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284627
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-13 18:14:45 -08:00
Alex Waterman
b9194a1c33 gpu: nvgpu: Organize nvgpu_common.[ch]
Move nvgpu_common.c to drivers/gpu/nvgpu/common since it is a common
C file to all drivers.

Similarly move nvgpu_common.h to drivers/gpu/nvgpu/include/nvgpu since
this follows the new include guidelines.

Bug 1799159

Change-Id: I00ebed289973b27704c2cff073526e36505bf699
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284612
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
2017-02-13 18:14:34 -08:00
Terje Bergstrom
ed35f0a404 gpu: nvgpu: Add enable/disable shadow ROM HAL
Add HAL for enabling and disabling shadow ROM. This removes XVE dependency
from bios code.

Change-Id: Icafec72dae71669376bbfb97077661b7165badb8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302223
2017-02-13 09:43:09 -08:00
Alex Waterman
9af5105749 gpu: nvgpu: Update missing copyright headers
Some copyright updates have been missed in the header files. This patch
takes care of updating those copyrights.

Bug 1799159

Change-Id: Ie51111a5da5fb1eb12aabe69dc00bfb7caea5aba
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1293354
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-10 11:58:10 -08:00
Alex Waterman
cf0ef133e6 gpu: nvgpu: Move kmem_caches to allocator
Instead of using a single static kmem_cache for each type of
data structure the allocators may want to allocate each
allocator now has its own instance of the kmem_cache. This is
done so that each GPU driver instance can accurately track how
much memory it is using.

In order to support this on older kernels a new NVGPU API has
been made,

  nvgpu_kmem_cache_create(struct gk20a *g, size_t size)

To handle the possibility that caches cannot be created with
the same name.

This patch also fixes numerous places where kfree() was wrongly
used to free kmem_cache allocs.

Bug 1799159
Bug 1823380

Change-Id: Id674f9a5445fde3f95db65ad6bf3ea990444603d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283826
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-10 11:57:31 -08:00
Alex Waterman
24e8ee192a gpu: nvgpu: Fix call to wrong free function
Fix a mistake in which the wrong free call is used.

Bug 1799159
Bug 1823380

Change-Id: I3b60949cabbdb6b4d193c6687657cad606462687
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283142
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-10 11:57:31 -08:00
Alex Waterman
c891fc81ad gpu: nvgpu: Make sure struct is specified
Make sure that struct class is at least forward declared so that
inclusing nvgpu_common.h can be done from anywhere with no dependencies.

Bug 1799159
Bug 1823380

Change-Id: Id8feaa5fd456f7a6e12ed85360d5df28f308faa4
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-10 11:57:30 -08:00
Mahantesh Kumbar
3885fe099a gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpu
Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder
to support cross platform feature implementation.

Made changes to files which accessed “include pmuif/*” to reflect
pmuif/* movement changes.

Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files.

Jira NVGPU-19

Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1299823
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-10 09:43:46 -08:00
Shardar Shariff Md
8da422ac57 gpu: nvgpu: use upstream function to get chipid
Use upstream function tegra_get_chip_id and chip id macros,
as downstream function tegra_get_chipid() and chip_id macros
is going to be deprecated.

This is done as a part to removing duplicate code.

Change-Id: I846384955e983a36af0b3501d2b23c47e1d0798c
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1299873
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-10 05:09:36 -08:00
Mahantesh Kumbar
35980eac09 gpu: nvgpu: Delete PMU fecs override interface
Deleted PMU fecs override interface from pmu_api.h
header file as feature not used anymore
& its dependent code too.

Deleted file pmu_api.h as file dont
have any interfaces left inside

Jira NVGPU-19

Change-Id: I490cf67ae60ce2f1de37da063199ee04835b940d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297370
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-09 13:44:31 -08:00
Mahantesh Kumbar
8afd83238a gpu: nvgpu: PMU ACR interface header reorg
Moved ACR interface from pmu_api.h to
gpmuif_acr.h header file

gpmuif_acr.h - PMU Command/Message Interfaces for
Access Control Region (ACR)

Jira NVGPU-19

Change-Id: Ic37ff3f4ca069aa4bdd6729bbfccc00e15185b02
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297369
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-09 13:44:31 -08:00
Mahantesh Kumbar
de2dfd0c1e gpu: nvgpu: PMU perfmon interface header reorg
Moved perfmon interface from
pmu_api.h & pmu_gk20a.h to gpmuif_perfmon.h
header files

gpmuif_perfmon.h - PMU Command/Message Interfaces
PERFMON

Jira NVGPU-19

Change-Id: I983f89f0f6ec3b889d975178fb1405f166b7d1b9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297262
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-09 13:44:31 -08:00
Mahantesh Kumbar
2caa3a9361 gpu: nvgpu: PMU PG interface headers reorg
Moved Power Gating (PG) interface from
pmu_api.h & pmu_gk20a.h to gpmuif_ap/pg
header files.

gpmuif_pg.h - PMU Command/Message Interfaces
for power gating (PG)

gpmuif_ap.h - PMU Command/Message Interfaces
for Adaptive Power

Jira NVGPU-19

Change-Id: I1eeee78bdf89d894f9a4731435cdb121f73b1e0f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297203
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-09 13:44:31 -08:00
Seema Khowala
e4a17d6379 gpu: nvgpu: gp10b: removed static keyword
Removed static keyword for t19x usage
-int gp10b_tegra_get_clocks(struct device *dev);
-int gp10b_tegra_reset_assert(struct device *dev);
-int gp10b_tegra_reset_deassert(struct device *dev);

JIRA GV11B-34

Change-Id: I0bcb02db431b3a11f1b0e40776698c5dd3a9703d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1296847
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-09 11:24:25 -08:00
David Nieto
7324301751 gpu: nvgpu: enable PCI MSI interrupts
Use MSI interrupts instead of legacy on PCIe
dGPUs to reduce latency and contention with other
PCIe devices

JIRA EVLR-986

Change-Id: I6cecc7e62e5797860d42a5bee21e8f4f664e1b18
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1291758
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-08 11:32:24 -08:00
Laxman Dewangan
27dd1ce475 gpu: nvgpu: gp10b: Use T186 POWER DOMAIN macros
The driver file gp10b/platform_gp10b_tegra.c is compiled for
T186 SOCs and hence use the T186 power domain macros directly
instead of legacy TEGRA_POWERGATE_* macros.

This helps in kernel unification to not define the TEGRA_POWERGATE_*

bug 200257351

Change-Id: I955c5dd11e6deaaf537377beb6e67a58ab7787ab
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1300524
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-08 04:34:11 -08:00
Laxman Dewangan
8264681bb6 gpu: nvgpu: gk20a: Remove inclusion of unused header
The driver file includes <linux/tegra-powergate.h> but does
not use anything from this header.

Remove this unnecessarily inclusion of header file.

bug 200257351

Change-Id: Idc9c79bfdcad0081b1121ec746fcc7a70306adf5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1300555
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-08 03:25:52 -08:00
Mahantesh Kumbar
4d64bd9637 gpu: nvgpu: fix broken dev-kernel TOT
pmu_common.h still referred in gpmuifpmgr.h file
causing TOT build failure

Jira NVGPU-19

Change-Id: Ie387cdd2f3d2294b0b6b390abfcb2d89dbd322fb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1301218
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
2017-02-08 03:07:47 -08:00
Mahantesh Kumbar
8522004c00 gpu: nvgpu: Falcon-controller interface update
Moved falcon-controller common interface code
from pmu_common.h to flcnif_cmn.h file.
Interfaces are common for falcons irrespective
of F/W on falcon controllers

Jira NVGPU-19

Change-Id: Iad11b2fade8cf6716888773b2b1c23919cbcc07b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-07 21:53:44 -08:00
Mahantesh Kumbar
02190c7597 gpu: nvgpu: PMU interface headers reorganization
Moved PMU/Falcon interface which are present
in pmu_gk20a.h & pmu_common.h to new files
as per feature

nvgpu_gpmu_cmdif.h - Top-level header-file that defines
the command/message interfaces used to communicate with PMU

gpmuif_pmu.h - PMU Command/Message init interfaces

gpmuif_cmn.h - Common definitions used by interfaces

Jira NVGPU-19

Change-Id: Id8ea6075e4dbba7697036951dcb85487eb861710
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296415
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-02-07 21:53:39 -08:00
Srikar Srimath Tirumala
3335ff9fe9 gpu: nvgpu: add support for EMC freq scaling
Add support to do EMC frequency scaling via bwmgr on T210 K4.4.

Bug 200267304

Change-Id: Ib01f1a256cfceefc5551e128b7ba8953fafe21d3
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1285001
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
2017-02-07 16:04:39 -08:00
seshendra Gadagottu
521253acb7 gpu: nvgpu: implement chip specific init_elcg_mode
Added function pointer to implement chip specific
init_elcg mode and updated this pointer for legacy chips.

JIRA GV11B-58

Change-Id: I3fff4f771eaa5dad98a3d8166c9127ecd6b745e4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1300120
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-07 15:16:59 -08:00
Alex Waterman
8c3dddd81f gpu: nvgpu: Fix more pmu circular dependencies
Similar to patch 67fc462989 fix
more circular dependencies arising from #include'ing gk20a.h
for no apparent reason.

Bug 200192125

Coverity ID 2011397
Coverity ID 2011398

Change-Id: I75bcb3e4e66b680498b0e20d645ab9543aae6697
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1296947
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-07 14:54:02 -08:00
Alex Waterman
c6594c744d gpu: nvgpu: Remove ref count from as_share
Remove the broke ref counting from as_share. The ref-count is
incremented for every bind channel but never decremented. This
results in VMs never being freed.

Bug 1846718

Change-Id: I6253b3eab7c7471d3ed6feddb3705c49a8704bed
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1296900
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-07 14:54:02 -08:00