ifdef function prototypes with CONFIG_* defines. This fixes MISRA rule
8.6 violations which complain about undefined functions.
Also moved nvgpu_channel_get_from_file prototype to ioctl_channel.h &
nvgpu_probe to driver_common.h as those are linux specific. Define
nvgpu_init_soc_vars in posix/soc.c as it is implemented in QNX.
JIRA NVGPU-3873
Change-Id: I5d2b238e1b5d1318867cd2416ac5f03cc6ab7c6a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196794
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In some cases, we would get deadlock issue due to there are two locks
acquisition on common clk driver's lock and nvgpu driver's locks. At
the bug, inconsistent lock ordering problem will come with one thread
gets "nvgpu lock -> clk lock" and the other thread gets "clk lock ->
nvgpu lock".
Slove the latter path with one-time initializing clk_parent entry
and use cached data afterward.
Bug 2555115
Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8
Signed-off-by: Jeremy Ho <jeremyh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146727
(cherry picked from commit 42c2bdfb9f)
Reviewed-on: https://git-master.nvidia.com/r/2160290
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Use uintptr_t for for pointer arithmmatic instead of char *
to fix following CERT-C violations.
cert_exp36_c_violation: Pointer "char *" is more strictly aligned
than pointer "struct gk20a_event_id_data_rmos const *".
cert_exp36_c_violation: Pointer "struct nvgpu_clk_dev_rmos *" is
more strictly aligned than pointer "char *".
JIRA NVGPU-3908
JIRA NVGPU-3561
Change-Id: I9d40b3337ed0ddaf172ad4f4c9dd319996d479a1
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197151
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add safety checks to validate precision of unsigned types.
These validations are used to justify that no security issues
exist in NvGPU driver due to CERT-C INT34-C and INT35-C
violations.
These are done early in the driver probe to ensure that
code violating CERT-C INT34-C and INT35-C rules is not run
before these checks.
JIRA NVGPU-3908
JIRA NVGPU-3561
Change-Id: Iffb8e21935d16f31c52af909689c334bc120cf7c
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195033
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Remove const from __mptr declaration to fix EXP40-C violation.
cert_exp40_c_violation: Casting pointer "__mptr" with type
"struct nvgpu_clk_dev const *" to type "char *" allows an
object defined with a const-qualified type to be modified
through use of an lvalue with non-const-qualified type
Considering implementation of container_of() a const is
not required.
JIRA NVGPU-3908
JIRA NVGPU-3561
Change-Id: Ie94c3f994a962124afcda49a178a72c9b87ba7c7
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195032
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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gr config is allocated and initialized as part of gr_init_setup_sw().
The sw setup is done before gr_init_setup_hw() where sm id table
is initialized. This makes the gr_config == NULL check redundant.
Fix the coverity issue (dereference before null check) by removing
the redundant check.
JIRA NVGPU-4026
Change-Id: I16a8700ff5fee524c2e32e75b621e74c59c8e44f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199360
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add doxygen documentation for gr/gr_falcon.h header
Also move below functions under appropriate compile time flag:
- nvgpu_gr_falcon_get_pm_ctxsw_image_size() under CONFIG_NVGPU_DEBUGGER
- nvgpu_gr_falcon_get_preempt_image_size() under CONFIG_NVGPU_GRAPHICS
- nvgpu_gr_falcon_get_fecs_mutex() under CONFIG_NVGPU_ENGINE_RESET
- nvgpu_gr_falcon_bind_fecs_elpg() under CONFIG_NVGPU_POWER_PG
Also remove CONFIG_NVGPU_GRAPHICS flag used for falcon methods related
to ELPG. Use CONFIG_NVGPU_POWER_PG instead.
Jira NVGPU-4028
Change-Id: I8b93b786a2fca90998e6c1204e0a17843bc577b0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197148
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This patch fixes the below misra violation.
kernel/nvgpu/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b_fusa.c:209
Checker: MISRA C-2012 Rule 10.7 (Required)
kernel/nvgpu/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b_fusa.c:209:
1. misra_c_2012_rule_10_7_violation: The width of the composite
expression "1U << 0U + active_eng_id * 1U" (8 bits) is less that the
left hand operand "ctxsw_timeout_engines" (32 bits).
Jira NVGPU-3881
Change-Id: I4b48ee224a014734d55d24d0c5865eda26d5b920
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196114
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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Rename gr register space allocation and deallocation functions
to test_gr_init_setup and test_gr_remove_setup
Add tests to support following functions
nvgpu_gr_init
nvgpu_gr_init_support
nvgpu_gr_suspend
nvgpu_gr_remove_support
Jira NVGPU-3970
Change-Id: I11418ddcb9946ef75de162fd5689fdbbbfb62e79
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194612
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Do some doxygen cleanup for the whitelisting macros:
- Previously doxygen documentation was being generated for the no-op
whitelisting macros. Enable the NV_IS_COVERITY define in the
doxygen build. This generates doxygen documentation for the actual
whitelisting macros.
- Create a doxygen group for the whitelisting macros. This adds
additional documentation for the whitelisting macros.
- Add doxygen line breaks
JIRA NVGPU-3820
Change-Id: Id452147a3a909da7981303d0908f2aff4a2ff86b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194711
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Whitelisting changes for tmake are set at the top level in
tmake/umbrella/parts.tmk. The change in drivers/gpu/nvgpu/Makefile.tmk
is unnecessary. Therefore, the nvgpu change is being removed.
JIRA NVGPU-3820
Change-Id: I2053e69759df0d3dbf58b209a957d9227c1ebb40
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193805
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reduce code complexity of gr falcon unit functions.
Rewrite the gm20b_gr_falcon_check_ctx_opcode_success and
gm20b_gr_falcon_check_ctx_opcode_failure function to use
gm20b_gr_falcon_check_ctx_opcode_status.
Reduce complexity of gm20b_gr_falcon_check_ctx_opcode_status function
by using following sub functions
gm20b_gr_falcon_check_valid_gr_opcode
gm20b_gr_falcon_gr_opcode_equal
gm20b_gr_falcon_gr_opcode_not_equal
gm20b_gr_falcon_gr_opcode_and
gm20b_gr_falcon_gr_opcode_less
gm20b_gr_falcon_gr_opcode_less_equal
Jira NVGPU-3975
Change-Id: I9dc6330e175e5200643dbfe177716cfd3df2d5c1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Some of the debugger and graphics specific functions were already
not being used in safety build. Compile out their definitions
and declarations as well.
Also, fail preemption set call if non-zero graphics preemption mode
is requested in safety build.
Jira NVGPU-3967
Change-Id: Iaf5e3bd58e6096da40301b79e9295a6c5893cd4a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191764
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Reduced MCC for nvgpu_netlist_init_ctx_vars_fw from 11 to 9 using
following helper function:
nvgpu_netlist_is_valid: MCC 3 TCC 3
Reduced TCC for nvgpu_netlist_init_ctx_vars_fw from 46 to 9 using
following helper functions:
nvgpu_netlist_handle_region_id : MCC 10 TCC 10
nvgpu_netlist_handle_ucode_region_id : MCC 2 TCC 5
nvgpu_netlist_handle_sw_bundles_region_id: MCC 2 TCC 7
nvgpu_netlist_handle_generic_region_id: MCC 2 TCC 5
nvgpu_netlist_handle_debugger_region_id: MCC 2 TCC 23
nvgpu_netlist_handle_debugger_region_id is not enabled for safety build
so higher TCC can be ignored.
JIRA NVGPU-3976
Change-Id: I38516b50642dd8c72aafc8795d9d336bb1bb1771
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192959
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Move gr_init_prepare to separate gr unit test
Use of global register spaces between two different
gr unit tests corrupt the memory in multi thread support.
Add support for local register spaces with pre initialized
register values for each gr unit test.
Jira NVGPU-3582
Change-Id: I4e47c1ca4f312335cd33a73a377f9fa9f12ccd5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189502
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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