Commit Graph

11 Commits

Author SHA1 Message Date
Konsta Holtta
d6730d5214 gpu: nvgpu: gp10x: add support for vidmem in page tables
Modify page table updates to take an aperture flag (up until
gk20a_locked_gmmu_map()), don't hard-assume sysmem and propagate it to
hardware.

Jira DNVGPU-76

Change-Id: I797fdaaf5f42a84fa0446577359147fb6908a720
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1169295
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:26:18 +05:30
Terje Bergstrom
ae893b37c0 gpu: nvgpu: gp10b: Use sysmem aperture for SoC memory
In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it
has to be accessed as sysmem.

Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1122591
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
2016-12-27 15:22:12 +05:30
Terje Bergstrom
be7ee41989 gpu: nvgpu: gp10b: Sync with register generator
Use re-generated register definitions. This synchronizes
kernel with the register generator.

Change-Id: I5ad34ad0b92327091758a2d10581a1b4170fa919
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120811
2016-12-27 15:22:11 +05:30
Terje Bergstrom
6a071e5ad5 gpu: nvgpu: gp10b: Implement priv pages
Implement support for privileged pages. Use them for kernel allocated buffers.

Change-Id: I24778c2b6063b6bc8a4bfd9d97fa6de01d49569a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/761920
2016-12-27 15:22:06 +05:30
Terje Bergstrom
94a7c5ff2c gpu: nvgpu: gp10b: Fix PDE/PTE address handling
We were dropping the part of address that span word bounary. The register
generator does not know how to real with multi-word fields, to edit things
in manually.

Bug 1646531

Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/747468
2016-12-27 15:22:05 +05:30
Terje Bergstrom
ac0cd782ab gpu: nvgpu: gp10b: Implement new page table format
Implement the 5-level Pascal page table format. It is enabled
only for simulation.

Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/682114
2016-12-27 15:22:05 +05:30
Terje Bergstrom
1f11c7ffe7 gpu: nvgpu: gp10b: Add new supported kind
Bug 1567274

Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606931
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:02 +05:30
Terje Bergstrom
23a4456260 gpu: nvgpu: gp10b: Add SM debug registers
Add SM debug registers to gp10b, and regenerate headers.

Bug 1567274

Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592646
2016-12-27 15:22:02 +05:30
Terje Bergstrom
07b7a534fa gpu: nvgpu: Synchronize gp10b headers with gm20b
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.

Bug 1567274

Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:02 +05:30
Adeel Raza
1f3b9d851a gpu: nvgpu: headers for linsim CL 33759297
Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5
Signed-off-by: Adeel Raza <araza@nvidia.com>
2016-12-27 15:22:02 +05:30
Ken Adams
dfdd5ba3cb gpu: nvgpu: gp10b headers
first cut.  just to get started...

Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/447753
2016-12-27 15:22:01 +05:30