Scott Long
3c7cf8b75a
gpu: nvgpu: fix MISRA 10.5 issue in timeout code
...
This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2155617
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2019-07-24 17:04:38 -07:00
Vaibhav Kachore
e8c53b4e81
Revert "Revert "gpu: nvgpu: Improve accuracy of dGPU clk measurement""
...
This reverts commit ffda24df36 .
Bug 2637525
Bug 200530176
Change-Id: I542e51ea340f344768f9a3a090164964372fb5d2
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2148174
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2019-07-24 10:16:30 -07:00
ajesh
4249359aa9
gpu: nvgpu: fix CERTC violation in timers unit
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INT31-C requires that integer conversions do not result in lost or
misinterpreted data.
Fix violation of INT31-C in timers unit.
Jira NVGPU-3605
Change-Id: Ia145e3bf814bd16d48a0f1fbbf8e62d73d08c98c
Signed-off-by: ajesh <akv@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2152240
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2019-07-12 11:26:12 -07:00
Abdul Salam
ffda24df36
Revert "gpu: nvgpu: Improve accuracy of dGPU clk measurement"
...
The newly added nvgpu_current_time_ms API results in inaccurate time
measurements sometime which causes nvgpu_dgpu_freq_test.sh to fail.
Bug 2637525
Bug 200530176
This reverts commit 318d6451e9 .
Change-Id: I96279c556b3c044f590882b3bff358cfcb545ab1
Signed-off-by: Abdul Salam <absalam@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2147571
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2019-07-04 03:48:27 -07:00
ajesh
fa8e1904e2
gpu: nvgpu: fix CERTC violations in timers unit
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INT32-C requires that operations on signed integers do not result in
overflow.
Fix violations of INT32-C in timers unit.
Jira NVGPU-3605
Change-Id: I2d5ba6d1c2e3a84a5b3df1ecaf16cce13c1b2c97
Signed-off-by: ajesh <akv@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2139971
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2019-06-21 10:26:50 -07:00
Vaibhav Kachore
318d6451e9
gpu: nvgpu: Improve accuracy of dGPU clk measurement
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- This patch replaces "nvgpu_current_time_ms" with "nvgpu_hr_timestamp_us".
- "nvgpu_hr_timestamp_us" gives timestamp in microseconds and has better
accuracy than "nvgpu_current_time_ms" (which gives timestamp in millisecond)
Bug 200503143
Change-Id: I6a10e8e1b3e8ff842aa23f58bf2ba9344af232a6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2125959
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2019-06-21 10:25:48 -07:00
Vedashree Vidwans
6f37ac5de2
gpu: nvgpu: Disable logging for safety build
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This patch adds a conditional flag to filter out logging functions from
safety release build. Logging functions are replaced with stubs.
Jira NVGPU-869
Change-Id: If898b9ce8edb260727df28b407df83f0a92f61ad
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2109509
Reviewed-by: Alex Waterman <alexw@nvidia.com >
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2019-06-17 00:16:03 -07:00
Philip Elcan
e0fa45135a
gpu: nvgpu: timers: fix MISRA 5.5 violation
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MISRA Rule 5.5 requires identifiers be unique from macro names. The
struct timeout member max is renamed to max_attempts to fix the
violation.
JIRA NVGPU-3374
Change-Id: I701899e38a25b654d5f78feabbb273e21601f313
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2118815
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2019-05-15 12:15:16 -07:00
ajesh
fe9f1e9e5c
gpu: nvgpu: fix MISRA violations in timers unit
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MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. Fix the violations of MISRA rule 21.2 in timers unit.
Jira NVGPU-3139
Change-Id: I507d0f2a51e83ce24d642dcc81975aa513fa41eb
Signed-off-by: ajesh <akv@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2112599
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2019-05-06 12:07:16 -07:00
ajesh
1e158de579
gpu: nvgpu: use posix timers implementation for QNX
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Unify qnx timer unit with posix.
Jira NVGPU-2145
Change-Id: I6aa22fbfadf5245abda556877c8fa5233502117a
Signed-off-by: ajesh <akv@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2029170
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2019-03-29 13:34:15 -07:00
Adeel Raza
800d96865d
gpu: nvgpu: posix: MISRA rule 15.6 fixes
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MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the POSIX code.
JIRA NVGPU-775
Change-Id: Idafd5a5068c23b850ad1b0b083550a75b35588c1
Signed-off-by: Adeel Raza <araza@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2011739
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com >
Reviewed-by: Scott Long <scottl@nvidia.com >
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2019-02-05 19:23:58 -08:00
Philip Elcan
90024cb73a
gpu: nvgpu: misc MISRA 14.4 fixes
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This fixes a few lingering MISRA Rule 14.4 violations. Rule 14.4
requires that the condition of an if statement be a boolean.
JIRA NVGPU-1022
Change-Id: Ib6293e00e0436fceee9f7bf0ada1b6ac01a82faa
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1975424
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2018-12-19 11:24:42 -08:00
Nicolas Benech
4e41a0b199
gpu: nvgpu: Fix LibC MISRA 17.7 in os/posix
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Posix interface.
JIRA NVGPU-1036
Change-Id: I2da417edc992f16de24cdff536c0538f1fde8b61
Signed-off-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1929901
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2018-10-31 15:25:27 -07:00
Alex Waterman
b15624b39b
gpu: nvgpu: posix: move the posix dir to os
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Since the posix code is supporting a particular OS this code
should belong under os/ not common/.
Change-Id: Idf5f75b8ab9d614c9dd43ea23dab8df3c346c0ef
Signed-off-by: Alex Waterman <alexw@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1800658
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2018-08-17 13:54:25 -07:00