Commit Graph

6 Commits

Author SHA1 Message Date
Philip Elcan
e156066256 gpu: nvgpu: fuse: return int for cal APIs
The APIs read_vin_cal_slope_intercept_fuse() and
read_vin_cal_gain_offset_fuse() where prototyped for u32 return types,
but they were actually returning negative errno's for errors. Change the
return type to int so the errors can be checked properly.

clk_vin.c still stores the return values as u32's. This will be fixed in
a future patch.

JIRA NVGPU-938

Change-Id: I4fc47468dcf39f923c4f302919c705b50e10f446
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943383
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-08 21:42:59 -08:00
Amurthyreddy
1023c6af14 gpu: nvgpu: MISRA 14.4 boolean fixes
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.

Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.

JIRA NVGPU-1022

Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-07 10:35:22 -08:00
Srirangan Madhavan
ef5fdac7a6 gpu: nvgpu: Fix MISRA rule 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.

JIRA NVGPU-775

Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-05 22:13:16 -08:00
Debarshi Dutta
421e64aad7 gpu: nvgpu: move header location of gk20a.h
Update header path of gk20a.h in files present in common/
to <nvgpu/gk20a.h>

Jira NVGPU-597

Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832024
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-25 00:20:25 -07:00
Sai Nikhil
05f45bcfc3 gpu: nvgpu: MISRA 10.3 Conversions to/from char
MISRA Rule 10.3 states that the value of an expression shall not be
assigned to an object with a narrower essential type or of a
different essential type category.

We have cases where we are converting to/from char and non char types
and this fix 10.3 violations resulting from these conversions.

This also fix violations in conversions between s8 and non-s8 types
as s8 can be typedefed as char.

Jira NVGPU-1010

Change-Id: I150dd633eb7575de9ea2bedd598b7af74d1fcbd9
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801613
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-08-21 14:54:27 -07:00
Terje Bergstrom
227c6f7b7a gpu: nvgpu: Move fuse HAL to common
Move implementation of fuse HAL to common/fuse. Also implements new
fuse query functions for FBIO, FBP, TPC floorsweeping and security
fuses.

JIRA NVGPU-957

Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797177
2018-08-20 11:00:59 -07:00