Moved
-mmu_fault_pending mm ops to is_mmu_fault_pending mc ops
-mmu_fault_pending fb ops to is_mmu_fault_pending fb.intr ops. This
is needed to check if mmu fault intr is pending for volta onwards.
Added
is_mmu_fault_pending fifo ops. This is needed to check if mmu fault
interrupt is pending for chips prior to volta
JIRA NVGPU-1313
Change-Id: Ie8e778387cd486cb19b18c4aee734c581dcd9229
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094895
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Moved fb interrupt handling related code to fb intr sub-unit.
Moved following hals from fb hal to fb intr hal and renamed to:
void (*enable)(struct gk20a *g);
void (*disable)(struct gk20a *g);
void (*isr)(struct gk20a *g);
gk20a_readl/writel are replaced with nvgpu_read/writel.
Hals are populated with new function names and code is modified
to call new hals.
Moved ecc interrupt to gv11b_fb_intr_handle_ecc in a separate file:
fb_intr_ecc_gv11b.c/h
JIRA NVGPU-2034
Change-Id: I80c7110c902c4e082561cf7cbe65c20eb9acb661
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090070
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Move chip specific mc code from common/mc to hal/mc.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define
Change local variable names to fix checkpatch errors/warnings
Change BUG to WARN
Move defines to header files
Create new defines for hard coded delays
JIRA NVGPU-2041
Change-Id: I3594121a81da37ef58c47e87c45e96441e4cf8c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085268
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Moved following ltc related data to struct nvgpu_ltc
and has a reference to it from struct gk20a:
struct nvgpu_spinlock ltc_enabled_lock;
u32 max_ltc_count;
u32 ltc_count;
u32 slices_per_ltc;
u32 cacheline_size;
Added function remove_support for ltc and it is called
during nvgpu remove sequence.
Added following helper functions in ltc.h:
u32 nvgpu_ltc_get_ltc_count(struct gk20a *g);
u32 nvgpu_ltc_get_slices_per_ltc(struct gk20a *g);
u32 nvgpu_ltc_get_cacheline_size(struct gk20a *g);
Removed redudnant ltc.init_fs_state call from vgpu init
sequence since it is getting called from nvgpu_init_ltc_support.
NVGPU-2044
Change-Id: I3c256dc3866f894c38715aa2609e85bd2e5cfe5a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073417
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Currently ACR header files are part of "include/nvgpu/acr/" folder &
ACR interfaces are not used by any other UNIT which allows headers to
keep restricted to ACR unit, as ACR can be divided into two stage
process like blob preparation & bootstrap, so moved header files from
of "include/nvgpu/acr/" to "nvgpu/common/acr/" to respective blob/
bootstrap/acr header files along with its dependent interfaces, this
allows interfaces restricted to header file based on operation it does.
With this any access to ACR must go through provided public functions,
this header move change caused large code modification & required to
make it with big single CL to avoid build break.
JIRA NVGPU-2907
Change-Id: Idb24b17a35f7c7a85efe923c4e26edfd42b028e3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071393
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The fb APIs compression_page_size() and compression_align_mask() were
returning u32s, but the users all really need u64s.
This also eliminates MISRA Rule 10.3 violations for implicit casts to
smaller size objects.
JIRA NVGPU-2954
Change-Id: I8dc2b434d9564c89c0e8a1b19c4acbe167e339c1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075595
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