Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.
This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.
JIRA NVGPU-2042
Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
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vgpu_finalize_poweron_common calls g->ops.fifo.channel_resume.
This call is not valid anymore as no such function pointer exists.
Correct this by replace g->ops.fifo.channel_resume() by
g->ops.channel.resume_all_serviceable_ch()
Change-Id: I09fdfce64d48ec6971396fb2ecabc43051e9bf10
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102359
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g->ops.gr.get_preemption_mode_flags() hal is used to fetch information
on supported preemption modes and default preemption mode
Temporary struct nvgpu_preemption_modes_rec is used for this purpose
and is defined in gk20a/gr_gk20a.h right now.
Split above hal into two separate hals and move them to hal.gr.init unit
g->ops.gr.init.get_supported__preemption_modes()
g->ops.gr.init.get_default_preemption_modes()
These hals now return respective flags in pointers passed in function
parameter list, so there is no need to use temporary structure anymore
Hence delete struct nvgpu_preemption_modes_rec
Implement gm20b/gp10b chip specific hals in hal.gr.init unit.
Delete g->ops.gr.get_preemption_mode_flags() hal
Jira NVGPU-3126
Change-Id: I84f507fcd8d122bb7f0ecf697e8b4f16c9339ce1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102455
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Description:
Present p-state unit handle both pstate boardobj and
initializing all the units. As part of restructuring,
the pstate unit is separated into two units:
1) Perf_pstate: This unit will handle pstate boardobjs.
2) Pmu_pstate: This unit will initialize all the units
which supoort performance states.
Changes:
1) Created pmu_pstate unit.
2) Pstate boardobjs are moved under perf_pstate which
is under perf unit.
NVGPU-1958
Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096339
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Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:
int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
int nvgpu_gr_halt_pipe(struct gk20a *g);
HALs also moved accordingly and updated code to reflect this.
Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;
JIRA NVGPU-3168
Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
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Instead of using GPC and TPC counts to allocate memory
to hold sm info, use nvgpu_gr_config_get_no_of_sm() to get
the actual number. This fixes memory issues (corruption and
segmentation fault) seem when nvgpu_gpu_ioctl_wait_for_pause
is used.
Bug 2559631
Change-Id: Idcf9983fbbec7ec7f53835c59164e04bc45cd041
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102557
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Netlist names used across common and hal netlist units.
Hal units are having dependency only on this part of netlist.h
So moved netlist names defs to new header and included as required.
Also moved MAX_NETLIST_NAME define to netlist.c.
Fixed MISRA issues related to usage of "__max_name".
Fixed MAX_NETLIST_NAME length by adding "/" after chip architecture
name.
JIRA NVGPU-3108
Change-Id: I11c95c4d60ed48a9b3c0908ed8cbc7e736bd831f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100741
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Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo
Remove fifo.get_preempt_timeout
Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel
Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal
Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc
JIRA NVGPU-3144
Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Register gk20a non-arch-specific functions for gm20b
gpu_ops.fecs_trace,
Register nvgpu_os_linux_ops.fecs_trace.init_debugfs
gp10b_fecs_trace_flush is now replaced by gm20b_fecs_trace_flush in
fecs_trace_gm20b.* and the fecs_trace_gp10b.* files are removed.
Bug 2052906
Change-Id: Ie7598dbfe876e68ec0a1e2250dff9fa2de3c975f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088526
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- PG seq_buf is used to send command to PMU which is
related to ZBC and it is handled as part of PG state
machine path so moving seq_buf from struct nvgpu_pmu
to pmu_pg struct.
- Also, adding two new functions in PG unit:
nvgpu_pmu_pg_init_seq_buf() and nvgpu_pmu_pg_free_seq_buf()
to allocate and free up space for seq_buf respectively.
JIRA NVGPU-1954
Change-Id: I153879c5d0e72c39e6282e9db1b062facc7bf071
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094188
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Add esr_bpt_pending_events hal to report the type of
esr_bpt_pending_events to isr to process.
Add hal functions in gr instead of moving to gr.intr unit, as it
is part of non safety code.
JIRA NVGPU-1891
Change-Id: I70d75686042f97aa0e820d7982e95354971c9074
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100669
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.common.hal.fifo.runlist
- nvgpu.common.hal.fifo.fifo
JIRA NVGPU-3039
Change-Id: I9483f5cb623cfe36d6b26e41c33f124c24710c08
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098765
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void.
In the case of the gk20a_channel_get_timescale_from_timeslice, it
was always returning 0, so this patch changes the signature to return
void instead.
JIRA NVGPU-3039
Change-Id: Icff12af534ddae9929694f171b6a20ba359df7e7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098764
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Move all simulation related code to common sim unit.
Moved common/sim.c -> common/sim/sim.c
common/sim_pci.c -> common/sim/sim_pci.c
Also moved sim netlist related functionality also here. Because, sim
related code is not part of safety build and it will work as single
place-holder for all sim related code.
common/netlist/netlist_sim.c -> common/sim/sim_netlist.c
Changed function name for initializing sim netlist context vars and
moved it to sim.h from netlist.h
nvgpu_netlist_init_ctx_vars_sim -> nvgpu_init_sim_netlist_ctx_vars
JIRA NVGPU-2078
Change-Id: Ibe3452d1595ebd8cc08ce7bd186fdf4291e40ca6
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.hal.bus
- nvgpu.hal.fb
- nvgpu.hal.fifo
- nvgpu.hal.gr
JIRA NVGPU-3153
Change-Id: Iac9477ee7c36a0f2f8840e178dc5418e600f9c84
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100652
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. In the case of the gk20a_gr_debug_dump function, it
was always returning 0, so this patch changes the signature to
return void instead.
JIRA NVGPU-3153
Change-Id: I90173ba4e74fe045d9d6a819889d443f8423f34e
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100651
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gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars
struct so that any user could configure them through sysfs nodes
But the sysfs nodes are legacy and not being actively used by anyone.
Hence delete the sysfs nodes to configure these fields.
Since the gfxp timeout unit/count can now be statically programmed,
make following changes
- remove g->ops.gr.init_gfxp_wfi_timeout_count() hal
- remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal
- update g->ops.gr.init.preemption_state() hals to configure the values
using macros instead of caller passing the values
- update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values
using macros instead of caller passing the values
Finally, we don't need to store gfxp_wfi_timeout_count/unit fields
anymore, hence delete them from gr_gk20a.ctx_vars
Jira NVGPU-3112
Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100219
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Debug boolean flag dump_ctxsw_stats_on_channel_close is right now stored
in gr_gk20a.ctx_vars struct
This flag logically is property of gr.ctx units since it indicates
whether each context should dump ctxsw stats on channel/context close
Move this flag to struct nvgpu_gr_ctx_desc and remove it from
gr_gk20a.ctx_vars
Expose below API from gr.ctx unit to check if flag is set
nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of this variable from platform
specific probe functions
Jira NVGPU-3112
Change-Id: Id675e047237f82e9b8198a42082e99c95824578f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099399
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Debug boolean flags force_preemption_gfxp and force_preemption_cilp are
right now stored in gr_gk20a.ctx_vars struct
These flags logically are property of gr.ctx units since they indicate
whether each context should be forced to gfxp/cilp preemption mode by
default
Move these flags to struct nvgpu_gr_ctx_desc and remove them from
gr_gk20a.ctx_vars
Expose below APIs from gr.ctx unit to check if flags are set
nvgpu_gr_ctx_desc_force_preemption_gfxp()
nvgpu_gr_ctx_desc_force_preemption_cilp()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of these variables from platform
specific probe functions
Jira NVGPU-3112
Change-Id: I8b2de27f0c71dd2ea5abcf94221c2e15c80073ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099398
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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.
Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c
Call gr free before the gk20a free call in nvgpu_free_gk20a.
Rename struct gr_gk20a to struct nvgpu_gr
JIRA NVGPU-3132
Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Renamed and moved from fifo_gk20a.c to common/fifo/engines.c
gk20a_fifo_should_defer_engine_reset -> nvgpu_engine_should_defer_reset
Renamed and moved from fifo_gk20a.c to common/fifo/channel.c
gk20a_fifo_deferred_reset -> nvgpu_channel_deferred_reset_engines
JIRA NVGPU-1314
Change-Id: Ifc32ff4dde398143b83c2c1b6fab896142574240
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Rename the two native GPU GMMU map/unmap functions and update the
HAL initializations to reflect this:
gk20a_locked_gmmu_map -> nvgpu_gmmu_map_locked
gk20a_locked_gmmu_unmap -> nvgpu_gmmu_unmap_locked
This matches what other units do for handling vGPU "HAL" indirection.
Also move the function declarations to <nvgpu/gmmu.h> since these are
shared among all non-vGPU chips. But since these are still technically
HAL operations they should never be called directly. This is a bit of
an organixational issue that I have not thought through hwo to solve
yet.
Ideally they would go into a "hal/mm/gmmu/" include somewhere, but
that A) doesn't yet exist, and B) those are chip specific; these
functions are native specific. Ugh.
JIRA NVGPU-2042
Change-Id: Ibc614f2928630d12eafcec6ce73019628b44ad94
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099692
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In gk20a_open_new_channel(), grab the ref_obtain_lock
before marking the channel as referenceable/gettable
to ensure that the ref_count and referenceable flag
are set in a consistent manner. This will ensure that
a thread getting the channel asynchronously while it's
not fully initialized yet (e.g.,
gk20a_channel_semaphore_wakeup()) will always see a
valid ref_count
Bug 200427711
Change-Id: I55ff43f979e7e0a00a49feb2d24be25cec698d95
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
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nvgpu_log() was incorrectly casting the log_mask to a u32. log_mask
should be a u64. This patch resolves 2.2k CERT C INT31-C violations.
Rule INT31-C deals with integer conversions which can lead to lost or
misinterpreted data.
Change-Id: If308f5264e8a53f87ac63e4f6ce582d658ebb9ac
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098946
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Unify qnx types unit with posix. Modify certain defines as part of
unification. Modify the fecs trace function mmap_user_buffer to
not have OS specific structure as parameter. Rename the function
pointer mmap_user_buffer as get_mmap_user_buffer_info to reflect the
functionality handled by the function.
Jira NVGPU-2146
Change-Id: I58ec9bf23a435c039d1b5f04194f56067b11aa28
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082619
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Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception
Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx
JIRA NVGPU-1891
Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
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