MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I65c37f6b515aaa10c5945e9b68180e92e40c1f61
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939226
Reviewed-by: Automatic_Commit_Validation_User
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I70a2dded2e6cd5c04b54bf208d77a8d40a8f7af0
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933534
Reviewed-by: Automatic_Commit_Validation_User
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I1d71d7e62ce1a6331a4f33740a814bb3aa0309aa
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933533
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I1bca4258614d4c5feb75a47b3a98d2f385731bfb
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933532
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I7e39bc38b620c8a521a4a75d41379b8fb107f347
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933531
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: Ia0f4bcf1a8629d77ff9ae3c75e683ebd34929d7f
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933514
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I7ced14d6629e033b0ccef3a93a3dbf099e43ba4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946662
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gk20a.h depends on definition of struct therm_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I67010a979ed7f874070796dd834b9b3d1d9dad4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946661
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I2442eba6231c52cca2db0f0ed42cf0a419bc4c10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945307
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945286
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clk_gp106.h and clk_gv100.h define conflicting symbols, which prevent
including them both at the same time. One of the conflicting structs
is namemap_cfg, which has different definitions in clk_gp106.h and
include/nvgpu/clk.h.
Move all constants used only by clk_*.c to be defined there, delete
the extra namemap_cfg structure definition, and modify code to cope
with the unified namemap_cfg.
JIRa NVGPU-596
Change-Id: Id68919da4567ec1507eda0cfaa19bf047a7bfc59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945285
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MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations by casting them to an appropriate
type or using the relevant BITxx() macros.
JIRA NVGPU-666
Change-Id: I57b6081e9bd98c45ca9f7aa5f35e1d2d66ed0134
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945655
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.
JIRA NVGPU-1020
Change-Id: I6a756ee1bbb45d43f424d2251eebbc26278db417
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936334
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926820
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I4c04e2720a3b068909cc4af6847d4718568c13ea
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822740
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822587
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This macro helps us differentiate what to do with debugging
statements depending on OS. Different OSes have different
considerations for what to do when bad state in the driver
is detected.
JIRA NVGPU-1323
Change-Id: If435ef490146e87e809645453e8ac1065e13cace
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945144
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The APIs read_vin_cal_slope_intercept_fuse() and
read_vin_cal_gain_offset_fuse() where prototyped for u32 return types,
but they were actually returning negative errno's for errors. Change the
return type to int so the errors can be checked properly.
clk_vin.c still stores the return values as u32's. This will be fixed in
a future patch.
JIRA NVGPU-938
Change-Id: I4fc47468dcf39f923c4f302919c705b50e10f446
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943383
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This function returns a boolean describing if a given log
mask is enabled for a given GPU. Previously this returned
and int but the bool type is far better suited for this.
Also implement this function in posix, as it may be useful
to have implemented there if any common code chooses to
use this function.
Change-Id: I7382e73df83282763df1bdbccbbb219c9f3e6f1b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938341
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
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Add a fifo HAL for querying the doorbell token of a specific channel and
call it instead of doing the calculation directly. For Volta the token
is just the channel id plus the possible base number.
Bug 200145225
Change-Id: Ifbb150191575fdc72e413a14c799cab7e52d8c14
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849639
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Different SKUs may require different nvlink speed and hence the
nvlink speed value should come from VBIOS. The initpll number
corresponding to speed is present in VBIOS Low Power Nvlink table
header. Parse this data from VBIOS and set corresponding nvlink
speed and minion initpll DLCMD as default.
We can no longer update the GV100 VBIOS with necessary nvlink speed
value. Hence the hardcoding stays for GV100.
The nvlink speed should match across the endpoints. So in speed_config
fops, communicate the speed to nvlink core-driver for co-ordination
with Tegra endpoint.
Bug 2418403
Change-Id: Ib6f60951d4ca1c275968707d4cc6d738ba3a3f08
Signed-off-by: tkudav <tkudav@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.
JIRA NVGPU-775
Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
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pmuif structures refer to the ctrl structures, so that means that ctrl
structures are part of the pmuif. Move the headers to the right place
and update all include statements to include from the right place.
JIRA NVGPU-596
Change-Id: I7be1a727be654d58eccd0e12d599979687dd0733
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1934022
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in PMU files.
JIRA NVGPU-1036
Change-Id: Ie189acf13007f79a1046e8723cdec5b878d4ccc4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929904
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I9e18ffc961d485225732c34d3ca561e84d182d07
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921370
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All the netlist parsing code is currently under GR unit, but netlist
ucode parsing does not really have any logical dependency to GR
Hence separate out a new unit common/netlist/ that parses the netlist
image and stores/exposes its content through netlist_vars structure
Structure nvgpu_netlist_vars is added to structure gk20a
Move netlist parsing code to common/netlist/netlist.c and chip
specific files to common/netlist/netlist_<chip>.c
Move simulation netlist parsing to common/netlist/netlist_sim.c
Rename g.ops.gr_ctx HAL to g.ops.netlist
Rename all the exported structures to be in the form of nvgpu_*
Rename all exported functions to be in the form of nvgpu_netlist_*()
Add netlist initialization to GPU boot path, and add deinitialization
to GPU remove path
Jira NVGPU-1317
Change-Id: I9af86e3b3230a89db5260cc8ed96ff5f72938c9a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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In gk20a/gr_ctx_gk20a.c we right now directly read the GR register
gr_fecs_ctx_state_store_major_rev_id_r() which adds the dependency
to GR h/w header
Add a new HAL g.ops.gr.get_fecs_ctx_state_store_major_rev_id() to
read this register and use this instead
Also remove h/w header from gr_ctx_gk20a.c
Jira NVGPU-1317
Change-Id: Iab64fbfacff4d7ce4f3b61ca90b00ddc77e29551
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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-Add support for volt device OPERATION_TYPE_IPC_VMIN
support
-Added defines required for ipc vmin operation support
-Modified volt_get_voltage_device_table_1x_psv()
to add check to support IPC_VMIN & assign pwm source
based on operation type.
JIRA NVGPU-1156
Change-Id: Ia168669ea6b5896916747fccde8c6a52c271c4e3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Reduce the size of memory allocations in the channel debug dump by
capturing only the necessary values from the instance block. This also
simplifies the allocation path slightly with the downside of having to
add a capture_channel_ram_dump HAL for reading the interesting parts
explicitly beforehand to the now smaller staging buffer.
Also rename struct ch_state to struct nvgpu_channel_dump_info.
Jira NVGPU-886
Change-Id: I5d7518d9d474b0b728b183383bc83d89ecf91b98
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928207
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Sometimes longer 64-bit values are composed of pairs of low and high
parts in a same nvgpu_mem. Add a function to read the two and to do the
bit ops given the low and high word offsets.
Jira NVGPU-886
Change-Id: I4fe698d7c5a891ef5740ea0fb31549195e2e6c43
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928206
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MISRA rule 10.4 doesn't allow arithmetic conversions on operands of
different essential type category.
Fix violations where an arithmetic conversion is performed on boolean
and non-boolean types.
JIRA NVGPU-994
Change-Id: I2af9937678462b632bb6ec6178e10d02104fc3bc
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832337
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The only declaration from gr is struct nvgpu_gr_ctx and that can now be
forward-declared. Do that and remove the gr_gk20a include; add the
include to gk20a.h where it was missing.
Jira NVGPU-967
Change-Id: Idf77e7dc2ca043e9bbde9e9db03306fdd37e3c04
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822024
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Update the PD cache code to handle 64KB pages. To do this the
number of partial/full lists is expanded for when we have 64K
pages. Currently we only explicitly support 4K and 64K page
sizes. Other pages sizes (16K for example) will fail compilation
during preprocessing.
This change also cleans up the definitions for some of the
internal structs. They have been moved into pd_cache.c since
they are not used outside of pd_cache.c.
This allows the following functions to be removed from the global
context:
__nvgpu_pd_cache_alloc_direct()
__nvgpu_pd_cache_free_direct()
They have been replaced by calls to nvgpu_pd_{alloc,free}().
The nvgpu_pd_mem_entry alloc_map also had to be expanded to a
real bitmap. 32 or 64 bits is not sufficient for packing 256
byte PDs into a 64K page (there's 256 PDs per nvgpu_pd_mem_entry
in that case). To prevent doing too many find_first_zero
operations on the bitmap an 'allocs' field was also added which
tracks how many allocs are done. We can use this instead of
comparing a mask against the bitmap to determine if an
nvgpu_pd_mem_entry is full.
Note: there's still a limitation with the TLB invalidate code:
it simply assumes an nvgpu_mem is a 1 to 1 with a PDB. This means
we can't invalidate a PDB allocated at an offset greater than 0
in a nvgpu_pd_mem_entry. This in turn means we must always use a
full page size for a context's PDB.
Bug 1977822
Change-Id: I6a7a3a95b7c902bc6487cba05fde58fbc4a25da5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1718755
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Import userd and gpfifo buffers from userspace if provided via
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token
(i.e., the hw channel id) to userspace.
To keep the buffers alive, store their dmabuf and attachment/sgt handles
in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for
buffers that are mainly in kernel use. The buffers are freed via a new
API in the os_channel interface.
Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the
usermode gpfifo buffer.
Bug 200145225
Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795821
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
